Protecting Chips Against Hold Time Violations Due to Variability

Transcription

1 Protecting Chips Against Hold Time Violations Due to Variability

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3 Gustavo Neuberger Ricardo Reis Gilson Wirth Protecting Chips Against Hold Time Violations Due to Variability

4 Gustavo Neuberger Instituto Federal de Educação Ciência e Tecnologia do Rio Grande do Sul(IFRS) Campus Canoas Canoas, Rio Grande do Sul, Brazil Ricardo Reis Instituto de Informática Universidade Federal do Rio Grande do Sul (UFRGS) Porto Alegre, Brazil Gilson Wirth Depto de Eng Elétrica Universidade Federal do Rio Grande do Sul (UFRGS) Porto Alegre, Brazil ISBN ISBN (ebook) DOI / Springer New York Dordrecht Heidelberg London Library of Congress Control Number: Springer Science+Business Media Dordrecht 2014 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. Exempted from this legal reservation are brief excerpts in connection with reviews or scholarly analysis or material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Duplication of this publication or parts thereof is permitted only under the provisions of the Copyright Law of the Publisher s location, in its current version, and permission for use must always be obtained from Springer. Permissions for use may be obtained through RightsLink at the Copyright Clearance Center. Violations are liable to prosecution under the respective Copyright Law. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. While the advice and information in this book are believed to be true and accurate at the date of publication, neither the authors nor the editors nor the publisher can accept any legal responsibility for any errors or omissions that may be made. The publisher makes no warranty, express or implied, with respect to the material contained herein. Printed on acid-free paper Springer is part of Springer Science+Business Media (

5 To my parents Lotário and Isabel, who always gave me the support to follow my dreams. Gustavo Neuberger To my wife Mariana, who always gave me unconditional love and support. Gilson Wirth To my wife Lucia, to my daughter Mariana, to my sons Guilherme and Eduardo, and to my parents Constantino and Maria de Lourdes. Ricardo Reis

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7 Contents 1 Introduction: Process Variations and Flip-Flops Process Variability: Overview Sources and Types of Variations Lithography Doping Impact on Circuit Design Design Techniques with Process Variations Monte Carlo Simulations Corner Analysis Statistical Static Timing Analysis (SSTA) Flip-Flops and Hold Time Violations: Definitions Flip-Flop Timing Metrics Setup Time Hold Time Clock-to-Output Delay Data-to-Output Delay Delay Internal Race Immunity Hold Time Violations Circuits Under Test: For Characterization Inverter Sensitivity Flip-Flop Sensitivity Hold Time Violation Probability Test Circuits for Fabrication Measurement Circuits: For Precise Characterization Programmable Delay Line Ring Oscillator vii

8 viii Contents 5.3 Shift Register Final Circuit and Layout Experimental Results: Of Fabricated Circuits Measurement Flow and Setup Ring Oscillator Frequency Variability Hold Time Violation Distribution Comparisons Different Wafers of a Same Technology Different Technologies at Nominal Conditions Different Temperatures Different Vdd s Different Technologies at Same Vdd Systematic and Random Variability: Of Measured Results Separation Methods Separation Results Normality Tests: Of Measured Results The Tests Wilks-Shapiro Test Anderson-Darling Test Kurtosis and Skewness Analysis Normality Test Results Probability of Hold Time Violations: Of Short Logic Paths Simulation of Dependence of Race Immunity on Vdd Hold Time Violation Probability Using Simulated Data Hold Time Violation Probability Using Measured Data Dependency on Technology Dependency on Flip-Flop Strength Dependency on Vdd Dependency on Padding Dependency on Clock Skew Model Protecting Circuits Against Hold Time Violations: Due to Process Variability Motivation Protection Against Hold Time Violations Vdd Reduction Increasing Flip-Flop Race Immunity Padding... 93

9 Contents ix 11 Padding Efficiency: Of the Proposed Padding Algorithm Methodology Results Final Remarks References

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11 About the Authors Gustavo Neuberger Instituto Federal de Educação, Ciência e Tecnologia do Rio Grande do Sul (IFRS) Campus Canoas Canoas, Rio Grande do Sul, Brazil Ricardo Augusto da Luz Reis Professor at Universidade Federal do Rio Grande do Sul (UFRGS), Instituto de Informática, Graduate Program on Computer Science (PPGC) and Graduate Program on Microelectronics (PGMicro), Porto Alegre, RS, Brazil Gilson Inácio Wirth Departamento Engenharia Elétrica and Graduate Program on Microelectronics (PGMicro), Professor at Universidade Federal do Rio Grande do Sul (UFRGS), Escola de Engenharia, Porto Alegre, RS, Brazil xi