Design for Testability
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1 TDTS 01 Lecture 9 Design for Testability Zebo Peng Embedded Systems Laboratory IDA, Linköping University Lecture 9 The test problems Fault modeling Design for testability techniques Zebo Peng, IDA, LiTH 2 1
2 What is Testing? To examine a product to ensure that it functions correctly and exhibits the properties and capabilities it was designed to possess. Automatic Test Equipment Testing is an important activity in the life-cycle of an electronics product. Zebo Peng, IDA, LiTH 3 Life-Cycle of an Electronic System Specification Design Implementation Production Production Test Validation Verification Review Inspection Simulation Test Preparation and DFT Integration Test System Test Testing Operation and Maintenance Zebo Peng, IDA, LiTH 4 2
3 Causes of Incorrect Functions Design errors usually consistent Fabrication (manufacturing) errors often consistent, e.g., wrong components usually mistakes by operators Fabrication (manufacturing) defects inconsistent, e.g., impurity of materials Physical failures wear-out environmental factors defects Zebo Peng, IDA, LiTH 5 Defect Example Zebo Peng, IDA, LiTH 6 3
4 The Stuck-At Fault Model Every fault in a circuit changes its functionality as if some nodes were steadily tied to either logic 0 or 1. a b c S-A-0 o d N Total no of faults = 3-1 A single stuck-at model is usually used. That is, we assume that only one node at a time is tied to 0 or 1. Zebo Peng, IDA, LiTH 7 Single Stuck-At (SSA) Fault Model Number of possible faults is small (2N). Capable of representing many different physical faults. Test patterns produced for SSA faults detect also many other faults. Facilitate the use of Boolean algebra mathematics in deriving test patterns. Technology independent. SSA fault coverage remains an established metric for test quality, and is widely used in the industry. Zebo Peng, IDA, LiTH 8 4
5 Bridging Faults a b c AND An AND-bridging example o d Technology dependent (e.g., a short-circuit can lead to an AND-bridging, OR-bridging or dominance-bridging). Faults are related to the placement of the components. Fault activation and propagation are more difficult. Zebo Peng, IDA, LiTH 9 Composition of Costs of Testing Cost of test equipment (hardware): A test controller (usually a computer). Interface drivers and receivers and cable-connections. System of probe-contacts. A controlled environment (e.g., a temperature chamber). Cost of software supports: Test pattern generation programs. Test-design verification procedures (fault simulation and analysis). Testing time: Test development time. Test application time. ATE Zebo Peng, IDA, LiTH 10 5
6 Test = Optimization Testing and DFT are optimization problems: To minimize the total test cost, C(x), defined as: C test = C dev + C appl + C silicon + C quality Subject to a set of constraints, G i (x), i = 1,2, k test strategy and methods fault coverage requirement power consumption ATE and tool limitation test and DFT engineers Zebo Peng, IDA, LiTH 11 Types of Testing Production test testing of individual products to check whether faults are introduced during the manufacturing phase. It is assumed that the design is correct. System test testing of the product in the environment where it is operating to ensure that it works correctly when interconnected with other components. Burn-in testing at elevated temperature and voltage to accelerate and detect early life failures. Operation and maintenance test testing of the product in the filed for diagnosis or "preventive" purpose. Prototype test testing to check for design faults during the system development phase. Diagnosis is required. Zebo Peng, IDA, LiTH 12 6
7 Lecture 9 The test problems Fault modeling Design for testability techniques Zebo Peng, IDA, LiTH 13 Design for Testability (DFT) To take into account the testing aspects during the design process so that more testable designs will be generated. Advantages of DFT: Reduce test efforts. Reduce cost for test equipment. Shorten time-to-market. Increase product quality. Limitations: Hardware overhead, 5-30%, and performance degradation. Increased design complexity. Zebo Peng, IDA, LiTH 14 7
8 Controllability and Observability The key to design for testability is the ability to control and observe directly the internal states. Controllability of an internal node - ability to set it to a specific logic value. Observability of an internal node - ability to observe its specific logic value on primary output. a b c S-A-0 o d Zebo Peng, IDA, LiTH 15 Ad Hoc DFT Techniques Good design practices learnt through experience are used as guidelines: Test point insertion: OP C 1 C 2 C 1 C 2 a1 CP0 CP1 o1 (a) original design (b) 0/1-injection and observation Very simple. Can be used in principle anywhere. Large overhead of I/O ports (-> multiplexing and addressing) Zebo Peng, IDA, LiTH 16 8
9 Ad Hoc DFT Techniques (Cont d) Design circuits to be initializable. Provide easy reset. Eliminate asynchronous logic. Control/bypass internal clocks and oscillators. Clock Reset Zebo Peng, IDA, LiTH 17 Ad Hoc DFT Techniques (Cont d) Redundancy must be avoided or controlled. a b c 2 x 1 stuck-at-0 3 Stuck-at-0 on X is a redundant fault! a z 4 b c z z = ab + bc + ac = ab + ac A Hazard-Free Circuit High sequential depth should be avoided. Combinational feedback loops should be avoided since they result in additional hidden storage elements. Zebo Peng, IDA, LiTH 18 9
10 Disadvantages of Ad-Hoc Methods Experts and tools not always available. Test generation must often be manually performed with no guarantee of high fault coverage. Design iterations may be needed, which is very time consuming. Zebo Peng, IDA, LiTH 19 Structural DFT Techniques Can be applied to any design in a systematic way: Full scan. Partial scan. Boundary scan. Built-in self-test (BIST). Zebo Peng, IDA, LiTH 20 10
11 Basic Scan Technique Sequential circuits have poor controllability and poor observability. To address this problem, the flip-flops are connected into a long shift register. PI Combinational part PO PI Combinational part PO Scan Out In test mode, the flip-flops will be controlable and observable. Scan Out Scan In Scan In Zebo Peng, IDA, LiTH 21 Scan Design Circuit is designed using pre-specified design rules. Test structure is added to the completed design: Add a test control (TC) primary input. Replace flip-flops by scan flip-flops (SFF), and connect them to form one or several shift registers in the test mode. Make input/output of each scan shift register controllable/observable from PI/PO. Full scan = all flip-flops are included in the scan path: The problem of ATPG for sequential circuits is reduced to ATPG for combinational ones. Zebo Peng, IDA, LiTH 22 11
12 Scan Design Rules Use only clocked D-type of flip-flops for all state variables. At least one PI pin must be available for test; more pins, if available, can be used. All clocks must be controlled from PIs. Clocks must not feed data inputs of flip-flops. Zebo Peng, IDA, LiTH 23 Correcting a Rule Violation All clocks must be controlled from PIs. Comb. logic D1 CK D2 FF Comb. logic Comb. logic D2 D1 CK FF Comb. logic Zebo Peng, IDA, LiTH 24 12
13 Scan Flip-Flop (SFF) D Master latch Slave latch TC SD MUX CK D flip-flop CK Master open Slave open t TC Normal mode, D selected Scan mode, SD selected t Zebo Peng, IDA, LiTH 25 IO pins: One pin necessary. Area overhead: Scan Overheads Gate overhead = [4 Nff/(Ng + 10 Nff)] x 100%, where Ng = No. of comb. gates; Nff = No. of flip-flops. Example: Ng = 100k gates, Nff = 2k flip-flops, overhead = 6.7%. More accurate estimate must consider scan wiring and layout area. Performance overhead: Multiplexer delay added in combinational path; approx. two gate-delays. Flip-flop output loading due to one additional fanout; approx. 5-6%. Zebo Peng, IDA, LiTH 26 13
14 Partial Scan A subset of FFs is selected for the scan path. Advantages: reduced area overhead. avoid performance degradation. reduced test application time. Disadvantages: design time may increase. need a sequential ATPG tool. need a method for selecting the partial scan subset. Zebo Peng, IDA, LiTH 27 Partial-Scan Architecture PI PO Combinational circuit CK1 CK2 TC SCANIN FF FF SFF SFF SCANOUT Zebo Peng, IDA, LiTH 28 14
15 A Partial-Scan Method Select a minimal set of flip-flops for scan to eliminate all cycles. Combinational Alternatively, in order to keep the overhead low, only long cycles will be eliminated. In some circuits with a large number of self-loops, all cycles other than self-loops will be eliminated. Zebo Peng, IDA, LiTH 29 Partial Scan Example Circuit: TLC, 355 gates, 21 flip-flops Scan Max. cycle Depth* ATPG Fault sim. Fault ATPG Test seq. flip-flops length CPU s CPU s cov. vectors length , % % 247 1, % 136 1, % 112 1, % 52 1,190 * Cyclic paths ignored Zebo Peng, IDA, LiTH 30 15
16 Summary Testing is mainly used to find physical defects introduced during the manufacturing and operation phases. It is an expensive and complex task, and is becoming more and more difficult with the development of complex systems. Testability must be taken into account at all stages of the design and synthesis process. In particular, early testability consideration prevents costly design iterations. The key to successful testing lies in the design process! Zebo Peng, IDA, LiTH 31 16
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