Parallelization of Multimedia Applications by Compiler on Multicores for Consumer Electronics

Transcription

1 Vol. 0 No TV MPEG2 MP3 JPEG 2000 OSCAR API VLIW 4 FR1000 SH-4A 4 RP1 FR RP Parallelization of Multimedia Applications by Compiler on Multicores for Consumer Electronics Takamichi Miyamoto, Saori Asaka, Hiroki Mikami, Masayoshi Mase, Keiji Kimura and Hironori Kasahara Multicore processors have attracted much attention because there are much opportunity to overcome the increase of power consumption, the difficulity of improvement of processor clock speed and the increase of hardware/software developing period. Also speeding up multimedia applications is required with the progress of consumer electronics like mobile phones digital TV and games. This paper evaluates parallel processing performances of multimedia applications such as MPEG2 encode and decode, MP3 encode and JPEG 2000 encode using newly developed multicore API by OSCAR parallelizing compiler on the FR VLIW cores multicore processor developed by Fujitsu Ltd, and the RP1 4 SH-4A cores multicore processor jointly-developed by Renesas Technology Corp., Hitachi Ltd. and Waseda University. As the results, the OSCAR comiler gave us 3.27 speedup in average using 4 cores on FR1000 multicore, 3.31 speedup in average using 4 cores on RP1 multicore. 1. Waseda University OS Quad Xeon Core 2 Quad AMD Quad Phenom IBM Power6 Sun SPARC T2 SCE/IBM/ Cell 1) NEC /ARM MPCore MP211 2) FR1000 3) UniPhier 4) 1

2 SH-X3 5) DSP Intel SSE SIMD NEDO API API API The Multicore ASSOCIATION 6) API API API API OSCAR API FR1000 RP1 2 3 API API 4 OSCAR 5 FR1000 RP1 6 CMP (chip multiprocessor 0) 0 LPM/ I-Cache CPU LDM/ D-cache DSM Network Interface CSM / L2 Cache PE 0 PE1 PE n Intra-chip connection network (Multiple Buses, Crossbar, etc) m CSM Inter-chip connection network (Crossbar, Buses, Multistage network, etc) j I/O I/O Devices Devices k 1 OSCAR Fig. 1 OSCAR Multicore Architecture 2. NEDO API FR1000 MP211 CELL UniPhier API OSCAR OSCAR FR1000 OSCAR RP1 2.1 OSCAR OSCAR OSCAR 7),8) 1 OSCAR 1 PE PE LDM DSM LPM CPU DTU PE Interconnection Network CSM

3 Vol. 0 No. 0 3 Core 0 Primary I$:32KB WorkRAM D$:32KB 128KB Core 2 I$:32KB D$:32KB WorkRAM 128KB Chip Local Memory Bus Inter-Processor Communication Bus Main Memory Controller Internal DMAC WorkRAM 128KB WorkRAM 128KB Core 1 I$:32KB D$:32KB Core 3 I$:32KB D$:32KB snoop bus Core 3 Core 2 CPU FPU Core 1 CPU I$ FPU D$ 32K CCN Core 0 CPU I$ 32K ILRA FPU D$ CCN CPU I$ 32K FPU M DTU 32K OLRAM ILRA D$ CCN 16K 32K M 8K I$ DTU 32K OLRAM ILRA D$ CCN URAM 16K128K 32K M DTU 8K 32K OLRAM ILRAM 8K URAM 16K128K DTU OLRAM 8K URAM 16K128K URAM 128K snoop controller (SNC) DDR-SDRAM (off-chip CSM) 2 FR1000 Fig. 2 Block Diagram of FR FR1000 FR way VLIW FR KB 32KB OSCAR DSM 128KB WorkRAM 2 DTU DMAC off-chip CSM 2 1GB RP1 RP1 3 SH-4A SH- X3 4 32KB 32KB OSCAR LDM 16KB OLRAM LPM 8KB ILRAM DSM 128KB URAM on-chip CSM 128KB CSM SMP AMP SMP 3. API FR1000 RP1 API LBSC SRAM On-chip system bus (SHwy) DBSC DDR2 SDRAM CSM 128K 3 RP1 Fig. 3 Block Diagram of RP1 API OpenMP API 9) API C FORTRAN SMP OpenMP API API API 4 4 C FORTRAN OSCAR API C FORTRAN API API 4. OSCAR OSCAR 4.1 BPA

4 C 2 3 OSCAR Data Dependency Control Flow API Proc0 Scheduled Tasks Proc1 Scheduled Tasks... ProcN Scheduled Tasks Conditional Branch API API... API Data Dependency Extended Control Dependency Conditional Branch AND OR Original Control Flow (a) Macro Flow Graph(MFG) (b) Macro Task Graph(MTFG) - 5 Fig. 5 Macro flow graph and Macro-task graph FR1000 RP1 Z 4 API Fig. 4 Evaluation Flow on Multicores using Developed API RB SB 3 MT RB SB MT MT 5 a MFG 5 a MT MFG MFG MT MT MT 5 b MTG MFG MTG MTG MT ) DLG 4.3 PEPG MTG MT PG ETF/CP Earliest Task First/Critical Path DLG MT PG ETF/CP considering DLG PG PE 5. API FR1000 RP1 OSCAR OSCAR FR1000 RP1

5 4 MT52 8 MT56 MT51 MT55 MT50 MT MT53 Vol. 0 No. 0 5 void mpeg2decode() { unsigned char arr[16][22][16][16]; : for (i=0; i<16; i++) { process_slice(arr[i],...); } : } Process one picture Process one macroblock doall2 doall9 doall3 07 doall4 18doall25 doall2 doall5 29doall26 loop33 doall3 doall6 3doall20doall27 loop34 doall41 OSCAR Compiler doall7 4doall21doall28 loop35 doall42doall49 doall4 doall8 5doall22doall29 loop36 doall43doall50 void process_slice(unsigned char rarr[22][16][16],...); 6 OSCAR Fig. 6 Loop Description for Parallelization by OSCAR Compiler loop5 doall6 doall7 emt8 6doall23doall30 loop37doall44doall51 doall24doall31 loop38doall45doall52 doall32 loop39doall46doall53 loop40doall47doall54 doall48doall55 doall OSCAR C C OSCAR C MPEG2 MPEG2 MP3 JPEG2000 OSCAR MPEG2 MPEG2 DCT 7 MPEG2 Group of Picture GOP MPEG2 GOP 7 PE0 PE1 PE2 PE3 7 MPEG2 Fig. 7 Parallelization MPEG2 encode using Locality 0.0E+00 MT1 MT17MT25 MT2 MT18MT26 MT19MT27 MT20MT MT5 6 MT6 MT7 emt57 Processing macroblocks in parallel MT MT8 MT MPEG2 4PE Fig. 8 Scheduling Result of MPEG2 encode on 4PE MTG OSCAR MTG 8 4PE 8 PE MPEG2 MPEG2 6 MPEG2 11) 9 MTG OSCAR

6 8 7 6 MT Process one picture loop1 doall2 emt3 Inner Layer (Process one slice) sb1 bb2 sb3 doall4 doall5 doall7 doall6 OSCAR Compiler loop1 doall9 loop2 0 Process one slice loop3 1 3 loop4 loop5 2 loop6 loop7 4 loop8 5 Inner Layer sb1 bb2 sb3 doall4 doall5 doall6 doall7 doall8 doall Process some frames doall2 loop9 7 doall3 loop10doall258 doall4 loop119 doall33doall26 doall20 loop12 doall5 doall27 doall41doall34 loop2 doall3 doall4 doall5 Process one frame OSCAR Compiler doall28 loop13doall21 doall35 doall6 doall42 doall36doall29doall43 doall7 loop14 doall22 doall44doall37 doall8 loop15doall23doall30 doall45doall24 loop16 doall31 doall38 doall6 doall32 doall39 doall46 6 emt emt7 doall40 doall47 emt17 Process one macroblock 9 MPEG2 Fig. 9 Parallelization MPEG2 decode emt20 doall48 emt49 11 MP3 Fig. 11 Parallelization MP3 encode 10 Fig. 10 PE0 PE1 PE2 PE3 using Locality MT1 MT2 MT9 MT10 MT11 MT12 MT5 MT6 MT11 MT15 Processing slices in parallel MT7 MT7 MT8 MT13 MT19 MT8 MT12 MT14 Inner Layer MT15 MT16 MT9 MT13 MT16 MT5 MT17 MT10 MT14 MT6 MT18 using Locality MPEG2 4PE Scheduling Result of MPEG2 decode on 4PE MTG 10 4PE 10 PE MP3 MP3 5 MP3 MP3 11 MTG OSCAR MTG 12 4PE 12 PE0 PE1 PE2 PE3 using Locality MT1 MT2 0.0E+00 MT25 MT10 MT26 MT11 MT27 MT12 MT Processing frames in parallel 1MT5 2MT6 3MT7 4MT8 MT13 MT29 MT14 0 MT15 1 MT MP3 4PE Fig. 12 Scheduling Result of MP3 encode on 4PE PE JPEG 2000 JPEG 2000 DC DWT EBCOT Embedded Block Coding with Optimized Truncation 4 JPEG 2000 DWT 2 64x64 JPEG 2000 DC DWT EBCOT DWT 13 MTG OSCAR DC DWT

7 MT14 MT16 MT17 MT19 MT20 MT18 MT13 MT15 Vol. 0 No. 0 7 Process one picture doall2 doall3 doall4 doall5 doall6 doall7 loop8 loop9 emt10 OSCAR Compiler sb31 sb41 sb34 sb44 doall2 doall3 doall4 doall5 doall6 doall7 doall8 doall doall209 doall21doall22doall23doall24 doall25doall26doall27doall28 sb37 sb47 Process some lines sb38 sb48 sb36 sb46 emt49 sb35 sb45 sb29 sb39 sb32 sb42 Process one codeblock 13 JPEG 2000 Fig. 13 Parallelization JPEG 2000 encode Processing some lines and codeblocks in parallel PE0 PE1 PE2 PE3 MT1 MT5 MT9 MT2 MT6 MT10 MT7 MT11 MT8 MT12 0.0E MT29 MT21 MT22 MT23 MT24 MT25 MT26 MT27 MT sb30 sb40 sb33 sb JPEG PE Fig. 14 Scheduling Result of JPEG 2000 encode on 4PE EBCOT MTG 14 4PE MPEG2 MediaBench 12) MP3 UZURA MP3 encoder 13) JPEG 2000 JJ ) 5.1 C FR1000 MPEG2 DCT Intel ) MPEG2 30 SIF 352x240 MPEG2 30 SIF 352x240 MP3 32 PCM JPEG x300 JPEG 2000 OSCAR 5.4 FR FR1000 API gcc O3 API WorkRAM CSM API WorkRAM CSM MP3 gcc O0 OSCAR API 4PE 1PE MPEG MPEG MP JPEG CSM MP3 JPEG RP1 16 RP1 Speedup vs 1PE PE 2PE 3PE 4PE 1PE 2PE 3PE 4PE 1PE 2PE 3PE 4PE 1PE 2PE 3PE 4PE MPEG2enc MPEG2dec MP3enc JPEG 2000enc 15 FR1000 Fig. 15 Evaluation Result on FR1000 Multicore

8 RP1 SMP API SH SH C SMP OSCAR API 4PE 1PE MPEG MPEG MP JPEG SMP RP1 SMP JPEG PE 6. API OSCAR FR1000 RP1 FR1000 4PE 1PE MPEG MPEG MP JPEG RP1 4PE 1PE MPEG MPEG MP JPEG API OSCAR NEDO NEDO NEDO Speedup vs 1PE PE 2PE 3PE 4PE 1PE 2PE 3PE 4PE 1PE 2PE 3PE 4PE 1PE 2PE 3PE 4PE MPEG2enc MPEG2dec MP3enc JPEG 2000enc 1) Pham, D. et al.: The Design and Implementation of a First-Generation CELL Processor, In Proceeding of the IEEE International Solid- State Circuits Conference (2005). 2) Cornish, J.: Balanced Energy Optimization, International Symposium on Low Power Electronics and Design (2004). 3) Suga, A. et al.: FR-V Single-Chip Multicore Processor:FR1000, Fujitsu Sci Tech J, Vol. 42, No. 2, pp (2006). 4) : UniPhier, DA (2005). 5) Kamei, T.: SH-X3 : An Enhanced SuperH Core for Low-power MP Systems, Fall Microprocessor Forum 2006 (2006). 6) The Multicore ASSOCIATION: multicore-association.org/. 7) :,, Vol. 40, No. 5 (1999). 8) Kimura, K. et al.: Multigrain Parallel Processing on Compiler Cooperative Chip Multiprocessor, Proc. of 9th Workshop on Interaction between Compilers and Computer Architectures (INTERACT-9) (2005). 9) OpenMP Application Program Interface Version 2.5 (2005). 10) :,, Vol. 43, No. 4 (2002). 11) Iwata, E. et al.: Exploiting Coarse-Grain Parallelism in the MPEG-2 Algorithm, Technical Report CSL-TR (1998). 12) C. Lee et al.: MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems, 30th International Symposium on Microarchitecture (MICRO-30) (1997). 13) UZURA3:MPEG1/LayerIII Encoder in FOR- TRAN90. kitaurawa/index e.html. 14) R Grosbois et al.: 15) Intel: A Fast Precise Implementatioin of 8x8 Discrete Consine Transform Using the Streaming SIMD Extensions and MMX Instructions (1999). AP-922, Order Number RP1 Fig. 16 Evaluation Result on RP1 Multicore