Read-only memory (ROM) Digital logic: ALUs Sequential logic circuits. Don't cares. Bus

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1 Digital logic: ALUs Sequential logic circuits CS207, Fall 2004 October 11, 13, and 15, Read-only memory (ROM) A form of memory Contents fixed when circuit is created n input lines for 2 n addressable locations Number of output bits = size of each entry Each input in the truth table is represented in the addresses (all inputs represented) Each output in the truth table is represented in the contents (all outputs represented) Programmable ROM: can be changed or programmed if you know the contents 2 Don't cares Sometimes a function does not depend on certain combinations of inputs, or the result only depends on certain variables Don't cares (X) indicates these states in the truth table can be input or output Bus Collection of data lines that are treated as a single data line only works if each input line is independent of the others example: 32-bit multiplexor abstraction Bus means something entirely different for I/O (later) 3 4

2 Designing an ALU ALU must implement logic functions (AND, OR, etc.) arithmetic functions ALU does not implement shifts can be done faster with special shifting hardware than by adding Derive 1-bit ALU first, then 32-bit ALU 1-bit ALU: addition Three inputs: A, B, CarryIn Two outputs: Sum = A'B'CarryIn + A'BCarryIn' + AB'CarryIn' + ABCarryIn CarryOut = BCarryIn + ACarryIn + AB Multiplexor: Line 2 = addition line 0 = AND, line 1 = OR bit ALU 32-bit ALU 32 1-bit ALUs CarryOut is propagated from least significant bit to most significant bit ripple carry adder Subtraction: A B = A + B' = CarryIn for least significant adder Source: Patterson and Hennessy, Computer Organization and Design: The Hardware/Software Interface, 3 rd ed. 7 8

3 32-bit ALU Other MIPS ALU operations slt: subtract the operands, take the sign, compensating for overflow conditional branches: test for zero OR all inputs and then invert (1 = no bits are set = zero) Source: Patterson and Hennessy, Computer Organization and Design: The Hardware/Software Interface, 3 rd ed Clock Signal with a cycle time (frequency) that oscillates between high and low values must be long enough for inputs Used to synchronize sequential logic gates state changes occur on an up or down edge (edgetriggered) samples the digital signal Memory (sequential) devices Flip-flops Latches Registers 11 12

4 S-R (set-reset) latch Unclocked memory device Basis for more complicated flip-flops and latches Flip-flop Output = value of the stored state inside the device Internal state changes on clock edge R S Q Q' 0 0 previous value previous value unstable unstable Source: Patterson and Hennessy, Computer Organization and Design: The Hardware/Software Interface, 3 rd ed Latch Output = value of the stored state inside the device Internal state changes when one or more inputs change AND the clock signal is high D latch Stores the value of the input signal when the clock signal is high Timing diagram 15 Source: Patterson and Hennessy, Computer Organization and Design: The Hardware/Software Interface, 3 rd ed. 16

5 D flip-flop Output is stored on the falling clock edge D latches are in a master-slave configuration Application: shift register 32 D flip-flops Output (Q) of {left, right} flip-flop connected to input (D) of {right, left} flip-flop Circular shift: connect output (Q) of last flip-flop to input (D) of first flip-flop Timing diagram Q changes as clock signal moves from high to low Source: Patterson and Hennessy, Computer Organization and Design: The Hardware/Software Interface, 3 rd ed Memory elements SRAM: static random access memory fixed access time fixed number of addressable locations and memroy widths DRAM: dynamic random access memory data storage = charge on a capacitor must be periodically refreshed (capacitors slowly discharge) by reading the contents and writing them back occurs once every several milliseconds Error detection and correction Parity code: count of the number of 1's in a sequence of bits odd parity: number of 1's is odd (parity bit = 1) even parity: number of 1's is even (parity bit = 0) Parity bit can be used for error detection or correction 1 parity bit can detect an odd number of errors more bits required for error correction 19 20

6 Finite state machine A sequential logic function that contains: Set of states: all possible values that can be stored Next-state function: maps current state and inputs to new state Output function: maps current state and inputs to a set of (asserted) outputs Finite state machines are synchronous State changes on clock cycle New state is computed once per clock cycle Used to control processor, datapath (more in Chapters 5-6) Note: there are asynchronous finite state machines too Source: Patterson and Hennessy, Computer Organization and Design: The Hardware/Software Interface, 3 rd ed Some applications of FSMs Life behaviors (sleep patterns, etc) Networking Pattern matching Large complex systems User interface design Video game logic AI Types of finite state machines Moore machine: output function only depends on current state Mealy machine: output depends on current state and current inputs 23 24

7 Finite state machine: example 2-bit counter States: 00, 01, 10, 11, 00,... Outputs: 00, 01, 10, 11, 00,... No inputs (changes occur on clock cycle) Implementation: bit0 inverts on every clock cycle, bit1 inverts on every other clock cycle Field programmable devices Non-custom integrated circuit Contains combinational logic gates and memory devices programmable logic devices: combinational gates only field programmable gate arrays: combinational gates and flip-flops Programmable by user Field programmable devices (cont.) Static gates and registers Connections permanent: connection between two wires (antifuse) temporary: SRAM FPGAs are actually mini-programmable RAMs! 27

COMP2611: Computer Organization. Introduction to Digital Logic

1 COMP2611: Computer Organization Sequential Logic Time 2 Till now, we have essentially ignored the issue of time. We assume digital circuits: Perform their computations instantaneously Stateless: once