EUV Mask and Wafer Defectivity: Strategy and Evaluation for Full Die Defect Inspection

Transcription

1 EUV Mask and Wafer Defectivity: Strategy and Evaluation for Full Die Defect Inspection Ravi Bonam 1, Hung-Yu Tien 2, Acer Chou 2, Luciana Meli 1, Scott Halle 1, Ivy Wu 2, Xiaoxia Huang 2, Chris Lei 2, Chiyan Kuan 2, Fei Wang 2, Daniel Corliss 1, Wei Fang 2, Jack Jau 2, Zhengqing John Qi 3, Karen Badger 3, Christina Turley 3 and Jed Rankin 3 1 IBM Research, 257 Fuller Rd, Albany, USA 2 Hermes Microvision, 1762 Automation Pkwy, San Jose, USA 3 GLOBALFOUNDRIES Inc., 1000 River St, Burlington, VT, USA ABSTRACT Over the past few years numerous advancements in EUV Lithography have proven its feasibility of insertion into High Volume Manufacturing (HVM). 1, 2 A lot of progress is made in the area of pellicle development but a commercially solution with related infrastructure is currently unavailable. 3, 4 Due to current mask structure and unavailability of a pellicle, a comprehensive strategy to qualify (native defects) and monitor (adder defects) defectivity on mask and wafer is required for implementing EUV Lithography in High Volume Manufacturing. In this work, we assess mutltiple strategies for mask and wafer defect inspection including a two-fold solution to leverage resolution of e-beam inspection along with throughput of optical inspection are evaluated. Defect capture rates for inspections based on full-die, critical areas based on priority and hotspots based on design and prior inspection data are evaluated. Each strategy has merits and de-merits, particularly related to throughput, effective die coverage and computational overhead. A production ready EUV Exposure tool was utilized to perform exposures at the IBM EUV Center of Excellence in Albany, NY for EUV Lithography Development along with a fully automated line of EUV Mask Infrastructure tools. We will present strategies considered in this study and discuss respective results. The results from the study indicate very low transfer rate of defect detection events from optical mask inspection. They also suggest a hybrid strategy of utilizing both optical and e-beam inspection can provide a comprehensive defect detection which can be employed in High Volume Manufacturing. Keywords: EUV Lithography, EUV Mask, E-beam Inspection, Die-Die, Die-Database, EUV Etched Wafer, Etch Pattern 1. INTRODUCTION EUV Lithography is without doubt the foremost adoptable optical lithography solution for sub-20nm pattern fabrication by the semiconductor industry. Defectivity on masks is major challenge for insertion into High Volume Manufacturing. Unavailability of a commercial pellicle solution, actinic inspection tools on EUV masks has made critical defect detection and mitigation a major challenge. E-beam (electron beam) inspection offers high resolution for defect detection and has been shown to detect sub-10nm defects 5 on resist patterns. A known drawback of using e-beam inspection is its throughput but multiple strategies such as hot-spot inspection, design derived care area etc., have been proposed to provide improved throughput. 8 Currently, e-beam inspection is widely used as yield monitor in semiconductor manufacturing industry. Design errors, pattern defects and surface defects are captured through optical mask inspection post EUV mask fabrication. 10 An approximate signature of buried defects can also be captured by mask optical inspection in a phase contrast mode. This information can assist mask known defect locations to filter out process and mask use added defect data. 7 Prior to usage of the mask in production environment, comprehensive mask defectivity information is required with a minimum detection resolution targeted below printable wafer pattern Send correspondence to: Ravi Bonam : rkbonam@us.ibm.com Extreme Ultraviolet (EUV) Lithography VII, edited by Eric M. Panning, Kenneth A. Goldberg. Proc. of SPIE Vol. 9776, 97761C 2016 SPIE CCC code: X/15/$18 doi: / Proc. of SPIE Vol C-1

2 dimensions. As initial mask qualification requires the need for complete defectivity information, we use e-beam mask and wafer defect inspection to qualify the mask, also leveraging optical mask defect inspection. This generates an initial reference state for the mask. As the mask is qualified for use, an optical wafer inspection tool is utilized to monitor defectivity on the mask by inspecting patterned wafers. The optical patterned wafer inspection tool has the capability of comparing current die inspection data to a golden wafer virtual die. 9 This Virtual Die feature captures the initial/qualified state of the printed patterned defect of the mask and it can be compared to successive patterned wafers. This enables detection of random and repeater type defects as the mask is utilized of patterning. 2. EXPERIMENTAL SETUP A production ready EUV lithography tool 1 at College of Nanoscale Science and Engineering, SUNY Polytechnic Institute was used to pattern silicon wafers. A fully automated suite of mask infrastructure tools were utilized for mask inspection, cleans, handling and storage. Wafers were coated high resolution EUV resist on an etch stack consisting of a Silicon containing hard mask and an organic underlayer to facilitate pattern transfer. Figure 1 illustrates EUV mask qualification strategy post mask delivery. Due to unavailability of actinic inspection tool, printability assessment of defects requires high resolution inspection at all possible defect locations. As shown in the figure, full die, priority care areas or hotspots type inspections can be performed with e-beam inspection. In this study, we evaluated this strategy on 10 Back End of the Line (BEOL) EUV mask levels which are part of an integrated device maskset. As the masks were received, all three e-beam inspection strategies were applied to assess differences in defect detection. Mask Inspection (optical) Defect Map (buried and surface) 1 Scanner exposure (through focus) Optical wafer inspection E -beam wafer inspect Full Die Critical Areas - Macro and priority based Hotspots - Design and Inspection data aided Mask Ready for production E -beam mask inspection Mask Ready for re -entry Mask Clean Figure 1. EUV Mask Qualification Strategy to assess and record native defectivity state Along with mask qualification it is critical to monitor for particle defectivity (adders) as they are utilized for patterning and other mask operations. Figure 2 illustrates a strategy for monitoring the state of a mask to its qualified state which was saved as virtual reference. In this work, this strategy was successfully implemented and validated on product and monitor masks. Proc. of SPIE Vol C-2

3 Scanner exposure Optical {et inspection E -beam wafer inspect Mask Ready for Production E -beam mask inspection Mask Ready for re -entry Mask Clean Figure 2. EUV Mask Monitor Strategy to detect particle adders An e-beam inspection tool 6, 12 was used to perform inspection on patterned wafers. The wafer inspection tool has two modes of inspection, Die-Die and Die-Database, and both were evaluated for sensitivity, capture efficiency and throughput. The e-beam wafer inspection tool as shown in Figure 3a utilized in this work is capable of performing Die-Database inspection in multiple modes. It can capture large areas and stitch multiple fields together, generate care-areas from design layers and also perform targeted hot-spot inspections as shown in Figure 3b. TFE source Magnetic Lens Detector Laser Blanker I 1 I I Stigmator uu N N u u E1 EI... _... Wafer /Mask Large Area Notspot Inspection TIMINIBION J Figure 3. E-beam Wafer and Mask Inspection tool, a. Block diagram of e-beam inspection tool and capability to perform, b. Large area Die-Database inspection c. Hot-spot Inspection Figure 4 illustrates two steps in the Die-Virtual Reference optical inspection, Step I indicates recording native state of the mask as it transfers to the wafer and Step II shows the recorded virtual reference being compared to follow on wafers to detect mask adder events. In this process inspection is performed based on averaging multiple die, as indicated in Figure 4a, in this case a row of seven die are utilized. It was reported in a recent study [3], defect printability on wafer has a non-linear trend and as a result of post-exposure processing effects their dimensions are much larger than predicted from optical simulations. Proc. of SPIE Vol C-3

4 STEP II b sca n detector filters Scan chips Across row NEMBININ "defect" wafer a STEP I Reference wafer Additive Reticle repeater SRD training => b "Native" Reticle repeater Random defect Average Virtual Reference Die Image "Native" Reticle repeater Additive Reticle repeater Average Test Image Comparison to Virtual Reported defects (KLARE) Per Chip Row Reference Die Image i Figure 4. Optical Inspection, a. Step 1 - Process to record native state of mask, b. Step II - Inspection process compares wafer defect signature to native state recorded in Step I Figure 5a show plot of mask defects from optical mask inspection. These defects locations were tracked from post Multilayer deposition, Absorber deposition, Blank Inspection (Phase contrast) to Patterned inspection. Some defect locations indicated in the plot are shown to propagate from blank deposition to pattern fabrication. An example of such a defect is shown in Figure 5b, which and is considered to be a yield limiter type defect. Figure 5c shows defect locations obtained from mask inspection marked on design as hot-spots along with a few critical areas marked based on designer priority. 3. RESULTS AND DISCUSSION In this study, aforementioned strategies for EUV mask qualification and monitor on 10 integrated BEOL levels. EUV masks ahead of exposures on the scanner are processed through a backside optical inspection. Figure 6a illustrates backside inspection defects post multiple uses on EUV exposure tool. Figure 6b shows review images of clamp events and cleanable adder defects. The challenge is differentiation between them as spatial signature is similar although clamp indentations are of very low concern to cause imaging impact. There are about 5% of particle defect events which have the potential to cause image placement error and are removable through a cleans process. Mask defect maps from blank inspection (phase contrast), pattern inspection were translated to wafer coordinates and e-beam hot-spot Die-Database inspection was performed to assess defect transfer rate. Figure 7 shows defects detected at mask house blank and pattern inspection and respective wafer transfer data. It is evident from the plot that there is insignificant transfer rate of defects detected in this mode. Inset also shows two defects detected at blank and pattern mask inspection respectively and were found to transfer to wafer. It was also confirmed from this study that defects detected at blank and pattern mask inspections had a 100% transfer rate to wafer prints. E-beam inspections were performed at 5 and 10nm pixel sizes and with different frame averages to compare capture efficiency which was found to be similar. Another important aspect to be considered is the mask defect detections to wafer transfer rate over all three strategies as shown in Figure 8. Full Die and Hotspot inspections based on mask defect locations indicate similar defect capture on wafer prints. Lower defect capture rate is reasonable in Priority care areas as they only cover 25% of die area. Proc. of SPIE Vol C-4

5 . 12, 10' Mask Defects Plot S O p Absorber Mulöayer Blank Patterned VC Mask Defects Translated to Design Notspots O o O ö Mask X Dimension (ms) x 10' t si i.s.s `.i' m Mask SEM review :n. et! +-LR tr) 11,0 "irktin t.i tiallettat11_41tivii Wafer e -beam inspection Large shaded areas - EUV1 markers, Scattered green boxes - Possible buried defect locations marked for Die -Db wafer inspection Figure 5. a. Mask defect maps from multiple inspections overlayed spatially at mask dimensions, b. Shows an example of buried defect detect at pattern mask inspection and respective wafer print detected from Die-Database inspection, c. A full die design with transformed mask defects marked on a layer to enable hot-spot inspection, also shows large areas marked based on priority 30 Mask Backside - Cleanable ( >5um) Defects o 15 5 A10 5 I I iiihili 0 #1 #3 #5 #7 #9 #1 #3 #5 #7 #9 #1 #3 #5 #7 #9 a L1 L2 L3 Mask Level / Inspections J Figure 6. a. Mask backside inspections on a few mask levels indicating cleanable defects greater than 5 microns, b. Optical review images of clamp indentations and particle adder defects Post qualification, mask monitoring is essential to detect particle adders as it is processed through wafer exposures and mask operations. As illustrated in Figure 2, qualified mask exposures were recorded as virtual reference and used to compare follow on exposures. Results from the applied strategy over a few weeks are shown in Figure 9, indicate native defects along with adder defects. Some detection variability can be noticed in the plot which is related to print variations as well as inherent defect capture rate of the tool. Post Wk15, the mask was processed through a wet cleans process which successfully restored native defectivity state of the mask. This can be clearly seen in the adder section of the plot and validates aforementioned strategy in detecting adder defects. Proc. of SPIE Vol C-5

6 !!!' Mask to Wafer Defect Transfer 100 Patterned Defects(Madt) 10 I i Blank Defects(Madt) Wafer Defects L2 L3 L4 LS L7 L9 EUV BEOL Levels L10 Figure 7. Plot of Patterned mask defect, buried defects and respective defect transfer to wafer 35 a, 30 C 7 V 25 V,v 20 Ol,- 15 ila' Q 10 cc 5 0 L1 E -beam Inspection Evaluation- EUV Mask Qual Id Ill Li L3 L4 L5 L6 L7 L8 L9 L10 EUV Mask Levels Full Die Priority Care Areas (25 %) HS (Optical Mask) Figure 8. Plot indicates native mask defect detection across multiple strategies, Full Die, Priority care area and Hotspots based on prior mask defect information Mask clean Natives Mask Adder iii:iiiiihhiiiiiiii Wkí Wk2 Wk3 Wk4 Wki Wk2 Wk3 Wk4 Wk5 Wk5 Wk6 Wk7 WkS Wk9 Wk10 Wkll Wk12 Wk13 Wk14 Wk15 Figure 9. Illustration of Die-Virtual reference optical wafer inspection data on a monitor mask over a few week indicating multiple adder detections and native state restoration post mask cleans Figure 10 shows a patterned mask monitored over the course of its usage on the EUV exposure tool. Defect detected was characterized and predominant material was identified as carbon. Post mask clean native Proc. of SPIE Vol C-6

7 defectivity state was restored as indicated in the plot. The plot indicates very low adders over long term usage of the mask in the EUV exposure tool as well as through mask operations. 7 e, g 6 V 4 2 a _111 Mask Adder Natives -Wafer Count Wk2 WK3 Wk4 Wk5 Wk6 r Wk7 Wk8 Wk e a o b Wafer Mask Dominant material identified as C Figure 10. a. Plot showing defect data from a mask 4. CONCLUSION Defect inspection strategies presented in this work indicates a feasible solution to qualify and monitor mask defectivity in a high volume manufacturing environment. Resolution and throughput of e-beam and optical respectively, can be utilized in tandem to provide comprehensive printable defect detection. In house Mask Infrastructure tools (Inspection, Cleans and Handling) provided the capability of restoring native mask defectivity state which is required post detection. Mask Backside inspection also indicated very low particle defects It can be inferred from figures 8, 7 that defect capture rate in targeted hotspots based on optical mask inspection is equivalent to full die e-beam inspection. Another important conclusion is defect transfer rate from detections identified from optical blank and pattern inspection are less than 1%. Most defects detected using blank defect inspection are also detected in patterned mask inspection, indicating very insignificance of blank mask inspection in phase contrast mode. It was reported in a recent study [3], defect printability on wafer has a non-linear trend and as a result of post-exposure processing effects their dimensions are much larger than predicted from optical simulations. This works as an advantage of using optical inspection for adder detection in this strategy. Results from this study indicate a plausible defectivity solution in the absence of a pellicle and actinic inspection tool. ACKNOWLEDGMENTS This work is a result of a joint development activity between IBM and Hermes Microvision Inc and it was performed by Research and Development Alliance Teams at IBM facility at Albany, NY. The authors would like to acknowledge Derek Tomlinson, Ray Zhang, Yan Zhao from Hermes Microvision Inc. REFERENCES [1] R. Peeters, et al. EUV lithography: NXE platform performance overview. SPIE Advanced Lithography. International Society for Optics and Photonics, [2] A. Pirati, et al. Performance overview and outlook of EUV lithography systems. SPIE Advanced Lithography. International Society for Optics and Photonics, Proc. of SPIE Vol C-7

8 [3] D. Goldfarb, Fabrication of a full-size EUV pellicle based on silicon nitride. SPIE Photomask Technology. International Society for Optics and Photonics, [4] C. Zoldesi, et al. Progress on EUV pellicle development. SPIE Advanced Lithography. International Society for Optics and Photonics, [5] R. Bonam, S. Halle, D. Corliss, H. Tien, F. Wang, W. Fang, and J. Jau, E-beam inspection of EUV programmed defect wafers for printability analysis. In Advanced Semiconductor Manufacturing Conference (ASMC), 24th Annual SEMI, pp IEEE, [6] R. Bonam, et al. E-beam inspection of EUV mask defects: To etch or not to etch?. SPIE Advanced Lithography. International Society for Optics and Photonics, [7] K. Seki, et al. Printability of buried extreme ultraviolet lithography photomask defects. Journal of Micro/Nanolithography, MEMS, and MOEMS 15.2 (2016): [8] O. D. Patterson, J. Lee, M. D. Monkowski, D. A. Ryan, S. Chen, S. C. Lei et. al., E-beam inspection system for comparison of wafer and design data, Proc. SPIE 8324, Metrology, Inspection, and Process Control for Microlithography XXVI, pp J-83242J-9, March, 2012 [9] S. Halle, et al. Toward defect guard-banding of EUV exposures by full chip optical wafer inspection of EUV mask defect adders. SPIE Advanced Lithography. International Society for Optics and Photonics, [10] J. Rankin, et al. EUV photomask defects: what prints, what doesn t, and what is required for HVM. SPIE Photomask Technology. International Society for Optics and Photonics, [11] K. Cho, J. Park, C. Park, Y. Lee, I. Kang, J. Yeo et. al., The analysis of EUV mask defects using a wafer defect inspection system, Proc. SPIE 7636, pp E-76361E-15, March, 2010 [12] X. Liu, X. Zhang, Y. Zhao, A. Desai, Z. W. Chen, Low energy large scan field electron beam column for wafer inspection, Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, vol. 22, no. 6, pp , November, 2004 [13] Z.W.Chen, Swinging objective retarding immersion lens electron optics focusing,, US Patent# , June, 2003 Proc. of SPIE Vol C-8