INTER-PROCESS COMMUNICATION AND SYNCHRONISATION: Lesson-12: Signal Function

Size: px
Start display at page:

Download "INTER-PROCESS COMMUNICATION AND SYNCHRONISATION: Lesson-12: Signal Function"

Transcription

1 INTER-PROCESS COMMUNICATION AND SYNCHRONISATION: Lesson-12: Signal Function 1

2 1. Signal 2

3 Signal One way for messaging is to use an OS function signal ( ). Provided in Unix, Linux and several RTOSes. Unix and Linux OSes use signals profusely and have thirty-one different types of signals for the various events. 3

4 Signal A signal is the software equivalent of the flag at a register that sets on a hardware interrupt. Unless masked by a signal mask, the signal allows the execution of the signal handling function and allows the handler to run just as a hardware interrupt allows the execution of an ISR 4

5 Signal Signal is an IPC used for signaling from a process A to OS to enable start of another process B Signal is a one or two byte IPC from a process to the OS. 5

6 Signal Signal provides the shortest communication. The signal ( ) sends a one-bit output for a process, which unmasks a signal mask of a process or task (called signal handler) The handler has coding similar to ones in an ISR runs in a way similar to a highest priority ISR. 6

7 Signal An ISR runs on an hardware interrupt provided that interrupt is no masked. The signal handler also runs on signal provided that signal is no masked 7

8 Signal Signal ( ) forces a signaled process or task called signal handler to run. When there is return from the signaled or forced task or process, the process, which sent the signal, runs the codes as happens on a return from the ISR. 8

9 Signal... OS connects a signal to a process or ISR j (called signal handler function), and resets the signal mask of j. Then the j runs after all higher than j priority processes (or ISRs) finish. 9

10 Signal... An OS provision for signal as an IPC function means a provision for interrupt-message from a process or task to another process or task 10

11 Signal ( ) IPC function 1. SigHandler ( ) to create a signal handler corresponding to a signal identified by the signal number and define a pointer to signal context.. The signal context saves the registers on signal. 2. Connect an interrupt vector to a signal number, with signaled handler function and signal handler arguments. The interrupt vector provides the program counter value for the signal handler function address. 11

12 Signal ( ) IPC functions 3. A function signal ( ) to send a signal identified by a number to a signal handler task 4. Mask the signal 5. Unmask the signal 6. Ignore the signal 12

13 2. Comparison between signal and semaphore 13

14 Signal and Semaphore Some OSes provide the signal and semaphore both IPC functions Every OS provides semaphore IPC functions. When the IPC functions for signal are not provided by an OS, then the OS employs semaphore for the same purpose. 14

15 Task A sending signal s B to initiate Task B (signal handler) to run Task A OS signal mask B Task B start B Send s B 15

16 Task A sending semaphore as event flag sem i to initiate a task section waiting to take sem i before it could run Task A OS signal mask B Task B Wait sem i = 0 sem i = 1 sem i Take Start Release sem i sem i 16

17 3. Example of using signal ( ) 17

18 Signal ( ) Example Handling of exception. An exception is a process that is executed on a specific reported run-time condition. 18

19 Signal ( ) Example A signal reports an error (called 'Exception') during the running of a task and then lets the scheduler initiate an error-handling process or ISR, for example, initiate error-login task. - Handling of signal is similar to an ISR handling function using an interrupt vector. 19

20 4. Advantage of using a Signal 20

21 Advantage of using a Signal Unlike semaphores, it takes the shortest possible CPU time. The signals are the flag or one or two byte message used as the IPC functions for synchronizing the concurrent processing of the tasks. 21

22 Signal handler Tasks B, C, and D Synchronizing their execution by signals s1, s2 and s3 Task A Task B Start B Task C Start C Task D Start D Send s1 Send s2 Send s3 22

23 Task i sending signal s to initiate signal handler ISR j Execute signal ( ) Task i OS signal mask j ISR j start j Send s j Return 23

24 Advantage of using a Signal 1. A signal is the software equivalent of the flag at a register that sets on a hardware interrupt. 2. It is sent on some exception or on some condition, which can set during running of a process or task or thread. 3. Sending a signal is software equivalent of throwing exception in C/C++ or Java program 24

25 Advantage of using a Signal 4. Unless process is masked by a signal mask, the signal allows the execution of the signal handling process, just as a hardware interrupt allows the execution of an ISR 25

26 Advantage of using a Signal 5. A signal is identical to setting a flag that is shared and used by another interrupt servicing process. 6. A signal raised by one process forces another process to interrupt and to catch that signal provided the signal is not masked at that process. 26

27 5. Drawbacks of using a Signal 27

28 Drawbacks of using a Signal 1. Signal is handled only by a very high priority process (service routine). That may disrupt the usual schedule and usual priority inheritance mechanism. 2. Signal may cause reentrancy problem [process not retuning to state identical to the one before signal handler process executed]. 28

29 Summary 29

30 We learnt (i) The simplest IPC for messaging and synchronizing processes is signal. A signal provides the shortest message. Signals are used for initiating another ISR or task and error handling process called signal handler. (ii) A signal is equivalent throwing exception in Java/C/C++ or setting of an interrupt flag 30

31 End of Lesson-12 on Signal 31

Solved MCQS From Midterm Papers. MIDTERM EXAMINATION Spring CS604 - Operating System

Solved MCQS From Midterm Papers. MIDTERM EXAMINATION Spring CS604 - Operating System CS604 - Operating System Solved MCQS From Midterm Papers May 13,2013 MC100401285 Moaaz.pk@gmail.com Mc100401285@vu.edu.pk PSMD01 MIDTERM EXAMINATION Spring 2012 CS604 - Operating System Question No: 1

More information

Solved MCQS From Midterm Papers. MIDTERM EXAMINATION Spring CS604 - Operating System

Solved MCQS From Midterm Papers. MIDTERM EXAMINATION Spring CS604 - Operating System CS604 - Operating System Solved MCQS From Midterm Papers Apr 27,2013 MC100401285 Moaaz.pk@gmail.com Mc100401285@vu.edu.pk PSMD01 MIDTERM EXAMINATION Spring 2012 CS604 - Operating System Question No: 1

More information

ECE 4220 Real Time Embedded Systems Final Project Spectrum Analyzer

ECE 4220 Real Time Embedded Systems Final Project Spectrum Analyzer ECE 4220 Real Time Embedded Systems Final Project Spectrum Analyzer by: Matt Mazzola 12222670 Abstract The design of a spectrum analyzer on an embedded device is presented. The device achieves minimum

More information

Lecture-47 INTEL 8085A INTERRUPT STRUCTURE

Lecture-47 INTEL 8085A INTERRUPT STRUCTURE Lecture-47 INTEL 8085A INTEUPT STUCTUE There are five interrupt inputs TAP, ST7.5, ST6.5, ST5.5 and INT. TAP is a non-maskable interrupt, that is, it cannot be disabled by an instruction. ST7.5, ST6.5,

More information

VeriLab. An introductory lab for using Verilog in digital design (first draft) VeriLab

VeriLab. An introductory lab for using Verilog in digital design (first draft) VeriLab VeriLab An introductory lab for using Verilog in digital design (first draft) VeriLab An introductory lab for using Verilog in digital design Verilog is a hardware description language useful for designing

More information

Outline. Signal Names and Types. What is a Signal? CSCI 4061 Introduction to Operating Systems

Outline. Signal Names and Types. What is a Signal? CSCI 4061 Introduction to Operating Systems Outline CSCI 4061 Introduction to Operating Systems Signal Overview Signal Generation and Handling Signal Safety Realtime Signals Instructor: Abhishek Chandra 2 What is a Signal? Signal Names and Types

More information

Section bit Analog-to-Digital Converter (ADC)

Section bit Analog-to-Digital Converter (ADC) Section 17. 10-bit Analog-to-Digital Converter (ADC) HIGHLIGHTS This section of the manual contains the following major topics: 17 17.1 Introduction...17-2 17.2 Control Registers...17-4 17.3 ADC Operation,

More information

Point System (for instructor and TA use only)

Point System (for instructor and TA use only) EEL 4744C - Drs. George and Gugel Spring Semester 2002 Final Exam NAME SS# Closed book and closed notes examination to be done in pencil. Calculators are permitted. All work and solutions are to be written

More information

Software architecture and larger system design issues

Software architecture and larger system design issues Software architecture and larger system design issues ecture 3: Monitor synchonization Topics: Programming language specifics (ACE) More on monitor synchronization More problems with concurrent software

More information

T 2 : WR = 0, AD 7 -AD 0 (μp Internal Reg.) T 3 : WR = 1,, M(AB) AD 7 -AD 0 or BDB

T 2 : WR = 0, AD 7 -AD 0 (μp Internal Reg.) T 3 : WR = 1,, M(AB) AD 7 -AD 0 or BDB Lecture-17 Memory WRITE Machine Cycle: It also requires only T 1 to T 3 states. The purpose of memory write machine cycle is to store the contents of any of the 8085A register such as the accumulator into

More information

Logic and Computer Design Fundamentals. Chapter 7. Registers and Counters

Logic and Computer Design Fundamentals. Chapter 7. Registers and Counters Logic and Computer Design Fundamentals Chapter 7 Registers and Counters Registers Register a collection of binary storage elements In theory, a register is sequential logic which can be defined by a state

More information

ST10F273M Errata sheet

ST10F273M Errata sheet Errata sheet 16-bit MCU with 512 KBytes Flash and 36 KBytes RAM memories Introduction This errata sheet describes all the functional and electrical problems known in the ABG silicon version of the ST10F273M.

More information

EECS145M 2000 Midterm #1 Page 1 Derenzo

EECS145M 2000 Midterm #1 Page 1 Derenzo UNIVERSITY OF CALIFORNIA College of Engineering Electrical Engineering and Computer Sciences Department EECS 145M: Microcomputer Interfacing Laboratory Spring Midterm #1 (Closed book- calculators OK) Wednesday,

More information

Design and Implementation of Nios II-based LCD Touch Panel Application System

Design and Implementation of Nios II-based LCD Touch Panel Application System Design and Implementation of Nios II-based Touch Panel Application System Tong Zhang 1, Wen-Ping Ren 2, Yi-Dian Yin, and Song-Hai Zhang School of Information Science and Technology, Yunnan University No.2,

More information

HW#3 - CSE 237A. 1. A scheduler has three queues; A, B and C. Outgoing link speed is 3 bits/sec

HW#3 - CSE 237A. 1. A scheduler has three queues; A, B and C. Outgoing link speed is 3 bits/sec HW#3 - CSE 237A 1. A scheduler has three queues; A, B and C. Outgoing link speed is 3 bits/sec a. (Assume queue A wants to transmit at 1 bit/sec, and queue B at 2 bits/sec and queue C at 3 bits/sec. What

More information

82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE

82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE Y Y Y Y Y 82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE Compatible with all Intel and Most Other Microprocessors High Speed Zero Wait State Operation with 8 MHz 8086 88 and 80186 188 24 Programmable I

More information

VARIABLE FREQUENCY CLOCKING HARDWARE

VARIABLE FREQUENCY CLOCKING HARDWARE VARIABLE FREQUENCY CLOCKING HARDWARE Variable-Frequency Clocking Hardware Many complex digital systems have components clocked at different frequencies Reason 1: to reduce power dissipation The active

More information

COMP2611: Computer Organization. Introduction to Digital Logic

COMP2611: Computer Organization. Introduction to Digital Logic 1 COMP2611: Computer Organization Sequential Logic Time 2 Till now, we have essentially ignored the issue of time. We assume digital circuits: Perform their computations instantaneously Stateless: once

More information

Using the Synchronized Pulse-Width Modulation etpu Function by:

Using the Synchronized Pulse-Width Modulation etpu Function by: Freescale Semiconductor Application Note Document Number: AN2854 Rev. 1, 10/2008 Using the Synchronized Pulse-Width Modulation etpu Function by: Geoff Emerson Microcontroller Solutions Group This application

More information

Errata OPERATING SYSTEM CONCEPTS, FIFTH EDITION Silberschatz and Galvin September 9, 1998

Errata OPERATING SYSTEM CONCEPTS, FIFTH EDITION Silberschatz and Galvin September 9, 1998 Errata OPERATING SYSTEM CONCEPTS, FIFTH EDITION Silberschatz and Galvin September 9, 1998 Corrected in 2 nd Printing: page ix (Preface), Second to the last line: which which which page 119, section 4.7,

More information

CS609- System Programming Solved MCQS From Midterm Papers. FINALTERM EXAMINATION Spring 2012 CS609- System Programming

CS609- System Programming Solved MCQS From Midterm Papers. FINALTERM EXAMINATION Spring 2012 CS609- System Programming CS609- System Programming Solved MCQS From Midterm Papers July 02 30,2013 MC100401285 Moaaz.pk@gmail.com Mc100401285@gmail.com PSMD01 FINALTERM EXAMINATION Spring 2012 CS609- System Programming Question

More information

KW11-L line time clock manual

KW11-L line time clock manual DEC-ll HKWB-D KW11-L line time clock manual DIGITAL EQUIPMENT CORPORATION MAYNARD, MASSACHUSETTS 1st Edition February 1971 2nd Printing (Rev) December 1971 3rd Printing July 1972 4th Printing October 1972

More information

Documentation for the HawkV9Utils support module.

Documentation for the HawkV9Utils support module. Documentation for the HawkV9Utils support module. This document describes the 9 calls provided by the module 'HawkV9Utils': This is the support module which forms part of the!hawkv9 application from Computer

More information

Application of A Disk Migration Module in Virtual Machine live Migration

Application of A Disk Migration Module in Virtual Machine live Migration 2010 3rd International Conference on Computer and Electrical Engineering (ICCEE 2010) IPCSIT vol. 53 (2012) (2012) IACSIT Press, Singapore DOI: 10.7763/IPCSIT.2012.V53.No.2.61 Application of A Disk Migration

More information

Come and join us at WebLyceum

Come and join us at WebLyceum Come and join us at WebLyceum For Past Papers, Quiz, Assignments, GDBs, Video Lectures etc Go to http://www.weblyceum.com and click Register In Case of any Problem Contact Administrators Rana Muhammad

More information

Laboratory Exercise 4

Laboratory Exercise 4 Laboratory Exercise 4 Polling and Interrupts The purpose of this exercise is to learn how to send and receive data to/from I/O devices. There are two methods used to indicate whether or not data can be

More information

The Lincoln TX-2 Input-Output System*

The Lincoln TX-2 Input-Output System* 156 1957 WESTERN COMPUTER PROCEEDINGS The Lincoln TX-2 Input-Output System*, JAMES w. FORGIEt INTRODUCTION THE input-output system of the Lincoln TX-2 computer contains a variety of input-output devices

More information

Performance Analysis with Vampir VIRTUAL INSTITUTE HIGH PRODUCTIVITY SUPERCOMPUTING

Performance Analysis with Vampir VIRTUAL INSTITUTE HIGH PRODUCTIVITY SUPERCOMPUTING Performance Analysis with Vampir Outline Part I: Welcome to the Vampir Tool Suite Event Trace Visualization Vampir & VampirServer The Vampir Displays Part II: Vampir Hands-On Visualizing and analyzing

More information

AVRcam Code Commentary. Version 1.3

AVRcam Code Commentary. Version 1.3 AVRcam Code Commentary Version 1.3 Copyright 2007 Revision History Date Version Author Description 2/15/2007 1.0 John Orlando Initial release 2/22/2007 1.1 John Orlando Added sections for User Interface

More information

Getting Started with UHD and C++

Getting Started with UHD and C++ Contents 1 Application Note Number 2 Revision History 3 Abstract 4 Overview 5 UHD Manual 6 Including Header Files 7 UHD_SAFE_MAIN() 8 set_thread_priority_safe() 9 Create Variables 10 Creating a USRP Object

More information

Tutorial Introduction

Tutorial Introduction Tutorial Introduction PURPOSE - To explain how to configure and use the Timebase Module OBJECTIVES: - Describe the uses and features of the Timebase Module. - Identify the steps to configure the Timebase

More information

Fast Quadrature Decode TPU Function (FQD)

Fast Quadrature Decode TPU Function (FQD) PROGRAMMING NOTE Order this document by TPUPN02/D Fast Quadrature Decode TPU Function (FQD) by Jeff Wright 1 Functional Overview The fast quadrature decode function is a TPU input function that uses two

More information

Hello, and welcome to this presentation of the STM32 system window watchdog. It will cover the main features of this peripheral used to detect

Hello, and welcome to this presentation of the STM32 system window watchdog. It will cover the main features of this peripheral used to detect Hello, and welcome to this presentation of the STM32 system window watchdog. It will cover the main features of this peripheral used to detect software faults. 1 The window watchdog is used to detect the

More information

Scans and encodes up to a 64-key keyboard. DB 1 DB 2 DB 3 DB 4 DB 5 DB 6 DB 7 V SS. display information.

Scans and encodes up to a 64-key keyboard. DB 1 DB 2 DB 3 DB 4 DB 5 DB 6 DB 7 V SS. display information. Programmable Keyboard/Display Interface - 8279 A programmable keyboard and display interfacing chip. Scans and encodes up to a 64-key keyboard. Controls up to a 16-digit numerical display. Keyboard has

More information

Thermal arm-wrestling. Customer game plan. Problem to be solved Customer game concept

Thermal arm-wrestling. Customer game plan. Problem to be solved Customer game concept Thermal arm-wrestling Problem to be solved Customer game concept I WIN YOU WIN Design of a video game using two programmable flags (PF) interrupts Tutorial on handling 2 Hardware interrupts from an external

More information

Logic Analyzer Triggering Techniques to Capture Elusive Problems

Logic Analyzer Triggering Techniques to Capture Elusive Problems Logic Analyzer Triggering Techniques to Capture Elusive Problems Efficient Solutions to Elusive Problems For digital designers who need to verify and debug their product designs, logic analyzers provide

More information

Dimming actuators GDA-4K KNX GDA-8K KNX

Dimming actuators GDA-4K KNX GDA-8K KNX Dimming actuators GDA-4K KNX GDA-8K KNX GDA-4K KNX 108394 GDA-8K KNX 108395 Updated: May-17 (Subject to changes) Page 1 of 67 Contents 1 FUNCTIONAL CHARACTERISTICS... 4 1.1 OPERATION... 5 2 TECHNICAL DATA...

More information

Microprocessor Design

Microprocessor Design Microprocessor Design Principles and Practices With VHDL Enoch O. Hwang Brooks / Cole 2004 To my wife and children Windy, Jonathan and Michelle Contents 1. Designing a Microprocessor... 2 1.1 Overview

More information

TABLE 3. MIB COUNTER INPUT Register (Write Only) TABLE 4. MIB STATUS Register (Read Only)

TABLE 3. MIB COUNTER INPUT Register (Write Only) TABLE 4. MIB STATUS Register (Read Only) TABLE 3. MIB COUNTER INPUT Register (Write Only) at relative address: 1,000,404 (Hex) Bits Name Description 0-15 IRC[15..0] Alternative for MultiKron Resource Counters external input if no actual external

More information

Virtex-II Pro and VxWorks for Embedded Solutions. Systems Engineering Group

Virtex-II Pro and VxWorks for Embedded Solutions. Systems Engineering Group Virtex-II Pro and VxWorks for Embedded Solutions Systems Engineering Group Embedded System Development Embedded Solutions Key components of Embedded systems development Integrated development environment

More information

Decade Counters Mod-5 counter: Decade Counter:

Decade Counters Mod-5 counter: Decade Counter: Decade Counters We can design a decade counter using cascade of mod-5 and mod-2 counters. Mod-2 counter is just a single flip-flop with the two stable states as 0 and 1. Mod-5 counter: A typical mod-5

More information

KW11-L line time clock manual

KW11-L line time clock manual EK-KWllL-TM-002 KW11-L line time clock manual digital equipment corporation maynard, massachusetts 1st Edition February 1971 2nd Printing (Rev) December 1971 3rd Printing July 1972 4th Printing October

More information

WWW.STUDENTSFOCUS.COM + Class Subject Code Subject Prepared By Lesson Plan for Time: Lesson. No 1.CONTENT LIST: Introduction to Unit III 2. SKILLS ADDRESSED: Listening I year, 02 sem CS6201 Digital Principles

More information

Dimming actuators of the FIX series DM 4-2 T, DM 8-2 T

Dimming actuators of the FIX series DM 4-2 T, DM 8-2 T Dimming actuators of the FIX series DM 4-2 T, DM 8-2 T DM 4-2 T 4940280 DM 8-2 T 4940285 Updated: Jun-16 (Subject to change) Page 1 of 70 Contents 1 FUNCTIONAL CHARACTERISTICS... 4 1.1 OPERATION... 5 2

More information

DUOLABS Spa. Conditional Access Module Hardware Brief. CA Module User Guide V0.2

DUOLABS Spa. Conditional Access Module Hardware Brief. CA Module User Guide V0.2 Conditional Access Module Hardware Brief CA Module User Guide V0.2 Index Conditional Access Module... 1 CA Module User Guide... 1 Revision history... Errore. Il segnalibro non è definito. Index... 1 Reference...

More information

o The 9S12 has a 16-bit free-running counter to determine the time and event happens, and to make an event happen at a particular time

o The 9S12 has a 16-bit free-running counter to determine the time and event happens, and to make an event happen at a particular time More on Programming the 9S12 in C Huang Sections 5.2 through 5.4 Introduction to the 9S12 Hardware Subsystems Huang Sections 8.2-8.6 ECT_16B8C Block User Guide A summary of 9S12 hardware subsystems Introduction

More information

Application on Control Technology

Application on Control Technology Application on Control Technology Programming example in Ladder Logic Warranty, liability and support Note The application examples are not binding and do not claim to be complete regarding the circuits

More information

Training Note TR-06RD. Schedules. Schedule types

Training Note TR-06RD. Schedules. Schedule types Schedules General operation of the DT80 data loggers centres on scheduling. Schedules determine when various processes are to occur, and can be triggered by the real time clock, by digital or counter events,

More information

o The 9S12 has a 16-bit free-running counter to determine the time and event happens, and to make an event happen at a particular time

o The 9S12 has a 16-bit free-running counter to determine the time and event happens, and to make an event happen at a particular time More on Programming the 9S12 in C Huang Sections 5.2 through 5.4 Introduction to the 9S12 Hardware Subsystems Huang Sections 8.2-8.6 ECT_16B8C Block User Guide A summary of 9S12 hardware subsystems Introduction

More information

Section 508 Conformance Audit Voluntary Product Accessibility Template

Section 508 Conformance Audit Voluntary Product Accessibility Template Date:11/06/2015 Section 508 Conformance Audit Voluntary Product Accessibility Template Marketing Name: OptiPlex 7440 All-In-One Regulatory Model: W11B Dell Inc. One Dell Way Round Rock, TX 78682 Reviewed

More information

Stimulus presentation using Matlab and Visage

Stimulus presentation using Matlab and Visage Stimulus presentation using Matlab and Visage Cambridge Research Systems Visual Stimulus Generator ViSaGe Programmable hardware and software system to present calibrated stimuli using a PC running Windows

More information

Video Output and Graphics Acceleration

Video Output and Graphics Acceleration Video Output and Graphics Acceleration Overview Frame Buffer and Line Drawing Engine Prof. Kris Pister TAs: Vincent Lee, Ian Juch, Albert Magyar Version 1.5 In this project, you will use SDRAM to implement

More information

Chapter 4. Logic Design

Chapter 4. Logic Design Chapter 4 Logic Design 4.1 Introduction. In previous Chapter we studied gates and combinational circuits, which made by gates (AND, OR, NOT etc.). That can be represented by circuit diagram, truth table

More information

TV Synchronism Generation with PIC Microcontroller

TV Synchronism Generation with PIC Microcontroller TV Synchronism Generation with PIC Microcontroller With the widespread conversion of the TV transmission and coding standards, from the early analog (NTSC, PAL, SECAM) systems to the modern digital formats

More information

Computer and Machine Vision

Computer and Machine Vision Computer and Machine Vision Lecture Week 3 Part-1 January 27, 2014 Sam Siewert Outline of Week 3 Processing Images and Moving Pictures High Level View and Computer Architecture for it Linux Platforms for

More information

Design and Implementation of Timer, GPIO, and 7-segment Peripherals

Design and Implementation of Timer, GPIO, and 7-segment Peripherals Design and Implementation of Timer, GPIO, and 7-segment Peripherals 1 Module Overview Learn about timers, GPIO and 7-segment display; Design and implement an AHB timer, a GPIO peripheral, and a 7-segment

More information

AUTOMATIC LICENSE PLATE RECOGNITION(ALPR) ON EMBEDDED SYSTEM

AUTOMATIC LICENSE PLATE RECOGNITION(ALPR) ON EMBEDDED SYSTEM AUTOMATIC LICENSE PLATE RECOGNITION(ALPR) ON EMBEDDED SYSTEM Presented by Guanghan APPLICATIONS 1. Automatic toll collection 2. Traffic law enforcement 3. Parking lot access control 4. Road traffic monitoring

More information

TXZ Family. Reference Manual 12-bit Analog to Digital Converter (ADC-A) 32-bit RISC Microcontroller. Revision

TXZ Family. Reference Manual 12-bit Analog to Digital Converter (ADC-A) 32-bit RISC Microcontroller. Revision 32-bit RISC Microcontroller TXZ Family Reference Manual (ADC-A) Revision 2.1 2018-06 2018/06/19 1 / 46 Rev. 2.1 2017-2018 Toshiba Electronic Devices & Storage Corporation Contents Preface... 5 Related

More information

DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) LATCHES and FLIP-FLOPS

DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) LATCHES and FLIP-FLOPS COURSE / CODE DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) LATCHES and FLIP-FLOPS In the same way that logic gates are the building blocks of combinatorial circuits, latches

More information

REVISIONS LTR DESCRIPTION DATE APPROVED - Initial Release 11/5/07 MDB A ECR /9/08 MDB

REVISIONS LTR DESCRIPTION DATE APPROVED - Initial Release 11/5/07 MDB A ECR /9/08 MDB REVISIONS LTR DESCRIPTION DATE APPROVED - Initial Release 11/5/07 MDB A ECR 8770 4/9/08 MDB CONTRACT NO. DRAWN BY CHECKED BY APPROVED BY DATE P. Phillips 11/2/07 TITLE M. Bester 11/5/07 SIZE A 2120 Old

More information

From Synchronous to Asynchronous Design

From Synchronous to Asynchronous Design by Gerrit Muller Buskerud University College e-mail: gaudisite@gmail.com www.gaudisite.nl Abstract The most simple real time programming paradigm is a synchronous loop. This is an effective approach for

More information

8 X 8 KEYBOARD INTERFACE (WITHOUT INTERRUPT SIGNAL)

8 X 8 KEYBOARD INTERFACE (WITHOUT INTERRUPT SIGNAL) UNIT 4 REFERENCE 1 8 X 8 KEYBOARD INTERFACE (WITHOUT INTERRUPT SIGNAL) Statement: Interface an 8 x 8 matrix keyboard to 8085 through 8279 in 2-key lockout mode and write an assembly language program to

More information

AXIS M30 Series AXIS M3015 AXIS M3016. User Manual

AXIS M30 Series AXIS M3015 AXIS M3016. User Manual AXIS M3015 AXIS M3016 User Manual Table of Contents About this manual.......................................... 3 Product overview........................................... 4 How to access the product....................................

More information

Better Business Graphics: Avoiding Death by Powerpoint Joe Levy

Better Business Graphics: Avoiding Death by Powerpoint Joe Levy Better Business Graphics: Avoiding Death by Powerpoint Joe Levy IEEE/ACM Information Technology Professional Conference at TCF March 16, 2018. This work is licensed under a Creative Commons AttributionNonCommercial-NoDerivatives

More information

6.3 Sequential Circuits (plus a few Combinational)

6.3 Sequential Circuits (plus a few Combinational) 6.3 Sequential Circuits (plus a few Combinational) Logic Gates: Fundamental Building Blocks Introduction to Computer Science Robert Sedgewick and Kevin Wayne Copyright 2005 http://www.cs.princeton.edu/introcs

More information

Theory Lecture Day Topic Practical Day. Week. number systems and their inter-conversion Decimal, Binary. 3rd. 1st. 1st

Theory Lecture Day Topic Practical Day. Week. number systems and their inter-conversion Decimal, Binary. 3rd. 1st. 1st Lesson Plan Name of the Faculty : Priyanka Nain Discipline: Electronics & Communication Engg. Semester:5th Subject:DEMP Lesson Plan Duration: 15 Weeks Work Load(Lecture/Practical) per week (In Hours):

More information

AN-ENG-001. Using the AVR32 SoC for real-time video applications. Written by Matteo Vit, Approved by Andrea Marson, VERSION: 1.0.0

AN-ENG-001. Using the AVR32 SoC for real-time video applications. Written by Matteo Vit, Approved by Andrea Marson, VERSION: 1.0.0 Written by Matteo Vit, R&D Engineer Dave S.r.l. Approved by Andrea Marson, CTO Dave S.r.l. DAVE S.r.l. www.dave.eu VERSION: 1.0.0 DOCUMENT CODE: AN-ENG-001 NO. OF PAGES: 8 AN-ENG-001 Using the AVR32 SoC

More information

Find the equivalent decimal value for the given value Other number system to decimal ( Sample)

Find the equivalent decimal value for the given value Other number system to decimal ( Sample) VELAMMAL COLLEGE OF ENGINEERING AND TECHNOLOGY, MADURAI 65 009 Department of Information Technology Model Exam-II-Question bank PART A (Answer for all Questions) (8 X = 6) K CO Marks Find the equivalent

More information

PROF. TAJANA SIMUNIC ROSING. Midterm. Problem Max. Points Points Total 150 INSTRUCTIONS:

PROF. TAJANA SIMUNIC ROSING. Midterm. Problem Max. Points Points Total 150 INSTRUCTIONS: CSE 237A FALL 2006 PROF. TAJANA SIMUNIC ROSING Midterm NAME: ID: Solutions Problem Max. Points Points 1 20 2 20 3 30 4 25 5 25 6 30 Total 150 INSTRUCTIONS: 1. There are 6 problems on 11 pages worth a total

More information

UNIT-3: SEQUENTIAL LOGIC CIRCUITS

UNIT-3: SEQUENTIAL LOGIC CIRCUITS UNIT-3: SEQUENTIAL LOGIC CIRCUITS STRUCTURE 3. Objectives 3. Introduction 3.2 Sequential Logic Circuits 3.2. NAND Latch 3.2.2 RS Flip-Flop 3.2.3 D Flip-Flop 3.2.4 JK Flip-Flop 3.2.5 Edge Triggered RS Flip-Flop

More information

AXIS M30 Network Camera Series. AXIS M3046-V Network Camera. AXIS M3045 V Network Camera. User Manual

AXIS M30 Network Camera Series. AXIS M3046-V Network Camera. AXIS M3045 V Network Camera. User Manual AXIS M3044-V Network Camera AXIS M3045 V Network Camera AXIS M3046-V Network Camera User Manual Table of Contents About this manual.......................................... 3 System overview............................................

More information

Chameleon: Application Level Power Management with Performance Isolation

Chameleon: Application Level Power Management with Performance Isolation Chameleon: Application Level Power Management with Performance Isolation Xiaotao Liu, Prashant Shenoy and Mark Corner Department of Computer Science, University of Massachusetts Amherst. Abstract In this

More information

3 Flip-Flops. The latch is a logic block that has 2 stable states (0) or (1). The RS latch can be forced to hold a 1 when the Set line is asserted.

3 Flip-Flops. The latch is a logic block that has 2 stable states (0) or (1). The RS latch can be forced to hold a 1 when the Set line is asserted. 3 Flip-Flops Flip-flops and latches are digital memory circuits that can remain in the state in which they were set even after the input signals have been removed. This means that the circuits have a memory

More information

CMSC 313 Preview Slides

CMSC 313 Preview Slides CMSC 33 Preview Slides These are draft slides. The actual slides presented in lecture may be different due to last minute changes, schedule slippage,... UMBC, CMSC33, Richard Chang CMSC

More information

MULTIFUNCTION DSP BASED REAL-TIME POWER QUALITY ANALYZER

MULTIFUNCTION DSP BASED REAL-TIME POWER QUALITY ANALYZER XVIII IMEKO WORLD CONGRESS Metrology for a Sustainable Development September, 17 22, 2006, Rio de Janeiro, Brazil MULTIFUNCTION DSP BASED REAL-TIME POWER QUALITY ANALYZER D.Gallo, C.Landi, N.Rignano Department.

More information

The University of Texas at Dallas Department of Computer Science CS 4141: Digital Systems Lab

The University of Texas at Dallas Department of Computer Science CS 4141: Digital Systems Lab The University of Texas at Dallas Department of Computer Science CS 4141: Digital Systems Lab Experiment #5 Shift Registers, Counters, and Their Architecture 1. Introduction: In Laboratory Exercise # 4,

More information

AXIS M30 Network Camera Series. AXIS M3046-V Network Camera. AXIS M3045 V Network Camera. User Manual

AXIS M30 Network Camera Series. AXIS M3046-V Network Camera. AXIS M3045 V Network Camera. User Manual AXIS M3044-V Network Camera AXIS M3045 V Network Camera AXIS M3046-V Network Camera User Manual Table of Contents About this manual.......................................... 3 Solution overview...........................................

More information

ET398 LAB 4. Concurrent Statements, Selection and Process

ET398 LAB 4. Concurrent Statements, Selection and Process ET398 LAB 4 Concurrent Statements, Selection and Process Decoders/Multiplexers February 16, 2013 Tiffany Turner OBJECTIVE The objectives of this lab were for us to become more adept at creating VHDL code

More information

Customized electronic part transport in the press shop siemens.com/metalforming

Customized electronic part transport in the press shop siemens.com/metalforming Press handling solutions Customized electronic part transport in the press shop siemens.com/metalforming Your handling. Your press. Your solution. Cost-effective workpiece transport is essential for presses.

More information

(Refer Slide Time: 1:45)

(Refer Slide Time: 1:45) (Refer Slide Time: 1:45) Digital Circuits and Systems Prof. S. Srinivasan Department of Electrical Engineering Indian Institute of Technology, Madras Lecture - 30 Encoders and Decoders So in the last lecture

More information

Profiling techniques for parallel applications

Profiling techniques for parallel applications Profiling techniques for parallel applications Analyzing program performance with HPCToolkit 17/04/2014 PRACE Spring School 2014 2 Introduction Thomas Ponweiser Johannes Kepler University Linz (JKU) Involved

More information

Published in A R DIGITECH

Published in A R DIGITECH Design of propeller clock by using 8051 Microcontroller Ahmed H. Al-Saadi*1 *1 (B.Sc. of Computer Engineering in Al Hussein University College of Engineering, Iraq) ah9@outlook.com*1 Abstract The propeller

More information

Processor time 9 Used memory 9. Lost video frames 11 Storage buffer 11 Received rate 11

Processor time 9 Used memory 9. Lost video frames 11 Storage buffer 11 Received rate 11 Processor time 9 Used memory 9 Lost video frames 11 Storage buffer 11 Received rate 11 2 3 After you ve completed the installation and configuration, run AXIS Installation Verifier from the main menu icon

More information

Hello and welcome to this presentation of the STM32L4 Analog-to-Digital Converter block. It will cover the main features of this block, which is used

Hello and welcome to this presentation of the STM32L4 Analog-to-Digital Converter block. It will cover the main features of this block, which is used Hello and welcome to this presentation of the STM32L4 Analog-to-Digital Converter block. It will cover the main features of this block, which is used to convert the external analog voltage-like sensor

More information

Multimedia Time Warping System. Akiko Campbell Presentation-2 Summer/2004

Multimedia Time Warping System. Akiko Campbell Presentation-2 Summer/2004 Multimedia Time Warping System Akiko Campbell Presentation-2 Summer/2004 Outline Overview Facts Features Multimedia Time Warping System Conclusion Effect of TiVo on VoD Overview Facts A Linux box that

More information

Introduction to Computer Graphics

Introduction to Computer Graphics Introduction to Computer Graphics R. J. Renka Department of Computer Science & Engineering University of North Texas 01/16/2010 Introduction Computer Graphics is a subfield of computer science concerned

More information

SEQUENTIAL LOGIC. Satish Chandra Assistant Professor Department of Physics P P N College, Kanpur

SEQUENTIAL LOGIC. Satish Chandra Assistant Professor Department of Physics P P N College, Kanpur SEQUENTIAL LOGIC Satish Chandra Assistant Professor Department of Physics P P N College, Kanpur www.satish0402.weebly.com OSCILLATORS Oscillators is an amplifier which derives its input from output. Oscillators

More information

SETH JAI PARKASH POLYTECHNIC, DAMLA COMPUTER ENGINEERING AIDED-3 RD SEMESTER

SETH JAI PARKASH POLYTECHNIC, DAMLA COMPUTER ENGINEERING AIDED-3 RD SEMESTER LESSON PLAN Sub: Multimedia Sanjeev Sehgal WEE K THEORY LECTUR E DAY TOPIC (Including assignment/ test) PRACTICAL PRACTICA L DAY TOPIC Ist 1st Introduction to multimedia Ist Installation of various MA

More information

5620 SAM SERVICE AWARE MANAGER 14.0 R7. Planning Guide

5620 SAM SERVICE AWARE MANAGER 14.0 R7. Planning Guide 5620 SAM SERVICE AWARE MANAGER 14.0 R7 Planning Guide 3HE-10698-AAAE-TQZZA December 2016 5620 SAM Legal notice Nokia is a registered trademark of Nokia Corporation. Other products and company names mentioned

More information

Obsolete Product(s) - Obsolete Product(s)

Obsolete Product(s) - Obsolete Product(s) AN1841 APPLICATION NOTE Closed Caption and XDS Software 1 INTRODUCTION This document describes the Closed Caption and extended Data Service (XDS) extraction software module available for the ST92x196 family.

More information

LogiCORE IP AXI Video Direct Memory Access v5.01.a

LogiCORE IP AXI Video Direct Memory Access v5.01.a LogiCORE IP AXI Video Direct Memory Access v5.01.a Product Guide Table of Contents Chapter 1: Overview Feature Summary.................................................................. 9 Applications.....................................................................

More information

May 26 th, Lynelle Briggs AO Chair Planning and Assessment Commission

May 26 th, Lynelle Briggs AO Chair Planning and Assessment Commission May 26 th, 2017 Lynelle Briggs AO Chair Planning and Assessment Commission Open Letter to Chair of NSW Planning Assessment Commission re Apparent Serious Breaches of PAC s Code of Conduct by Commissioners

More information

CSE115: Digital Design Lecture 23: Latches & Flip-Flops

CSE115: Digital Design Lecture 23: Latches & Flip-Flops Faculty of Engineering CSE115: Digital Design Lecture 23: Latches & Flip-Flops Sections 7.1-7.2 Suggested Reading A Generic Digital Processor Building Blocks for Digital Architectures INPUT - OUTPUT Interconnect:

More information

Tebis application software

Tebis application software Tebis application software Input products / ON / OFF output / RF dimmer Electrical / Mechanical characteristics: see product user manual Product reference Product designation TP device RF device WYC42xQ

More information

BLDC DRIVE USING AN OPTICAL ENCODER

BLDC DRIVE USING AN OPTICAL ENCODER Fujitsu Microelectronics Europe Application Note MCU-AN-300018-E-V10 FR FAMILY 32-BIT MICROCONTROLLER MB91265 SERIES BLDC DRIVE USING AN OPTICAL ENCODER APPLICATION NOTE Revision History Revision History

More information

Introduction to Serial I/O

Introduction to Serial I/O CS/ECE 6780/5780 Al Davis Serial I/O Today s topics: general concepts in preparation for Lab 8 1 CS 5780 Introduction to Serial I/O 2 CS 5780 Page 1 A Serial Channel 3 CS 5780 Definitions 4 CS 5780 Page

More information

Page 1. Introduction to Serial I/O. Definitions. A Serial Channel CS/ECE 6780/5780. Al Davis. Today s topics: Serial I/O

Page 1. Introduction to Serial I/O. Definitions. A Serial Channel CS/ECE 6780/5780. Al Davis. Today s topics: Serial I/O Introduction to Serial I/O CS/ECE 6780/5780 Al Davis Serial I/O Today s topics: general concepts in preparation for Lab 8 1 CS 5780 2 CS 5780 A Serial Channel Definitions 3 CS 5780 4 CS 5780 Page 1 Bandwidth

More information

COE328 Course Outline. Fall 2007

COE328 Course Outline. Fall 2007 COE28 Course Outline Fall 2007 1 Objectives This course covers the basics of digital logic circuits and design. Through the basic understanding of Boolean algebra and number systems it introduces the student

More information

DTMF Dialer Analog Output Data Sheet

DTMF Dialer Analog Output Data Sheet 13. DTMF Dialer Analog Output DTMF Dialer Analog Output Data Sheet Copyright 2003-2009 Cypress Semiconductor Corporation. All Rights Reserved. DTMFDialer PSoC Blocks API Memory (Bytes) Pins (per Resources

More information

MOI-V Linux dvblast tvheadend VDR Operating Instructions

MOI-V Linux dvblast tvheadend VDR Operating Instructions MOI-V Linux dvblast tvheadend VDR Operating Instructions Dear Customers, Thank you very much for choosing TBS products. The professional IPTV streamer MOI-V supports up to 6 built-in TV tuner PCI-e cards

More information