EKT 121/4 ELEKTRONIK DIGIT 1
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1 EKT 121/4 ELEKTRONIK DIGIT 1 Kolej Universiti Kejuruteraan Utara Malaysia Bistable Storage Devices and Related Devices
2 Introduction Latches and flip-flops are the basic single-bit memory elements used to build sequential circuit with one or two inputs/outputs, designed using individual logic gates and feedback loops. Latches: The output of a latch depends on its current inputs and on its previous output and its change of state can happen at any time when its inputs change. Flip-Flop: The output of a flip-flop also depends on current inputs and its previous output but the change of state occurs at specific times determined by a clock input.
3 Latches: S-R R Latch Gate S-R S R Latch Gate D-LatchD Introduction Flip-Flops: Flops: Edge-Triggered Flip-Flop Flop (S-R, J-K, J D) Asynchronous Inputs Master-Slave Flip-Flop Flop Flip-Flop Flop Operating Characteristics Flip-Flop Flop Applications One-shots & The 555 Timer
4 Latches Type of temporary storage device that has two stable (bistable( bistable) ) states Similar to flip-flop flop the outputs are connected back to opposite inputs Main difference from flip-flop flop is the method used for changing their state S-R R latch, Gated/Enabled S-R S R latch and Gated D latch
5 S-R R (SET-RESET) Latch Active-HIGH input S-R Latch Active-LOW input S-R Latch
6 Logic symbols for the S-R and S-R latch.
7 Negative-OR equivalent of the NAND gate S-R latch
8
9 Truth table for an active-low input S-R latch
10 Assume that Q is initially LOW Waveforms
11 S-R R latch using NOR Gate Active-HIGH When the Set is high and Reset is low Q is high and Q is low
12 S-R R latch using NOR Gate (cont d) Active-HIGH Once Set is Q high, then with S and R both LOW nothing change.
13 S-R R latch using NOR Gate (cont d) Active-HIGH With Reset high and Set low the flip=flop give a Q high and a Q low.
14 S-R R latch using NOR Gate (cont d) Active-HIGH Toggling the Reset (LOW) changes nothing
15 S-R R latch using NOR Gate (cont d) Active-HIGH The state of both Set and Reset high is not allowed since it would give a illogical condition. ( INVALID! )
16 S-R R Latch truth table for NOR Gate Active-HIGH Input S R Q Q 0 0 Q Q hold condition set reset not allowed (Invalid)
17 S-R R Latch using NAND Gate Set high Reset low Q high Q low
18 S-R R Latch using NAND Gate (cont d) Reset high Set low give a Q low and Q high
19 S-R R Latch using NAND Gate (cont d) Both low no change
20 S-R R Latch using NAND Gate (cont d) Both Set and Reset high is not allowed but give both Q and Q as high
21 S-R R Latch truth table for NAND Gate S R Q Q 0 0 Q Q hold condition set reset not allowed
22 Gated S-R Latch A gate input is added to the S-R latch to make the latch synchronous. In order for the set and reset inputs to change the latch, the gate input must be active (high/enable). When the gate input is low, the latch remains in the hold condition.
23 A gated S-R latch.
24 Gated S-R latch waveform
25 Truth Table for Gated S-R S R Latch S R G Q Q Q Q Hold Q Q Hold Q Q Hold Q Q hold Q Q hold set reset not allowed
26 Gated D Latch (74LS75) The D (data) latch has a single input that is used to set and to reset the flip-flop. When the gate is high, the Q output will follow the D input. When the gate is low, the Q output will hold.
27 Gated S-R Latch Q output waveform if the inputs are as shown. The output follows the input when the gate is high but is in a hold when the gate is low.
28 Gated D Latch (74LS75)
29 Edge-triggered Flip-flop Logic Positive edge triggered and Negative edge-triggered All the above flip-flops have the triggering input called clock (CLK/C)
30 Clock Signals & Synchronous Sequential Circuits 1 Clock signal 0 Rising edges of the clock (Positive-edge triggered) Falling edges of the clock (Negative-edge triggered) Clock Cycle Time A clock signal is a periodic square wave that indefinitely switches values from 0 to 1 and 1 to 0 at fixed intervals.
31 Operation of a positive edge-triggered S-R flip-flop. (d) S=1, R=1 is invalid or not allowed
32 Example
33 A positive edge-triggered D flip-flop formed with an S-R flip-flop and an inverter. D CLK/C Q Q SET (stores a 1) RESET (stores a 0)
34 Example
35 Edge-triggered J-K J K flip-flop flop The edge-triggered J-K will only accept the J and K inputs during the active edge of the clock. The small triangle on the clock input indicates that the device is edge-triggered. A bubble on the clock input indicates that the device responds to the negative edge. no bubble would indicate a positive edge-triggered device.
36 Truth Table for J-K J K Flip Flop J K CLK Q Q 0 0 Q 0 Q 0 Hold Reset Set 1 1 Q 0 Q 0 Toggle (opposite state)
37 A simplified logic diagram for a positive edge-triggered J-K flip-flop.
38 Example: Positive edge-triggered
39 Example: Negative edge-triggered
40 Logic symbol for a J-K flip-flop with active- LOW preset and clear inputs.
41 Logic diagram for a basic J-K flip-flop with active-low preset and clear inputs.
42 Example:
43 A Master-Slave J-K Flip-Flop The J-K flip-flop has a toggle mode of operation when both J and K inputs are high.toggle means that the Q output will change states on each active clock edge. J, K and Cp are all synchronous inputs. The master-slave flip-flop is constructed with two latches. The master latch is loaded with the condition of the J-K inputs while the clock is high. When the clock goes low, the slave takes on the state of the master and the master is latched. The master-slave is a level-triggered device. The master-slave can interpret unwanted signals on the J-K inputs.
44 Basic logic diagram for a Master-Slave J-K flip-flop.
45 Pulse-triggered (master-slave) J-K flipflop logic symbols.
46 Truth Table for Master-Slave J-K Flip Flop J K CLK Q Q 0 0 Q 0 Q 0 Hold Reset Set 1 1 Q 0 Q 0 Toggle (opposite state)
47 Example: The flip-fop starts out RESET and the clock is active -LOW
48 Flip-Flop Applications Parallel Data Storage Frequency Division Counting
49 Application : Example of flip-flops used in a basic register for parallel data storage.
50 Application: The J-K flip-flop as a divide-by-2 device. Q is one-half the frequency of CLK.
51 Example : Two J-K flip-flops used to divide the clock frequency by 4. Q A is one-half and Q B is one-fourth the frequency of CLK.
52 Application: Flip-flops used to generate a binary count sequence. Two repetitions (00, 01, 10, 11) are shown.
53 ONE-SHOTS A monostable multivibrator, a device with only one stable state. Normally in its stable state and will change to its unstable state only when triggered. Once triggered, will remains in its unstable state for a predetermined length of time and will automatically returns to its stable state. The time it stays in its unstable state determines the pulse width of its output
54 A simple one-shot circuit.
55 Basic one-shot logic symbols. CX and RX stand for external components.
56 Nonretriggerable one-shot action.
57 Retriggerable one-shot action.
58 THE 555 TIMER Versatile and widely used IC because it can be configured in two different modes as either a monostable multivibrator (one-shots) or as an astable multivibrator (oscillator). An astable multivibrator has no stable states and therefore changes back and forth (oscillates) between two unstable states without any external triggering.
59 Internal functional diagram of a 555 timer (pin numbers are in parenthesis).
60 The 555 timer connected as a nonretriggerable one-shot.
61 The 555 timer connected as an astable multivibrator (oscillator).
62 Next week Sequential Circuit - Thank you -
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