ESE 570 STATIC SEQUENTIAL CMOS LOGIC CELLS. Kenneth R. Laker, University of Pennsylvania, updated 25Mar15

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1 ESE 570 STATIC SEQUENTIAL CMOS LOGIC CELLS 1

2 Classes of Logic Circuits two stable op. pts. Latch level triggered. Flip-Flop edge triggered. one stable op. pt. One-shot single pulse output no stable op. pt. Ring Oscillator Combinational Circuits: a. Current Output(s) depend ONLY on Current Inputs. b. Suited to problems that can be solved using truth tables. Sequential Circuits or State Machines: a. Current Output(s) depend on Current Inputs and Past Inputs via State(s). b. Suited to problems that are solved by completing several steps using current inputs and past outputs in a specific order or a sequential manner. 2

Functions Using Sequential Operations Sequential Operations Combinational Operations are performed in an may use memory cells such as Flip-Flops/ Latches to accomplish Binary Counting Data Transfer

3 Functions Using Sequential Operations Sequential Operations Combinational Operations are performed in an may use memory cells such as Flip-Flops/ Latches to accomplish Binary Counting Data Transfer which may be Serial to accomplish and and Decade Counting Shift Register which is a component of a Microprocessor Frequency Division using a or Arithmetic Logic Unit Frequency Counting which is the core of a Microcomputer Parallel 3

4 Sequential Circuit (or State Machine) Construct Inputs Outputs Vo1.... Present State Vo2 Vo3 Next State.... Clock -> Memory is used to Store Past Values of State(s) and Output(s). -> Asynchronous Sequential Circuit no clock, outputs change after inputs change -> Synchronous Sequential Circuit clock, outputs change with clock event 4

State Register Moore FSM Xj Inputs Comb Log Outputs Combinational Logic Yk Outputs Yk's are solely function of current states. Yk's change in sync with state clock.

5 State Register Moore FSM Xj Inputs Comb Log Outputs Combinational Logic Yk Outputs Yk's are solely function of current states. Yk's change in sync with state clock. Clock State Feedback Mealy FSM Xj Inputs Yk Outputs State Register Clock State Feedback Combinational Logic Yk's function of inputs & current states. Yk's change when inputs change. Yk's are asynchronous 5

6 Static Bistable Sequential Circuits Basic Cross-coupled Inverter pair Q Q 6

7 Bistable Sequential Circuits - cont. Basic Cross-coupled Inverter pair VOH = VDD Q Q VOL = 0 maintain stable state. STATIC: VDD and GND are required to maintain a stable state. Basic Bistable Cross-coupled Inverter Pair has no means to apply input(s) to change the circuit's State. 7

8 Basic Sequential Circuits (Cells) Latch Asynchronous or synchronous If synchronous, clock input is level sensitive. If synchronous, output can change multiple times during a clock cycle. If synchronous, output changes while clock is active. Flip-Flop Synchronous Involves two synchronous latches. Output is edge sensitive, i.e. Output only changes on rising (or falling) edge of clock. Output can change only once during a clock cycle. Output changes on clock transition. 8

9 Asynchronous Latch Circuits Full CMOS Asynchronous SR Latch NOR Based Latch basic cross-coupled inverter pair pair Q t1=1, Q t1=0 Q t1=0, Qt1=1 Q t1=qt0,q t1=qt0 St1 = 1, Rt1 = 1 Qt1= 0, Qt1= 0 is forbidden state or not allowed state 9

10 Asynchronous CMOS NOR SR Latch Operation SET OP: S = 1, R = 0 Let at t = t0: Q t0 =0, Q t0 =V DD -> initial state At t = t1 > t0: St1= 1 Q t1=0 Rt1= 0 Q t1=1 Q t1=1 Q t1=0 Q t1=0 -> set state 10

11 Asynchronous CMOS NOR SR Latch Operation - cont. RESET OP: R = 1, S = 0 -> initial state -> reset state 11

12 Asynchronous CMOS NOR SR Latch Operation - cont. HOLD OP: S = 0, R =

13 Asynchronous CMOS NOR SR Latch Operation - cont. HOLD OP: S = 0, R =

14 Asynchronous CMOS NOR SR Latch Operation - cont. NR2 Q NR2 Q CQ = Cload-NR2Q = 2Cn-int + 3Cp-int + Cext CQ = Cload-NR2Q = 2Cn-int + 3Cp-int + Cext * rise,q (SR Latch) * rise,q (NR2)%* fall, Q' ( NR2) 14

15 Asynchronous Latch Circuits - cont. t0 t0 ACTIVE HIGH 15

16 Asynchronous CMOS NAND SR Latch Circuit Is NAND OR NOR SR LATCH PREFERRED? ACTIVE LOW 16

17 Asynchronous CMOS NAND SR Latch Circuit - cont. t1 > t0 17

18 CMOS Level Sensitive Synchronous Latches SR LATCH: NANDSR SRLatch LATCH NOTE: S and R are NAND asynchronous. S Sor orr NAND SR FLIP FLOP S' S' or or R' R' R S't1 R't1 CK CK When CK = 0, S' = R' =1 independent of the values of S and R => HOLD HOLD STATE: CK = 0, S = x, R = x => S' = 1, R' = 1 => Qn+1 = Qn, Qn+1 = Qn SET STATE: CK = 1, S = 1, R = 0 => S' = 0, R' = 1 => Qn+1 = 1, Qn+1 = 0 RESET STATE: CK = 1, S = 0, R = 1 => S' = 1, R' = 0 => Qn+1 = 0, Qn+1 = 1 NOT ALLOWED: CK = 1, S = 1, R = 1 => S' = 0, R' = 0 IS CK = 1, S = 0, R = 0 a HOLD STATE? ACTIVE HIGH 18

19 CMOS Level Sensitive Synchronous Latches - cont. HOLD STATE: CK = 1, S = 0, R = 0 NOT ALLOWED: CK = 1, S = 1, R = 1 T glitch T glitch&*rise,q Q error due to glitch on S R 19

20 CMOS Level Sensitive Synchronous Latches - cont. S' Another Gate Level Gate levelofschematic schematic a of clocked NAND Clocked NAND based SR Latch or Based Latch SR Flip Flop S't1 R't1 Flip-Flop R' SR LATCH When CK = 1, S' = R' =1 independent of the values of S and R => HOLD Set and Reset operations only occur when CK = 0. S' = R' = 0 ACTIVE LOW 20

21 CMOS Level Sensitive Synchronous Latches - cont. CMOS NAND Based Clocked SR Latch SR Latch 1 1 ACTIVE LOW 21

22 CMOS Level Sensitive Synchronous Latches - cont. CMOS NAND Based SR Clocked Latch CK = 1 SR Flip Flop CK = 1 When CK = 1, the latch state Q and Q is independent of inputs S and R, and the latch is in Hold operation. 22

23 CMOS Level Sensitive Synchronous Latches - cont. CMOS NAND Based SR Clocked Latch CK = 0 Latch CK = 0 When CK = 0, the state Q and Q depend on inputs S and R, and the schematic reduces to that of a NAND based SR latch. 23

24 CMOS Level Sensitive Synchronous Latches - cont. NAND BASED JK Synchronous Latch NAND SR CK = 1 => active S = R 0 for all values of J, K, CK LATCH 24

25 NAND JK Synchronous Latch Operation CK = 0 => Hold i.e. S = R = 1 independent of J, K CK = 1 => active ACTIVE HIGH SR LATCH The not-allowed S, R values S = R = 0 do not occur for any values of J, K, CK. reset (hold) set (hold) not desirable, but the state Qn+1, Qn+1 is not forbidden 25

26 NAND Based JK Synchronous Latch in Toggle Mode (high speed clock may be impractical) FLIP FLOP 2nd TIME) 26

Clocked Negative Edge Triggered SR Flip-Flop (FF) SR-NAND Latch 1 (master) S X SR-NAND Latch 2 (slave) Y Q1 Q2 CK = 1 Xt1 X't1 CK R X' Y' Q1 Q2 - S+ =Synchronous R = 0 are Not Op Allowed

27 Clocked Negative Edge Triggered SR Flip-Flop (FF) SR-NAND Latch 1 (master) S X SR-NAND Latch 2 (slave) Y Q1 Q2 CK = 1 Xt1 X't1 CK R X' Y' Q1 Q2 - S+ =Synchronous R = 0 are Not Op Allowed InputsSensitive + Not Level - S, R = 1 Not Allowed CK Start with CK = 0 => X = X' = 1, Latch 1 is Hold => Q1, Q1 are independent of S, R. Changes in S, R can't change the state of Latch 1 nor the state Q2, Q2 of Latch 2. When CK = 1, inputs S, R control the state of Latch 1. Inverted CK = 0 applied to Latch 2 (=> Y = Y' = 1) and Latch 2 is Hold and state Q2, Q2 are independent of Q1, Q1. When CK = 1 changes to S, R are tracked by Latch 1, but not reflected in the state Q2, Q2 of Latch 2. When CK = 0, the state of Latch 1 Q1, Q1 are independent of inputs S, R. to propagate to Latch2. Inverted CK = 1 enables the Held state of Latch 1 to effect the state Q2, Q2 of Latch 2. CK 1 to 0 is the the falling (negative) edge of the CK signal. 27

Sensitive + No Q2, Q2 Oscillation when J = K = 1; i.e. toggle of JK-Latch1 is not seen by

28 Clocked Negative Edge Triggered JK Flip-Flop JK Latch 1 J S1 JK Latch 2 S2 Q1 Q2 CK K R1 Q1 R2 CK Q2 CK = 1 Q1n-1Q1n-1 Q1n Q1n + Synchronous Operation + No Not-Allowed States + Not Level Sensitive + No Q2, Q2 Oscillation when J = K = 1; i.e. toggle of JK-Latch1 is not seen by JKLatch2 - Complex circuit, requiring 42 transistors - Note: SR FF circuit requires 32 transistors 28

29 Static CMOS D-LATCH Gate level implementation by modifying a NAND SR Latch. S LATCH R 18 Transistors Qn+1 0 SR-Set 1 SR-Reset Qn SR-Hold IN1 IN2 + NO TOGGLE + NO NOT-ALLOWED INPUTS IN2 CK D 1 0 x S' R' Qn Qn OUT IN1 29

30 Static CMOS TG D-LATCH Eight Transistors 8 Transistors **Transistor level implementation using transmission gates requires fewer transistors 30

31 CMOS TG D-LATCH Operation CK Q D Q CK CK CK D Q Q CK =1 D Q Q CK =0 Since when CK = 1 output Q = D, and tracks D until CK = 0, the D-Latch is referred to positive level triggered. When CK 1 to 0, the Q = D is captured, held (or stored) in the Latch. 31

32 D-LATCH Timing Requirements CLK NEG(pos) NEG(pos) NEG(pos) 32

33 D-Latch Metastability and Synchronization Failures latch, latch, the flip-flop output to 0 or 1. case) 33

34 CMOS D Edge Triggered Flip-Flop Negative Level Triggered D Latch Positive Level Triggered D Latch Positive Edge Triggered D Flip-Flop = Negative D-Latch + Positive D-Latch Negative Edge Triggered D Flip-Flop = Positive D-Latch + Negative D-Latch 34

35 CMOS D Flip-Flop Positive Edge Triggered slave (pos. D) i.e. positive level sensitive master (neg. master (neg. D) D) i.e. negative level sensitive unaffected by unaffected by unaffected by 35

36 Impact of Non-ideal Clock on D-Latch Operation CLK CLK CLK & CLK non-ideal ideal CLK t t CLK + τd CLK & CLK + τd 36

37 Two-Phase Clocked D-Latch φ1 t φ2 t φ1 φ1 φ2 φ2 37

38 Practical CMOS D Edge Triggered Flip-Flop NOT Practical φ1 φ2 Practical φ1 φ2 38

39 CMOS Dynamic D Latch D Q Cx is usually a parasitic capacitance Positive levelsensitive 39

40 Comparison CMOS Static & Dynamic D Latches φ1 φ2 φ1 φ2 Static D-Latch Data bit stored in bistable-loop when φ1 = 1 0 Dynamic D-Latch Data bit stored on Cx when CK =

41 CMOS Static & Dynamic D FFs φ2 φ1 φ1 φ2 φ1 φ1 φ2 φ2 41

EEC 118 Lecture #9: Sequential Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #9: Sequential Logic Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Outline Review: Static CMOS Logic Finish Static CMOS transient analysis Sequential