ELCT201: DIGITAL LOGIC DESIGN

Transcription

1 ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, Dr. Eng. Wassim Alexan, Lecture 6 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter 2017

2 COURSE OUTLINE 1. Introduction 2. Gate-Level Minimization 3. Combinational Logic 4. Synchronous Sequential Logic 5. Registers and Counters 6. Memories and Programmable Logic 2

3 LECTURE OUTLINE Sequential Circuits Introduction Memory Types Latches SR Latch D Latch Flip flops Master-Slave SR and D flip-flops Edge-Triggered D, JK and T flip-flops Flip-flops: Representation Summary of Terminology 3

4 COMBINATIONAL LOGIC CIRCUITS These are circuits that use logic gates, where the output depends only on the current inputs w x y F z 4

5 SEQUENTIAL LOGIC CIRCUITS These are circuits where the outputs depend on the sequence of past outputs As a result, such a circuit must remember something about the past Example: In a football game The current score = the previous goals (state) + new goal (input) For example, if you have a previous goal score of 5 and there is a new goal, then the final score will be 6 5

6 SEQUENTIAL LOGIC CIRCUITS A circuit with memory, whose outputs depend on the current input and the sequence of past outputs, is called a sequential circuit The behavior of such a circuit may be described by a state table that specifies its output and next state as functions of its current state and input 6

7 TYPES OF SEQUENTIAL LOGIC CIRCUITS 1. Synchronous, where the behavior of the circuit depends on the input signal at discrete instances of time (also called clocked) 2. Asynchronous, where the behavior of the circuit depends on the input signals at any instance of time and the order of the inputs change A combinational logic circuit with feedback 7

8 STORAGE ELEMENTS What is required from a storage element? Store data (hold) Accept writing new data (write) Read the stored data 8

9 TYPES OF STORAGE ELEMENTS Latches SR D Flip-flops Master-slave Edge-triggered D JK T Before going in detail regarding storage elements, we must understand what a clock signal is 9

10 DEFINING THE CLOCK A clock signal is a particular type of signal that oscillates between a high and a low state and is utilized to coordinate actions of circuits A clock signal is produced by a clock generator While other more complex arrangements are also in use, the most common clock signal takes the form of a square wave, with 50% duty cycle, usually with a fixed, constant frequency Circuits using a clock signal for synchronization may become active at either the rising or the falling edge of a clock cycle Clk 10

11 CLOCK PULSES A clock pulse can be positive or negative Positive pulse Negative pulse Positive edge Negative edge Negative edge Positive edge 11

12 BASIC MEMORY ELEMENTS A basic memory element consists of two cascaded inverters and the output of the last inverter is fed back into the input of the first inverter Q and Q are the outputs of the memory element Such a memory element will always store a single bit Such a memory element is called a Latch 1 Q = 0 Q = 1 12

13 STORAGE ELEMENTS But how to write a new value in this latch? We need a special technique that enables us to do this writing action 1 Q = 0 Q = 1 13

14 SR LATCH USING NOR GATES R S Q Q S R Q Q Circuit Graphic symbol Characteristic table 14

15 SR LATCH USING NOR GATES The SR latch is constructed with two cross-coupled NOR gates and two inputs labelled S for set and R for reset The SR latch has two useful states When the output Q = 1 and Q = 0, the latch is said to be in the set state When Q = 0 and Q = 1, it is in the reset state Outputs Q and Q are normally the complement of each other 15

16 SR LATCH USING NOR GATES The SR latch can store only 1 bit If both inputs are equal to 1 at the same time, a condition in which both new outputs are equal to 0 occurs (irrespective of the old output values) If both inputs are then switched to 0 simultaneously, the device will enter an undefined state In practice, setting both inputs to 1 is forbidden! 16

17 SR LATCH USING NOR GATES Writing a 1 into the memory cell set state R Q S Q 17

18 SR LATCH USING NOR GATES Hold the written data in the memory cell hold state R Q S Q 18

19 SR LATCH USING NOR GATES Writing a 0 into the memory cell reset state R Q S Q 19

20 SR LATCH USING NOR GATES Hold the written date in the memory cell hold state R Q S Q 20

21 SR LATCH USING NOR GATES Having both inputs equal to 1 in the memory cell forbidden state Because if S and R go to the hold state after being both equal to 1, the memory cell will go into an undefined state R Q S 1 10 Q 21

22 SR LATCH USING NOR GATES R S Q Q Timing diagram 22

23 SR LATCH USING NAND GATES Also known as the S R latch S Q R Q S R Q Q Circuit Graphic symbol Characteristic table 23

24 SR LATCH USING NAND GATES The outputs of the latch are Q and Q After each write operation there must be a hold operation to store the data Writing a 1 into the cell means set (S = 0 & R = 1) The hold state means store the data (S = R = 1) Writing a 0 into the cell means reset (R = 0 & S = 1) For S = R = 0, this is an unstable condition The S R latch (SR latch using NAND gates) can store only one bit 24

25 SR LATCH: IMPLEMENTATION COMPARISON R Q S Q S Q R Q S R Q Q S R Q Q set hold reset hold reset hold set hold Forbidden case

26 GATED SR LATCH USING NAND GATES S Can we hold (store) the value at the outputs unchanged, even if the inputs keep changing? Q En S R Next state of Q 0 X X No change No change En R Q Q = Q = Undefined Circuit Characteristic table 26

27 GATED SR LATCH USING NAND GATES The control input En acts as an enable signal for the other two inputs The outputs of the first two NAND gates stay at the logic-1 level as long as the enable signal remains at 0 When the enable input goes to 1, information from S or R input is allowed to affect the latch The set state is reached with S = 1, R = 0 and En = 1 The reset state is reached with S = 0, R = 1 and En = 1 In either case, when En returns to 0, the circuit remains in its current state, irrespective of any later changes to S or R An undefined condition occurs when S = R = En = 1. As this places 0s on both inputs of the basic SR latch, which puts in in the undefined state 27

28 D LATCH (TRANSPARENT LATCH) Forces S and R to be complements of each other (so that they are never equal to 1 at the same time) D Q En Q 28

29 D LATCH (TRANSPARENT LATCH) Forces S and R to be complements of each other (so that they are never equal to 1 at the same time) En D Next state of Q 0 X No change 1 0 Q = Q = 1 Graphic symbol Characteristic table 29

30 D LATCH (TRANSPARENT LATCH) The D latch receives that designation from its ability to hold data in its internal storage It is suited for use as a temporary storage for binary info between a unit and its environment The binary information present at the data input of the D latch is transferred to the Q output when the enable input is asserted (En = 1) The output follows changes in the data input as long as the enable input is asserted (En = 1) This situation provides a path from input D to the output (thus the naming transparent latch) When the enable input is de-asserted (En = 0), the binary info that was present at the data input at the time the transition occurred is stored 30

31 THE LATCH TIMING PROBLEM What happens if Clk = 1? What will be the value of Q when the Clk goes to 0? Problem: A latch is transparent, its state keeps changing as long as the clock remains active Due to this uncertainty, latches cannot be reliably used as storage elements 31

32 THE LATCH TIMING PROBLEM When latches are used as storage elements, a problem arises The state transitions of the latches start as soon as the clock pulse changes to the logic-1 level The new state of a latch appears at the output while the pulse is still active This output is connected to the inputs of the latches through the combinational circuit If the inputs applied to the latches change while the clock pulse is still at the logic-1 level, the latches will respond to new values and a new output state may occur 32

33 THE LATCH TIMING PROBLEM This is an unpredictable situation, since the state of the latches may keep changing as long as Clk = 1 Because of this unreliable operation, the output of a latch cannot be applied directly or through combinational logic to the input of the same or another latch when all the latches are triggered by a common clock source 33

34 FLIP-FLOPS A flip-flop is a one-bit memory cell, similar to latches A flip-flop solves the issue of latch transparency Latches are level sensitive memory elements (active as long as Clk = 1) Flip-flops are edge-triggered or edge-sensitive memory elements (active only at transitions; i.e. either 0 1 or 1 0) 34

35 RESPONSE OF LATCHES VS. FLIP-FLOPS Latch Flip-flop Flip-flop 35

36 LEVEL-SENSITIVE VS. EDGE-TRIGGERED STORAGE ELEMENTS D Clk Q a Q a Clk D Q b Q b Q a Q b Q c Q c Q c Timing diagram Circuit 36

37 FLIP-FLOP TYPES The commonly-used solution replaces the controlled D latch with a flip-flop We have two types of flip-flops Master-slave Edge-triggered 37

38 MASTER-SLAVE D FF USING LATCHES Clk D Y Q Timing diagram D Y Q Clk Circuit 38

39 MASTER-SLAVE D FF USING LATCHES The circuit samples the D input and changes its output Q only at the negative edge of the synchronizing or controlling clock When Clk = 0, the output of the inverter is 1 The slave latch is enabled and its output Q is equal to the master output Y The master latch is disabled because Clk = 0 D Y Q Clk Circuit 39

40 MASTER-SLAVE D FF USING LATCHES When the input pulse changes to the logic-1 level, the data from the external D is transferred to the master. The slave, however, is disabled as long as the clock remains at the logic-1 level, because its enable input is equal to 0 Any change in the input changes the master output at Y, but cannot affect the slave output D Y Q Clk Circuit 40

41 MASTER-SLAVE D FF USING LATCHES The value that is produced at the output of the flip-flop is the value that was stored in the master stage immediately before the negative edge occurred How to design a similar master-slave D flip-flop such that the output changes on the positive edge of the clock? D Y Q Clk Circuit 41

42 EDGE-TRIGGERED D FLIP-FLOP Sensitive to inputs only near the edge of the clock signal (not while high) signifies a positive edge Q(t) D Clk Q t Q pos Q neg Q pos Q neg 42

43 EDGE-TRIGGERED D FLIP-FLOP Sensitive to inputs only near the edge of the clock signal (not while high) This timing diagram is for a positive edge triggered D flip-flop Clk D Q Q Timing diagram 43

44 JK FLIP-FLOP USING D FLIP-FLOP Q t + 1 = D = JQ + K Q When J = K = 1, the output is complemented J sets the flip-flop to 1 K resets the flip-flop to 0 J K Clk Q Q Circuit Graphic symbol 44

45 T FLIP-FLOP USING JK FLIP-FLOP Q t + 1 = D = T Q T (toggle) flip-flop is a complementing flip-flop T = 0, no change T = 1, complement (toggle) T Q Q Circuit form JK FF Graphic symbol 45

46 T FF USING D FF Q t + 1 = D = T Q T (toggle) flip-flop is a complementing flip-flop T = 0, no change T = 1, complement (toggle) T Circuit form D FF Graphic symbol 46

47 FLIP-FLOPS: REPRESENTATION To represent any combinational circuit, we needed to write the truth table or logic function of the output To represent any flip-flop, we need to write the characteristic table, characteristic equation or excitation table A characteristic table defines the operation of a FF in a tabular form The next state is defined in terms of the current state and the inputs Q(t) refers to the current state (before the clock arrives) Q(t + 1) refers to the next state (after the clock arrives) Similar to the truth table in combinational circuits 47

48 FLIP-FLOPS: REPRESENTATION A characteristic equation defines the operation of a flipflop in an algebraic form For a D flip-flop: Q t + 1 For a JK flip-flop: Q t + 1 For a T flip-flop: Q t + 1 = D = JQ + K Q = T Q 48

49 Q t + 1 = JQ + K Q Q t + 1 = D Q t + 1 = T Q 49

50 FLIP-FLOPS: EXCITATION TABLES If we have the present and next output, what would be the input to the flip-flop that would lead to this output? Q(t) Q(t + 1) J K T D X X X X

51 STANDARD SYMBOLS FOR STORAGE ELEMENTS Latches Master-Slave Flip-flops Edge-Triggered Flip-flops 51

52 DIRECT INPUT (ASYNCHRONOUS INPUT) An example of an asynchronous sequential circuit is a counter circuit that counts the number of occurrences of some event Such a circuit is usually built using a number of flip-flops, whose outputs are interpreted as a number The counter circuit should be able to increment or decrement the number It is also important to be able to force the counter into a known initial state (count = 0), which means that all flip-flops must have Q = 0 Moreover, we should be able to preset each flip-flop to Q = 1, to insert some specific count as the initial value in the counter 52

53 DIRECT INPUT (ASYNCHRONOUS INPUT) These requirements can all be satisfied by incorporating a Clear and Preset inputs into the design of a flip-flop These extra inputs are called asynchronous because they can set or reset the flip-flop regardless of the status of the Clk signal Negative edge triggered D flip flop with Clear and Preset 53

54 SUMMARY OF TERMINOLOGY A basic latch is a feedback connection of two NOR gates or two NAND gates, which can store one bit of information. The NORbased latch can be set to 1 using the S input and reset to 0 using the R input A gated (clocked) latch is a basic latch that includes input gating and a control input signal. The latch retains its existing state when the control input is equal to 0. Its state may be changed when the control signal is equal to 1. We referred to this control input as the clock A gated (clocked) SR latch uses the S and R inputs to set the latch to 1 or reset it to 0, respectively A gated (clocked) D latch uses the input D to force the latch into a state that has the same logic value as the D input 54

55 SUMMARY OF TERMINOLOGY A flip-flop is a storage element based on the gated latch principle, which can have its output state changed only on the edge of the controlling clock signal A Master-slave flip-flop is built with two gated latches. The master stage is active during half of the clock cycle, and the slave stage is active during the other half. The output value of the flip-flop changes on the edge of the clock that activates the transfer into the slave stage An edge-triggered flip-flop is affected only by the input values present when the active edge of the clock occurs 55