NT Output LCD Segment/Common Driver. Features. General Description. Pin Configuration 1 V1.0 NT7702
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1 240 Output LCD Segment/Common Driver Features (Segment mode)! Shift Clock frequency: 20 MHz (Ma.) (VDD = 5 V ± 10%)! Adopts a data bus system! 4-bit/8-bit parallel input modes are selectable with a mode () pin! Automatic transfer function with an enable signal! Automatic counting function when in the chip select mode, causes the internal clock to be stopped by automatically counting 240 bits of input data (Common mode)! Shift clock frequency : 4.0 MHz (Ma.)! Built-in 240-bits bidirectional shift register (divisible into 120-bits 2) General Description! Available in a single mode (240-bits shift register) or in a dual mode(120-bits shift register 2) Single mode Single mode , Dual mode , Dual mode The above 4 shift directions are pin-selectable (Both for segment mode and common mode)! Supply voltage for LCD driver: 15.0 to 30.0 V! Number of LCD driver outputs: 240! Low output impedance! Low power consumption! Supply voltage for the logic system: +2.5 to +5.5 V! COMS process! Package: 272pin TCP (Tape Carrier Package)! Not designed or rated as radiation hardened The NT7702 is a 240-bit output segment/common driver LSI suitable for driving large scale dot matri LCD panels using as PDA/personal computers/work stations. Through the use of SST (Super Slim TCP) technology, it is ideal for substantially decreasing the size of the frame section of the LCD module. The NT7702 is good as both a segment driver and as a common driver, and a low power consuming, highprecision LCD panel display can be assembled using the NT7702. In the segment mode, the data input is selected as 4bit parallel input mode or as 8bit parallel input mode by a mode () pin. In the common mode, the data input/output pins are bi-directional and the four data shift directions are pin-selectable. Pin Configuration D U M M D U M M NT D V V V V V V V S E D D D D D D D D X D L E F L M N V N V V V V V D U S D / I C I P I R / D C S C U M L L 2 3 L S D C O K S O R S R 3 2 R R M M L L 2 P 1 R R M O F F 1 V1.0
2 Pad Configuration ALK_L Dummy Pad NT7702 Dummy Pad ALK_R Block Diagram V0R V12R V43R V5R Level Shifter 240 Bits 4 Level Driver /240 V5L V43L V12L 240 Bits Level Shifter V0L Active Control / Bits Line Latch/Shift Register /16 /16 /16 /16 /16 Control Logic 8Bits2 Data Latch /8 Data Latch Control S/C SP Conversion & Data Control (4 to 8 or 8 to 8) D0 D1 D2 D3 D4 D5 D6 D7 VDD 2
3 Pin Description Pin No. Designation I/O Description 1, 2 V0L P Power supply for LCD driver 3 V12L P Power supply for LCD driver 4 V43L P Power supply for LCD driver 5 V5L P Power supply for LCD driver 6 P Ground (0V), these two pads must be connected to each other 7 VDD P Power supply for the logic system (+2.5 to +5.5V) 8 S/C I Segment mode/common mode selection 9 I/O Input/output for chip select or data of the shift register D0 - D6 I Display data input for segment mode 17 D7 I Display data input for Segment mode/ Dual mode data input 18 I Display data shift clock input for segment mode 19 I Control input for deselect output level 20 I Latch pulse input/shift clock input for the shift register 21 I/O Input/output for chip select or data of the shift register 22 I AC-converting signal input for LCD driver waveform 23 I Display data shift direction selection 24 I Mode selection input 25, 27 NC - No connected 26 P Ground (0V), these two pads must be connected to each other 28 V5R P Power supply for LCD driver 29 V43R P Power supply for LCD driver 30 V12R P Power supply for LCD driver 31, 32 V0R P Power supply for LCD driver O LCD driver output 3
4 Pad Description Pad No. Designation I/O Description 1, 2 V5L P Power supply for LCD driver 3, 4 P Ground (0V), these two pads must be connected to each other 5, 6 VDD P Power supply for the logic system (+2.5 to +5.5V) 7, 8 S/C I Segment mode/common mode selection 9, 10 I/O Input/output for chip select or data of the shift register 11, 12-23, 24 D0 - D6 I Display data input for segment mode 25, 26 D7 I Display data input for Segment mode/ Dual mode data input 27, 28 I Display data shift clock input for segment mode 29, 30 I Control input for deselect output level 31, 32 I Latch pulse input/shift clock input for the shift register 33, 34 I/O Input/output for chip select or data of the shift register 35, 36 I AC-converting signal input for LCD driver waveform 37, 38 I Display data shift direction selection 39, 40 I Mode selection input 41, 42 P Ground (0V), these two pads must be connected to each other 43, 44 V5R P Power supply for LCD driver 45, 46 V43R P Power supply for LCD driver 47, 48 V12R P Power supply for LCD driver 49, 50 V0R P Power supply for LCD driver O LCD driver output 291, 292 V0L P Power supply for LCD driver 293, 294 V12L P Power supply for LCD driver 295, 296 V43L P Power supply for LCD driver 4
5 Input / Output Circuits VDD I Input Signal Applicable Pins, S/C, D0 - D6,,,, Input Circuit (1) VDD I Input Signal Control Signal Applicable Pins D7, Input Circuit (2) 5
6 VDD Input Signal Control Signal VDD Output Signal I/O Control Signal Applicable Pins, Input / Output Circuit V0 V12 Control Signal 1 Control Signal 2 O Control Signal 3 V43 V5 Control Signal 4 Applicable Pins 1 to 240 LCD Driver Output circuit 6
7 Pad Description Segment mode Symbol VDD VOR, VOL V12R, V12L V43R, V43L V5R, V5L D0 - D7 Function Logic system power supply pin connects to +2.5 to +5.5V Ground pin connects to 0V Power supply pin for LCD driver voltage bias " Normally, the bias voltage used is set by a resistor divider " Ensure that the voltages are set such that V5 < V43 < V12 < V0 " To further reduce the differences between the output waveforms of the LCD driver output pins 1 and 240, eternally connect ViR and ViL (I = 0, 12, 43, 5) Input pin for display data " In 4-bit parallel input mode, input data into the 4 pins D0 - D3. Connect D4 - D7 to or VDD " In 8-bit parallel input mode, input data into the 8 pins D0 - D Clock input pin for taking display data " Data is read on the falling edge of the clock pulse Latch pulse input pin for display data " Data is latched on the falling edge of the clock pulse Direction selection pin for reading display data " When set to level "L", data is read sequentially from 240 to 1 " When set to VDD level "H", data is read sequentially from 1 to 240 Control input pin for output deselect level " The input signal is level-shifted from logic voltage level to LCD driver voltage level, and controls LCD driver circuit. " When set to level L, the LCD driver output pins (1-240) are set to level V5 " While set to L, the contents of the line latch are reset, but read the display data in the data latch are read regardless of the condition of. When the function is canceled, the driver outputs deselect level (V12 or V43), then outputs the contents of the date latch onto the net falling edge of the. That time, if removal time can not keep regulation what is shown AC characteristics, can not output the reading data correctly AC signal input for LCD driving waveform " The input signal is level-shifted from the logic voltage level to the driver voltage level and controls the LCD driver circuit. " Normally inputs a frame inversion signal The LCD driver output pin s output voltage level can be set to the line latch output signal and the signal Mode selection pin " When set to level L, 8-bit parallel input mode is set " When set to VDD level H", 4-bit parallel input mode is set 7
8 Segment mode continued Symbol S/C, Segment mode/common mode selection pin " When set to VDD level "H", segment mode is set " When set to level "L", common mode is set Function Input/output pin for chip selection " When input is at level L, is set for output, and is set for input " When input is at VDD level H, is set for input, and is set for output " During output, it is set to H while * is H and after 240-bits of data have been read, it is set to L for one cycle (from falling edge to falling edge of ), after which it returns to H " During input, after the signal is input, the chip is selected while EI is set to L. After 240-bits of data have been read, the chip is deselected LCD driver output pins These correspond directly to each bit of the data latch, one level (V0, V12, V43, or V5) is selected and output Common mode Symbol VDD V0R, V0L V12R, V12L V43R, V43L V5R, V5L Function Logic system power supply pin connects to +2.5 to +5.5V Ground pin connects to 0V Power supply pin for LCD driver voltage bias. " Normally, the bias voltage used is set by a resistor divider " Ensure the voltages are set such that V5 <V43 < V12 < V0 To further reduce the differences between the output waveforms of the LCD driver output pins 1 and 240, eternally connect ViR and ViL (I = 0, 12, 43, 5) Bi-directional shift register shift data input/output pin " Is an output pin when is at level L and an input pin when is at VDD level H " When is used as an input pin, it will be pulled-down " When is used as an output pin, it won t be pulled-down Bi-directional shift register shift data input/output pin " Is an input pin when is at level L and an output pin when is at VDD level H " When is used as input pin, it will be pulled-down " When is used as output pin, it won t be pulled-down Bi-directional shift register shift clock pulse input pin " Data is shifted on the falling edge of the clock pulse Bi-directional shift register shift direction selection pin " Data is shifted from 240 to 1 when it is set to level L, and data is shifted from 1 to 240 when it is set to VDD level H 8
9 Common mode continued Symbol D7 S/C D0 - D Function Control input pin for output deselect level " The input signal is level-shifted from the logic voltage level to the LCD driver voltage level, and controls the LCD driver circuit " When set to level L, the LCD driver output pins (1-240) are set to level V5 " While set to L, the contents of the shift resister are reset and are not reading data. When the function is canceled, the driver outputs deselect level (V12 or V43), and the shift data is read on the falling edge of the. That time, if removal time can not keep regulation what is shown AC characteristics, the shift data is not reading correctly AC signal input for LCD driving waveform " The input signal is level-shifted from logic voltage level to the LCD driver voltage level, and it controls the LCD driver circuit " Normally, inputs a frame inversion signal The LCD driver output pin s output voltage level can be set using the shift register output signal and the signal Mode selection pin " When set to level L, Single Mode operation is selected. When set to VDD level H, Dual Mode operation is selected Dual Mode data input pin " According to the data shift direction of the data shift register, data can be input starting from the 121st bit When the chip is used as Dual Mode, D7 will be pulled-down When the chip is used as Single Mode, D7 won t be pulled-down Segment mode/common mode selection pin " When set to level L, common mode is set Not used " Connect D0-D6 to or VDD. Avoiding floating Not used " is pull-down in common mode, so connect to or open LCD driver output pins " These correspond directly Corresponding directly to each bit of the shift register, one level (V0, V12, V43, or V5) is selected and output 9
10 Functional Description 1. Block description 1.1 Active Control In the case of the segment mode, it controls the selection or deselection of the chip. Following a signal input, and after the select signal is input, a select signal is generated internally until 240 bits of data have been read in. Once data input has been completed, a select signal for cascade connection is output, and the ship is deselected. In the case of the common mode, it controls the input/output data of the bi-directional pins SP Conversion & Data Control In the case of the segment mode, keep input data which are 2 clocks of at 4-bit parallel mode into latch circuit, or keep input data which are 1 clock of at 8-bit parallel mode into latch circuit, after that they are put on the internal data bus 8 bits at a time Data Latch Control In the case of the segment mode, selects the state of the data latch, which reads in the data bus signals. The shift direction is controlled by the control logic and for every 16 bits of data read in, the selection signal shifts one bit, based on the state of the control circuit Data Latch In the case of the segment mode, latches the data on the data bus. The latched state of each LCD driver output pin is controlled by the control logic and the data latch control 240 bits of data are read in 20 sets of 8 bits Line Latch/Shift Register In the case of the segment mode, all 240 bits which have been read into the data latch, are simultaneously latched on to the falling edge of the signal, and output to the level shift block. In the case of the common mode, it shifts data from the data input pin on to the falling edge of the signal Level Shifter The logic voltage signal is level-shifted to the LCD driver voltage level, and output to the driver block Level Driver It drives the LCD driver output pins from the line latch/shift register data, selecting one of 4 levels (V0, V12, V43, V5) based on the S/C, and signals Control Logic Controls the operation of each block. In case of segment mode, when an signal has been input, all blocks are reset and the control logic waits for the selection signal output from the active control block. Once the selection signal has been output, operation of the data latch and data transmission are controlled, 240 bits of data are read in, and the chip is deselected. In the case of the common mode, it controls the direction of data shift. 10
11 2. LCD Driver Output Voltage Level The relationship amongst the data bus signal, AC converted signal and LCD driver output voltage is as shown in the table below: 2.1. Segment Mode Latch Data Driver Output Voltage Level (1-240) L L H V43 L H H V5 H L H V12 H H H V0 X X L V5 Here, V5 < V43 < V12 < V0, H: VDD (+2.5 to +5.5V), L: (0V), X: Don't care 2.2. Common Mode Latch Data Driver Output Voltage Level (1-240) L L H V43 L H H V0 H L H V12 H H H V5 X X L V5 Here, V5 < V43 < V12 < V0, H: VDD (+2.5 to +5.5V), L: (0V), X: Don't care Note: There are two kinds of power supply (logic level voltage, LCD driver voltage) for the LCD driver. Please supply regular voltage which assigned by specification for each power pin. That time "Don't care" should be fied to "H" or "L", avoiding floating. 11
12 3. Relationship between the Display Data and Driver Output pins 3.1. Segment Mode: (a) 4-bit Parallel Mode H L Output Input H H Input Output Data Number of Clock Input 60clock 59clock 58clcok ~ 3clock 2clock 1clock D ~ D ~ D ~ D ~ D ~ D ~ D ~ D ~ (b) 8-bit Parallel Mode L L Output Input L H Input Output Data Number of Clock Input 30clock 29clock 28clcok ~ 3clock 2clock 1clock D ~ D ~ D ~ D ~ D ~ D ~ D ~ D ~ D ~ D ~ D ~ D ~ D ~ D ~ D ~ D ~
13 3.2. Common Mode Data Transfer Direction D7 L L (shift to left) 240 to 1 Output Input X (Single) H (shift to right) 1 to 240 Input Output X H (Dual) L (shift to left) H (shift to right) 240 to to 1 1 to to 240 Output Input Input Input Output Input Here, L: (0V), H: VDD (+2.5V to +5.5V), X: Don't care Note: "Don't care" should be fied to "H" or "L", avoiding floating. 13
14 4. Connection Eamples of Segment Drivers 4.1. Case of = L first data last data (data taking flow) > > >1 D0~D7 D0~D7 D0~D7 D0~D7 / Case of = H VDD D0~D7 /8 D0~D7 D0~D7 D0~D >240 first data (data taking flow) > >240 last data 14
15 5. Timing waveform of 4-Device cascade Connection of Segment Drivers D0~D7 First data n12 n12 n12 n12 n12 device A device B device C device D Last data EI (device A) H L EO (device A) EO (device B) EO (device C) n: 4-bit parallel mode 60 8-bit parallel mode 30 15
16 6. Connection Eamples for Common Drivers First Last D D7 CS D7 CS D7 CS (VDD) CS Single Mode (Shifting towards the left) (VDD) D D7 D7 D First Last Single Mode (Sifting towards the right) 16
17 First1 Last1 First2 Last D1 D7 D7 D7 D2 (VDD) VDD Dual mode (Shifting towards the left) VDD (VDD) D2 D1 D7 D7 D First1 Last1 First2 Last2 Dual mode (Shifting towards the right) 17
18 7. Precaution Be careful when connecting or disconnecting the power This LSI has a high-voltage LCD driver, so it may be permanently damaged by a high current, which may occar, if a voltage is supplied to the LCD driver power supply while the logic system power supply is floating. The details are as follows:! When connecting the power supply, connect the LCD driver power after connecting the logic system power. Furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the LCD driver power.! We recommend that you connect a serial resistor ( Ω) or fuse to the LCD driver power V0 of the system as a current limiting device. Also, set a suitable value of the resistor in consideration of LCD display grade. In addition, when connecting the logic power supply, the logic condition of this LSI inside is insecure. Therefore connect the LCD driver power supply after resetting the logic condition of this LSI inside to function. After that, the cancel the function after the LCD driver power supply has become stable. Furthermore, when disconnecting the power, set the LCD driver output pins to level V5 on the function. After that, disconnect the logic system power after disconnecting the LCD driver power. When connecting the power supply, follow the recommended sequence shown. VDD VDD VDD V0 V0 18
19 Absolute Maimum Rating* DC Supply Voltage VDD V to +7.0V DC Supply Voltage V V to +30V Input Voltage V to VDD +0.3V Operating Ambient Temperature C to +85 C Storage Temperature C to +125 C *Comments Stresses above those listed under "Absolute Maimum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device under these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Eposure to the absolute maimum rating conditions for etended periods may affect device reliability. Electrical Characteristics DC Characteristics Segment Mode ( = V5 = 0V, VDD = V, V0 = 15 to 30 V, and TA = -30 to +85 C, unless otherwise noted) Parameter Symbol Min. Typ. Ma. Unit Condition Operating Voltage 1 VDD V Operating Voltage 2 V V Input high voltage VIH 0.8 VDD - - V D0-7,,,,,, S/C,, Input low voltage VIL VDD V, pins Output high voltage VOH VDD V, pins, IOH = -0.4mA Output low voltage VOL V, pins, IOL = +0.4mA Input leakage current 1 IIH µa D0-7,,,,,, S/C,,, pins, VI = VDD Input leakage current 2 IIL µa D0-7,,,,,, S/C,,, pins, VI = Output resistance RON V0 = +30.0V kω V0 = +20.0V Stand-by current ISB µa pin, Note 1 Consumed current (1) (Deselection) Consumed current (2) (Selection) IDD ma VDD pin, Note 2 IDD ma VDD pin, Note 3 Consumed current I ma V0 pin, Note pins, V O N = 0.5V Note: 1. VDD = +5.0V, V0 = +30V, VI = 2. VDD = +5.0V, V0 = +30V, f = 20MHz, No-load, EI = VDD The input data is turned over by the data taking clock (4-bit Parallel input mode) 3. VDD = +5.0V, V0 = +30V, f = 20MHz, No-load. EI = The input data is turned over by the data taking clock (4-bit parallel input mode) 4. VDD = +5.0V, V0 = +30V, f = 20MHz, f = 41.6kHz. f = 80 Hz, No-load The input data is turned over by the data taking clock (4-bit parallel-input mode) 19
20 Common Mode ( = V5 = 0V, VDD = V, V0 = 15 to 30 V, and TA = -30 to +85 C, unless otherwise noted) Parameter Symbol Min. Typ. Ma. Unit Condition Operating Voltage VDD V Operating Voltage V V Input high voltage VIH 0.8 VDD - - V D0-7,,,,,, S/C,, Input low voltage VIL VDD V, pins Output high voltage VOH VDD V, pins, IOH = -0.4mA Output low voltage VOL V, pins, IOL = +0.4mA Input leakage current 1 IIH µa D0-6,,,,, S/C and pins, VI = VDD Input leakage current 2 IIL µa D0-7,,,,,, S/C,,, pins, VI = Input pull down current IPD µa,,, D7 pins Output resistance RON V0 = +30.0V kω V0 = +20.0V Stand-by current ISB µa pin, Note pins, V O N = 0.5V Consumed current (1) IDD µa VDD pin, Note 2 Consumed current (2) I µa V0 pin, Note 2 Note: 1. VDD = +5.0V, V0 = +30.0V, VI = 2. VDD = +5.0V, V0 = +30.0V, f = 41.6KHz, f = 80Hz, case of 1/480 duty operation, No-load 20
21 AC Characteristics Segment Mode 1 ( = V5 = 0V, VDD = V, V0 = 15 to 30V, and TA = -30 to +85 C, unless otherwise noted) Parameter Symbol Min. Typ. Ma. Unit Condition Shift clock period twck 50 - ns tr, tf 10ns, Note 1 Shift clock "H" pulse width twckh 15 - ns Shift clock "L" pulse width twckl 15 - ns Data setup time tds 10 - ns Data hole time tdh 12 - ns Latch pulse "H" pulse width twh 15 - ns Shift clock rise to Latch pulse rise time tld 0 - ns Shift clock fall to Latch pulse fall time tsl 30 - ns Latch pulse rise to Shift clock rise time tls 25 - ns Latch pulse fall to Shift clock rise time tlh 25 - ns Input signal rise time tr - 50 ns Note 2 Input signal fall time tf - 50 ns Note 2 Enable setup time ts 10 - ns Removal time tsd ns enable pulse width twdl µs Output delay time (1) td - 30 ns CL = 15pF Output delay time (2) tpd1, tpd2-1.2 µs CL = 15pF Output delay time (3) tpd3-1.2 µs CL = 15pF Note 1. Take the cascade connection into consideration. 2. (tck-twckii-twckl)/2 is the maimum in the case of high speed operation. 21
22 Segment Mode 2 ( = V5 = 0V, VDD = V, V0 = 15 to 30V, and TA = -30 to +85 C, unless otherwise noted) Parameter Symbol Min. Typ. Ma. Unit Condition Shift clock period twck 66 - ns tr, tf 10ns, Note 1 Shift clock "H" pulse width twckh 23 - ns Shift clock "L" pulse width twckl 23 - ns Data setup time tds 15 - ns Data hole time tdh 23 - ns Latch pulse "H" pulse width twh 30 - ns Shift clock rise to Latch pulse rise time tld 0 - ns Shift clock fall to Latch pulse fall time tsl 50 - ns Latch pulse rise to Shift clock rise time tls 30 - ns Latch pulse fall to Shift clock fall time tlh 30 - ns Input signal rise time tr - 50 ns Note 2 Input signal fall time tf - 50 ns Note 2 Enable setup time ts 15 - ns Removal time tsd ns enable pulse width twdl µs Output delay time (1) td - 41 ns CL = 15pF Output delay time (2) tpd1, tpd2-1.2 µs CL = 15pF Output delay time (3) tpd3-1.2 µs CL = 15pF Note 1. Take the cascade connection into consideration. 2. (tck-twckii-twckl)/2 is the maimum in the case of high speed operation. 22
23 Segment Mode 3 ( = V5 = 0V, VDD = V, V0 = 15 to 30V, and TA = -30 to +85 C, unless otherwise noted) Parameter Symbol Min. Typ. Ma. Unit Condition Shift clock period twck 82 - ns tr, tf 10ns, Note 1 Shift clock "H" pulse width twckh 28 - ns Shift clock "L" pulse width twckl 28 - ns Data setup time tds 20 - ns Data hole time tdh 23 - ns Latch pulse "H" pulse width twh 30 - ns Shift clock rise to Latch pulse rise time tld 0 - ns Shift clock fall to Latch pulse fall time tsl 65 - ns Latch pulse rise to Shift clock rise time tls 30 - ns Latch pulse fall to Shift clock fall time tlh 30 - ns Input signal rise time tr - 50 ns Note 2 Input signal fall time tf - 50 ns Note 2 Enable setup time ts 15 - ns Removal time tsd ns enable pulse width twdl µs Output delay time (1) td - 57 ns CL = 15pF Output delay time (2) tpd1, tpd2-1.2 µs CL = 15pF Output delay time (3) tpd3-1.2 µs CL = 15pF Note 1. Take the cascade connection into consideration. 2. (tck-twckii-twckl)/2 is the maimum in the case of high speed operation. 23
24 Timing waveform of the Segment Mode twh tld tsl tlh tls twckh twckl tr tr twck tds tdh D0 - D7 LAST DATA TOP DATA twdl tsd EI 1 2 ts n td EO n: 4-bit parallel mode 60 8-bit parallel mode 30 tpd1 tpd2 tpd
25 Common Mode ( = V5 = 0V, VDD = V, V0 = 15 to 30V and TA = -30 to +85 C, unless otherwise noted) Parameter Symbol Min. Typ. Ma. Unit Condition Shift clock period tw ns tr, tf 20ns Shift clock "H" pulse width twh ns VDD = +5.0V 10% ns VDD = V Data setup time tsu ns Data hole time th ns Input signal rise time tr - 50 ns Input signal fall time tf - 50 ns Removal time tsd ns enable pulse width twdl µs Output delay time (1) tdl ns CL = 15pF Output delay time (2) tpd1, tpd µs CL = 15pF Output delay time (3) tpd µs CL = 15pF 25
26 Timing Characteristics of Common Mode tw tr twh tf tsu th (DI7) tdl twdl tsd tpd1 tpd2 tpd
27 /8 NT7702 Application Circuit (for reference only) SEG640 SEG639 1~240 S/C D0~D7 1~240 S/C 1920*480 DOT MATRIX LCD PANEL 1~240 D0~D7 NT7702*4 S/C D0~D7 SEG3 1~240 C O M 1 C O M 2 C O M 3 C O M C O M SEG2 SEG1 S/C D0~D7 1~240 1~240 1~240 S/C D0~D7 S/C D0~D7 S/C D0~D7 D /5 /5 /8 50~100Ω NT7702*3 R R (n-4)r R R (case of 1/n bias) LCD controller XD0~XD7 VEE V0 V1 V2 V3 V4 V5 VDD 27
28 Bonding Diagram um ALK_L NT7702 ( 0, 0 ) X ALK_R um 45 Dummy Pad Dummy Pad 1 44 Pad Location Pad No. Designation X Pad No. Designation X 1 V5L V5L VDD VDD SC SC D D D V5R D V5R D V43R D V43R D V12R D V12R D V0R D V0R D D D D D D
29 Pad Location (continued) Pad No. Designation X Pad No. Designation X
30 Pad Location (continued) Pad No. Designation X Pad No. Designation X
31 Pad Location (continued) Pad No. Designation X Pad No. Designation X V0L V0L V12L V12L V43L V43L ALK_R ALK_L
32 Dummy Pad Location (Total: 35 pad) NO X NO X NO X NO X
33 Package Information A1 D3 D3 A1 A2 224m2n D1 A2 C1 D3 m1 m1 m2 n C2 m1 m1 C1 D3 D1 14nm2 m2 J r NT7702 r m2 J D1 14nm2 D3 C1 n m1 H C2 n m1 H m1 n D3 C1 B D2 71m1n B Chip Outline Dimensions unit: um Symbol Dimensions in um Symbol Dimensions in um A1 225 D3 60 A2 81 m1 57 B 260 m2 37 C1 105 n 59 C2 75 r 35 D1 50 H 117 D2 160 J
34 34 TCP Pin Layout NT DUMM V0L V0L V12L V43L V5L VDD S/C D0 D1 D2 D3 D4 D5 D6 D7 NC NC V5R V43R V12R V0R V0R DUMM DUMM DUMM (Copper Side View)
35 Eternal view of TCP pins 35
36 Cautions concerning storage: 1. When storing the product, it is recommended that it be left in its shipping package. After the seal of the packing bag has been broken, store the products in a nitrogen atmosphere. 2. Storage conditions : Storage state Storage conditions unopened (less than 90 days) Temperature: 5 to 30; humidity: 80%RH or less. After seal of broken (less than 30 days) Room temperature, dry nitrogen atmosphere 3. Don't store in a location eposed to corrosive gas or ecessive dust. 4. Don't store in a location eposed to direct sunlight of subject to sharp changes in temperature. 5. Don't store the product such that it is subjected to an ecessive load weight, such as by stacking. 6. Deterioration of the plating may occur after long-term storage, so special care is required. It is recommended that the products be inspected before use. 36
37 Tray Information f e X 5*33 X W1 W2 c d g T2 T1 SECTION - h W1 W2 g a b e f h T2 T1 SECTION X-X Symbol Dimensions in mm Symbol Dimensions in mm a 1.46 g 0.84 b 2.04 h 4.20 c W d W e 1.60 T f 1.40 T
38 Ordering Information Part No. NT7702H-BDT NT7702H-TABF4 Package Au bump on chip tray TCP Form With collaboration of 38
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