On the Rules of Low-Power Design

Transcription

1 On the Rules of Low-Power Design (and How to Break Them) Prof. Todd Austin Advanced Computer Architecture Lab University of Michigan Once upon a time 1

2 Rules of Low-Power Design P = acv 2 f + VI leak 1. Minimize switching activity 2. Design for lower load capacitance 3. Reduce frequency 4. Reduce leakage and the most important of all: 5. Decrease supply voltage! V th Critical voltage (determined by critical path) 1.2v Noise margin Ambient margin Process margin 0.v Overclockers Break the Rules 1.2v Noise margin Ambient margin Process margin 0.v V th 2

3 Goals of This Presentation Review some of the rules of low-power design Show how clever designs can break these rules Razor resilient circuits Subliminal subthreshold voltage processor Highlight the benefits of taking a rule-breaking approach to technical research Investigating Overclocking 3

4 Two Slow Pipelines Check a Fast Pipeline Slow Pipeline A 4-bit 4-bit LFSR LFSR 4-bit 4-bit LFSR LFSR 1 1 clk/2 clk/2 X 1x1 45 MHz Slow Pipeline B X 1x1 45 MHz Fast Pipeline X 1x stabilize clk/2 clk/2 clk/2!= 40-bit 40-bit Error Error Counter Counter clk 90 MHz clk clk Observation: Voltage Margins Are Plentiful 1x1-bit Multiplier Block at 90 MHz and 27 C 35% energy savings with 1.3% errors 20% energy savings Supply Voltage (V) 1.69 V 1.54 V % % % % % % % % % % % One error every 20 seconds! Margin grows if a few (~1%) errors can be tolerated Error rate 4

5 Razor Resilient Circuits Main FF Main FF MEM clk clk Shadow Latch 9 clk_del Double-sampling metastability tolerant latches detect timing errors Second sample is correct-by-design Microarchitectural support restores program state Timing errors treated like branch mispredictions Distributed Pipeline Recovery Cycle: inst1 inst2 inst5 inst6 inst7 inst inst3 inst4 inst2 PC IF Razor FF error ID bubble Razor FF error EX bubble Razor FF MEM (read-only) error bubble Razor FF error bubble Stabilizer FF WB (reg/mem) recover recover recover recover Flush flushid flushid flushid flushid Builds on existing branch prediction framework Multiple cycle penalty for timing failure Scalable design as all communication is local 5

6 Razor Prototype Design Six stage 64-bit Alpha pipeline 200MHz in 1.V tunable via sw from MHz, V 32-entry, 3-port RF, K I-Cache/K D-Cache Branch-not-taken branch predictor Full scan capability Razor overhead: 192 Razor FF out of 240 (9%) Error-free power overhead: Razor flip-flops: < 1% Short path buffer: 2.1% Recovery power overhead: 1x an inst, for pipeline recovery 3 mm I-Cache Register File WB IF ID EX D-Cache MEM 3.3 mm Razor Prototype Testbed 6

7 Razor-Based Dynamic Voltage Scaling E diff = E ref -E sample reset E ref - E diff Voltage Function Voltage Regulator V dd Pipeline error signals... Σ E sample Current design utilizes a very simple proportional control function algorithm implemented in software Example Voltage ler Response Percentage Error Rate Time (Seconds) ler Output Voltage(V) Two minute snapshot of a 15 minute run 7

8 Effects of Razor DVS Energy IPC Total Energy, E total = E proc + E recovery Pipeline Throughput 1% 50% Optimal E total Energy of Processor Operations, E proc Energy of Processor w/o Razor Support Decreasing Supply Voltage Energy of Pipeline Recovery, E recovery Razor Also Improves Yield Voltage at 0.1%Error Rate 1. Chips 1.7 Linear Fit y=0.765x Voltage at First Failure

9 How Razor Breaks the Rules Traditional worst-case design techniques must observe margin rules for reliable operation Incorporating timing-error correction mechanisms allow margins to be erased V th 1.2v Noise margin Ambient margin Process margin 0.v Infrequent use of critical paths allow for even deeper cuts in V dd Back to the Rules P = acv 2 f + VI leak 1. Minimize switching activity 2. Design for lower load capacitance 3. Reduce frequency 4. Reduce leakage and the most important of all: 5. Decrease supply voltage! V th Critical voltage (determined by critical path) 1.2v Noise margin Ambient margin Process margin 0.v 9

10 Subthreshold Circuits Break The Rules Superthreshold Subthreshold 1.2V IN P OUT 1.2V 0.2V IN P OUT 0.2V 0V N 0V 0V N 0V Static logic still works below V th Differences in I leak continue to (dis)charge outputs But diminished I on /I off results in big delays Approach works if the apps are not too demanding Sensing Applications Security Biomedical Environmental Industrial 10

11 Sensor Processing Data Rates Sensor Processor Sensing Communication Computation Storage Power Supply 11

12 Sensing Performance Demands are Low xrt: # times faster than real-time Platform ARM 720T ARM 7TDMI ARM 920T ARM 1020T Voltage (V) Speed (Hz) 100M 133M 250M 325M Fast Growing Leakage Complicates Design E inst = E cycle CPI Cycles per Instruction Energy per Instruction Energy per Cycle 2 E cycle = N(½αC s V dd + V dd I leak t clk Activity factor - average number of transistor switches per transistor per cycle Total circuit capacitance Supply Voltage Leakage current Clock period 12

13 Fast Growing Leakage Complicates Design 2 E cycle = N(½αC s V dd + V dd I leak t clk Activity factor - average number of transistor switches per transistor per cycle Total circuit capacitance Supply Voltage Leakage current Clock period Impact of voltage reduction I leak t clk E leak E dyn E cycle Superthreshold linear linear ~const. quad. quad. Subthreshold linear exp. ~exp. quad.??? Tension Fast Growing Leakage Complicates Design Impact of voltage reduction I leak t clk E leak E dyn E cycle Superthreshold linear linear ~const. quad. quad. Subthreshold linear exp. ~exp. quad.??? Tension 13

14 Lessons from Architectural Studies To minimize energy at subthreshold voltages, architects must: Minimize area Maximize Transistor utility Minimize CPI To reduce leakage energy per cycle To reduce V min and energy per cycle To reduce Energy per instruction Winning designs tend to be compromising designs that balance area, transistor utility and CPI Memory comprises the single largest factor of leakage energy, therefore, efficient designs must reduce memory storage requirements Subliminal Architectural Overview IF/ID Stage EX/MEM Stage WB Stage Imem 4x16x2x12 24 Prefetch Buffer 2x2x12 12 Register File 32-bit Timer OpA OpB ALU Carry Zero Register Write Flag μoperation Decoder External Interrupts Scheduler Page Dmem 12x Fetch Jump 14

15 First Subliminal Chip Large solar cell Solar cell for processor Custom memories Solar cell for discrete cells Discrete cells Mux-based memories Test memory level converter array Test module Level converter array Solar cell for adders Discrete adders Subliminal processors Pareto Analysis of Sensor Network Processors Energy/Inst (pj) Hempstead (Harvard) 0.5pJ/Inst@0.0 4MIPS CleverDust (Berkeley) 2.25 pj/inst@1mips MIPS SNAP/LE (Cornell) Subliminal (Michigan) 15

16 How Subliminal Breaks the Rules Traditional circuit design relies an transistor switching to perform computation Static logic circuits continue to operate below V th by modulating leakage currents Approach lends itself to low-demand sensor apps, as long as care is taken to build an efficient processor What I Really Learned A rule-breaking approach to technical research is effective and engaging You will find yourself on very fertile ground It is that which everyone knows is certainly true, that is indeed false. The early bird gets the worm. If you are not failing some of the time, you are not trying hard enough. You will more fully engage your colleagues One half will think crazy idea will never work One half will be intrigued (with your crazy idea) 16

17 Questions???????????? 17