NATIONAL RADIO ASTRONOMY OBSERVATORY
|
|
- Claud Harrington
- 5 years ago
- Views:
Transcription
1 NATIONAL RADIO ASTRONOMY OBSERVATORY GREEN BANK ) WEST VIRGINIA ELECTRONICS DIVISION INTERNAL REPORT No. 17 DDP-116/MODCOMP DATA LINK AT THE -FT TELESCOPE GEORGE H. PATTON APRIL 17 NUMBER OF COPIES:
2 DDP-116/MODCOMP DATA LINK AT THE -FT TELESCOPE George H. Patton TABLE OF CONTENTS Page I. Introduction. OOOOOOO OOOOO 1 II. Description... OOOOOOOOOOO OOOOOOOOOOO OOOOOOOOOOOO 1 A. Modcomp Computer and Peripheral Equipment.. 1 B. Data Link III. Programming OOOOO OOOOO OOOOOOOOOOOOOOOO 2 A. Link Address. o O. OOOOOOO 2 B. Link Status. o OOOOO 2 C. Link Commands.. OOOOO 3 D. Interrupts.. OOOOO. OOOOO 7 IV. Circuit Description... OOOOO O. OOOOO 00 OOOOO OOOOO 0000 OOOOO 0 8 V. Acknowledgements.... OOOOO OOOOOOOOO 0 0 VI. Mnemonic List.. OOOOOOOOOOOOO OOOOOOO 0 OOOOO LIST OF FIGURES No. 1 Modcomp-116 Link - Sheet 1 of 3 O 1 2 Modcomp-116 Link - Sheet 2 of 3 OO O OO 1 3 Modcomp-116 Link - Sheet 3 of 3 O OO OOO OO OO O OO Modcomp Link Buffer - Card Modcomp Link Buffer - Card
3 DDP-116/MODCOMP DATA LINK AT THE -FT TELESCOPE George H. Patton I. Introduction A Modcomp 11/2 digital computer has been installed in the -ft telescope to permit the observer to perform some real time data reduction. The data, collected by the DDP-116 computer, can be transferred via a data link to the Modcomp and stored for processing by the observer. This report gives a description of the data link between the two computers. II. Description A. Modcomp Computer and Peripheral Equipment. The Modcomp 11/2 purchased for the -ft telescope is a general purpose 16-bit computer with 32 K words of core memory. Two general purpose controller modules were also purchased to facilitate interfacing the Modcomp computer to special NRAO devices. One of these controllers is used in the data link. The peripheral equipment consists of a punched card reader (Documation M200), a moving head disc with 2,8,00 words of storage (Diablo), a computer display terminal (Tektronix 0), and a hard copy unit (Tektronix 6). This equipment is located adjacent to the CPU unit in the control room. B. Data Link The data link is designed to transfer data between the two computers in block form (DMC mode for the DDP and DMP mode for the Modcomp) and can operate in either direction. At the present time, the link is active only in the direction for data transfer from the DDP-116 to the Modcomp, but can be activated in the other direction when required and the software becomes available. Once initialized, the transfer occurs at a rate of approximately one word every 7 psec times the number of words being transferred.
4 2 III. Programming A. Link Address The link address is different for the DDP-116 and the Modcomp since it was chosen not to coincide with any planned additions to either computer. The link address and associated information for each computer is as follows: commands: B. Link Status DDP-116 Link Arrangements: Link Address: 0 DMC Channel: 0* PIL Line: 1 * The start and stop addresses for DMC channel 0 are 20 and 21 respectively. Modcomp Link Arrangements: Link Address: 1C DMP Channel: 0* * The TA (transfer address) and TC (transfer count) locations are 7 and 6 respectively. The link status may be checked by the DDP-116 with the following SKS 20: The DRL (device ready line) will be low if the DDP-116 has reached an end of range. SKS 30: The DRL will be low if the Modcomp is ready to receiver or transmit data. SKS 0: The DRL will be low if the link is set to transfer data from the Modcomp to the DDP-116. The computers need not be ready to transfer data as this SKS just indicates the present condition of the direction flip-flop.
5 3 The Modcomp can check the link status by performing an input status command for device 1C. The status word has the following configuration: Bit 0 1 = Link controller power on. Bit 1 0 Bit 2 0 Bit 3 0 Bit 1 = Memory Parity Error. Bit 0 Bit 6 0!iI_Z Lf_nSL21 1 2_1 _11_11P.P.sfer Data. Bit 8 0 Bit 0 Bit A 0 Bit B 0 Bit C 1 = DDP-116 Ready to Transfer Data. Bit D 1 = EOBLK (End of Block) Flip Flop Set. Bit E 1 = ERL (End of Range) Flip Flop Set. Bit F 1 = Direction Flip Flop Set for Transfer from Modcomp. C. Link Commands The link commands for the DDP-116 are listed below: OCP 00: This command is used by the DDP-116 to initiate data transfer from it to the Modcomp. When the command is issued, the following flip-flops are set: Ready. 2. Direction (indicates transfer from Modcomp). 3. DIL Providing DMC channel 0 has previously been set up in the DDP-116, this command will load the first word to be transferred into the link buffer register and wait for the Modcomp to acknowledge the transfer request. The Modcomp would recognize the transfer request by monitoring the link status word bits C (DDP-116 Ready) and F (Direction).
6 OCP : This command is used by the DDP-116 to acknowledge a data transfer request initiated by the Modcomp for transfer from the Modcomp. This request would be via an interrupt on PIL 1 in the DDP-116. When interrupted, the DDP-116 needs to perform a series of SKS's to determine the reason for the interrupt. When this command is executed, the following flipflops are set: Ready. 2. DMP Request. When the Modcomp receives the DMP request, it will load the first word to be transferred into the link register and generate a PIL to the DDP-116. If DMC channel 0 has been set up, the transfer will take place. OCP 20: This command is used by the DDP-116 to initiate data transfer from the Modcomp to it. When the command is executed, the following flip-flops are set: Ready. 2. DMP Request. Also, the Direction flip-flop is reset so as to indicate a data transfer from the Modcomp. With the DMP Request flip-flop set, the link waits for the Modcomp to acknowledge the request which it detects by monitoring the link status and observing the DDP- 116 going ready. When the Modcomp acknowledges the
7 OCP 20 continued): request, and the Mod Ready flip-flop is set, the DMP Request will be sent on to the CPU and the first word will be loaded into the link register. The transfer will then occur providing DMC channel 0 is set up in the DDP-116. OCP 30: This command is used by the DDP-116 to acknowledge a data transfer request initiated by the Modcomp for transfer to the Modcomp. The transfer request would be via an interrupt on PIL 1 and the DDP-116 would need to perform the necessary SKS's to detect the reason for the interrupt. This command sets the following flip-flops: Ready. 2. DIL. Setting the DIL flip-flop will cause the DDP-116 to load the first data word to be transferred into the link register, thus starting the block transfer. Any of the OCP's listed above will also reset the ERL (End of Range) and EOBLK (End of Block) flip-flops. The Modcomp controls the link via the command OCB to device 1C. This instruction outputs a command word which permits control of the link by changing the word's bit pattern. The configuration of the command word is as follows:
8 Bit 0 1 = Transfer Initiate (0 = Control) Bit 1 1 Bit 2 1 = Data Interrupt Connect Bit 3 1 = Service Interru t Connect Bit 1 = End of Block Bit 1 = Terminate Bit 6 1 = Direction into Modcomp Bit 7 1 = DDP-116 Interru t Bit 8 1 = Modcomp Ready Bit 0 Bit A 0 Bit B 0 Bit C 0 Bit D 0 Bit E 0 Bit F 0 The following gives a brief explanation of the bits in the control word. BIT 2 and BIT 3: These two bits connect (or enable) the data and service interrupts respectively in the general purpose control of the Modcomp. BIT : This bit can be used to signify an end of block of data. It is not needed for the link as an end of block is already generated in the DM F mode. BIT : This bit can be used to terminate a transfer any time. A terminate command will also cause a Service Interrupt if this interrupt is enabled. BIT 6: This bit controls the direction flip-flop in the link along with commands from the DDP-116. BIT 7: This bit when set will interrupt the DDP-116 on PIL 1 (normally used when the Modcomp wants to initiate a transfer). BIT 8: This bit controls the Modcomp Ready flip-flop and is used to enable the link on the Modcomp end. The appropriate selection of bits can then handle all combinations of transfer requests either when the Modcomp initiates the request or acknowledges one from the DDP-11.6.
9 7 D. Interrupts The DDP-116 can be interrupted on PIL 1 by two methods (PIL 1 entrance location = 6 ): 8 1. An interrupt will be generated on PIL 1 when an end of range (ERL) is generated by the DDP-116 along with an input or output data command (INDCM or OUDCM) from the Modcomp, depending on the direction of transfer. 2. An interrupt can also be generated on PIL 1 by the Modcomp when it does an OCB to the link with bit 7 set. The Modcomp has two interrupts connected to the link. These are the data interrupt (DI) and the service interrupt OW for device address 1C (DI entrance location = C 16' SI entrance location = DC ). If these interrupts 16 are enabled, the following will generate an interrupt to the Modcomp. DATA INTERRUPT: A DI will be generated when the Modcomp reaches an end of block (EOBLK) in a DMP transfer. SERVICE INTERRUPT: A SI will be generated when one of three conditions are met. 1. When a terminate command is executed by the Modcomp. 2. When the Modcomp either reaches an end of block or outputs an end of block command. 3. When a complete (CMPT) is generated in the link. This is generated when either computer has transferred its entire block of data. Additional information on the programming for the computers can be found in their respective Programmers' Reference Manuals.
10 IV. Circuit Description The electronics for the link is located in two locations, with the main portion located with the General Purpose Controller in the Modcomp. The remainder, which consists of two buffer cards, is located in the expansion rack in the DDP-116. Figures 1, 2 and 3 show the circuit built on the board with the General Purpose Controller. This controller is designed with room for customer additions to interface with special systems. The circuits shown are just the addition to the controller. Along with the customer interface, there were four wiring connections to be completed in the controller. They were as follows: 1. Link address 1C. 2. Interrupt priority code. 3. Source ID for interrupt.. DMP channel address. The location for these connections and diagrams for the General Purpose Controller can be found in the Technical Manual, Peripheral Controllers, Volume II for the Modcomp computer. Figure 1 shows the logic for decoding commands from the DDP-l16, logic for SKS instructions, logic for generating CLEAR signals, and inverters for the bits from the output bus in the DDP-116. Output commands 00,, 20, 360, and 0 are decoded and gated with the OCP pulse. OCP 0 is not used at the present time but is available for future expansion. An output command pulse OCP 0 is also generated anytime an OCP is executed in the link. This pulse is used to reset the ERL and EOBLK flip-flops. The pulse OCP 0A is OCP 0 delayed by a few psec and is used to set the 116 READY flip-flop.
11 Three types of clear signals are generated: CLEAR A, CLEAR B, and CLEAR. CLEAR A is generated from MSTCL (Master Clear from the DDP-116) or ICBFB (Master Clear from the Modcomp), CLEAR B is generated from a CLEAR A signal or a TERM (Terminate) from the Modcomp, and CLEAR is generated from a CLEAR B signal or a HALT from the link. The three clear signals reset flip-flops as follows: CLEAR A: Resets - SI REQUEST F/F CLEAR B: Resets - PIL F/F 116 READY F/F DIL F/F ERL F/F EOBLK FiF OUT/IN F/F DMP REQUEST F/F Also clears - BUFFER 1 BUFFER 2 CLEAR: Resets - MOD READY F/F Figure 2 shows the buffer register in the link used in data transfer between the two computers. BUFFER 1 is used in transfer from the DDP-116 to the Modcomp. The output word from the DDP-116 is latched into this buffer by an OTP pulse gated with a DAL pulse. These two pulses gated together also generate a DATA READY pulse which sets the DMP REQUEST flip-flop notifying the Modcomp that a word is in the buffer. BUFFER 2 is used for transfer in the other direction ( q odcomp to DDP-116). The output word from the Modcomp is latched into the register by an OUDCM pulse which also sets the DIL flip-flop notifying the DDP-116 that the buffer contains data. The data contained in BUFFER 2 is then gated on to the DDP-116 input bus by a DAL pulse for transfer in this direction.
12 -- Figure 3 contains the remaining of the custom logic for the link which is located with the General Purpose Controller. This figure contains most of the receivers for command pulses from the DDP-116 along with the link control logic. The flip-flops used for control are explained in the following: MOD READY F/F: This flip-flop is set when the Modcomp performs an OCB with bit 8 set. It signifies that the Modcomp is ready to transfer data. It also gates the output of the DMP REQUEST F/F to the Modcomp and gates the RRL signal to the input of the DMP REQUEST F/F. SI REQUEST F/F: This flip-flop, when set, generates a service interrupt to the Modcomp. It can be set by an end block (EOBLK) or terminate command from the Modcomp, and by a complete of transfer (CMPT) from the link. It is reset by reset service interrupt (SIRSTN), CLEAR A, or load command register (UDGMR) pulse. DMP REQUEST F/F: This flip-flop is set when the link wants to transfer a word either to or from the Modcomp via a DMP channel. It can be set by an RRL pulse gated with the MOD READY signal, DATA READY signal, OCP 20, or OCP, depending on direction of transfer and whether initiating transfer or transfer in progress. The flip-flop is reset by a data command (DCM), end of block (EOBLK), data command delayed (DMCA) gated with end of range (ERLA) or CLEAR B. The DCM signal resets the flip-flop after every word transfer, while the rest of the reset signals are either associated with an end of block of data, a terminate command, of a master clear from either computer. PIL F/F: This flip-flop, when set, will interrupt the DDP-116 on priority interrupt line 1. It can be set by an OCB from the Modcomp with bit 7 = 1 or with a CMPT B. (CMPT B is an end of
13 PIL F/F (continued): range gated with data command pulse from the Modcomp.) It is reset by an acknowledge (ACK) signal from the DDP-116 or a CLEAR B signal. 116 READY F/F: This flip-flop, when set, signifies that the DDP-116 is ready to transfer data. It is set by an OCP 0. (0CP 0 is generated anytime the DDP-116 executes an OCP on the link.) It is used to gate signals to the DIL FiF for data transfers. They are (1) an end of range (ERL) from the DDP-116, (2) an end of block (EOBLK) from the Modcomp gated with the OUT/IN direction signal, (3) an end of block gated with a DAL, and () a CLEAR B. The second and third methods of reseting the flip-flop deal with an end of block from the Modcomp and are gated with the appropriate signal to make sure the last word to or from the Modcomp is removed from the link's buffer register before the flip-flop is reset. DIL F/F: The DIL flip-flop is set every time the link wants to transfer a word in or out of the DDP-116 via DMC channel 0. This is done by an OCP 0, output data command gated with the OUT/IN FF for transfer from the Modcomp, or input data command gated with the OUT/IN FiF for transfer in the other direction. There is a delay of approximately 7 psec in the clock pulse to the DIL F/F to slow down the rate of transfer in order to avoid any conflict with the DDP-116's normal functions. The DIL flip-flop is reset by all the signals which reset the 116 READY F/F plus it is reset by a DAL pulse each time a word is transferred in or out of the DDP-116.
14 - - ERL F/F: This flip flop is set when the DDP-116 reaches an end of range in a DMC data transfer. It is reset by a load command register (LDCMR) pulse from the Modcomp, by an OCP 0 from the DDP-116, or by a CLEAR B. EOBLK F/F: This flip-flop is set when the Modcomp reaches an end of block in a DMP data transfer. It is reset by the same signals as the ERL F/F. A one shot multivibrator, location U11, is used to generate a delayed data command pulse from the Modcomp. This delayed pulse, gated with end of range (ERL) from the DDP-116 generates a pulse called complete B (GMPT B). CMPT B indicates that an end of range has been reached and the last word removed from the link buffer for data transfer to the Modcomp. Likewise, an end of block from the Modcomp (EMILK) gated with a DAL from the DDP signifies that the entire data block has been transferred from the Modcomp and the DDP-116 has removed the last word from the link buffer register. The rest of Figure 3 contains gating for the various control signals. Figures and are the buffer cards for the DDP-116. These cards contain the necessary line drives and gates to drive the 60 feet of cable between the DDP-116 and the Modcomp and are located in the DDP-116 expansion rack. V. Acknowledgements Credit should be given to R. Weimer, D. Schiebel and W. Vrable for their help in the design and construction of the data link.
15 -- VI: Mnemonic List Mnemonic Description ACK Acknowledge signal from DDP-116 used to reset PIL F/F. ADBxx Address bits from DDP-116. CLEAR Generated by Master Clear, ICBFB, TERM, or HALT. CLEAR A Generated b Master Clear, or ICBFB. CLEAR B Generated by Master Clear, ICBFB, or TERM. CMPT Generated by CMPT A or CMPT B. CMPT A Complete A, generated by EOBLKA gated with DAL. CMPT B Complete B, ;:,enerated by ERLA sated with DCMA. DAL Signal from DDP-116 when a DMC work transfer occurs. DATA READY Signal which signifies data is in the link buffer for the Modcomp. DATARS Signal used for DMP word transfer request in Modcomp. DCMA Pulse to gate data to 'orfrom the Modcomp. DFB Output data from buffer - Modcomp. DIL Request for data transfer in DMC DDP-116. DTLM Input data to computer - Modcomp. EOBLK...Signal enerated at end of DMP block transfer - Modcomp. EOBLKA ERL ERLA HALT ICBFB Signal from F/F in link set by EOBLK. Signal generated at end of DMC block transfer Signal from F/F in link set by ERL. Sipal generated by EOBLKA or ERLA. DDP-116. INB INDCM ISLM xx LDCMR LDCMRA LDCMRB MOD READY OCP OCP xxx OCP 0 OCP 0A OTB xx OTB A xx OTP OUDCM OUT/IN PIL 1 RRL SIRSTN SKS xxx STSIRQ TERM Master clear - Modcomp. Input bits to DDP-116. Input data command - Modcomp. In ut status bit - Modcom Load command register pulse - Modcamp. DFB06 gated with LDCMR. DFB06 gated with LDCMR. Signal which signifies the Modcomp is ready to transfer data. Output control pulse from DDP-116. Output command gated with OCP. Pulse generated any time an OCP to the link is executed. Dela y ed OCP 0. Output bit from DDP-116. Inverted OTB xx. Output pulse for gating output bits from DDP-116. Output data command - Modcomp. Signal from F/F in link which determines direction of transfer. Priority interrupt line 1 - DDP-116. Pulse used to reset ready condition in the link. Signal to reset Service Interrupt F/F Modcomp. Sensing commands from DDP-116. Set Service Interrupt request to Modcomp. Terminate command from Modcomp.
16 C1-2._3 MSTCL >""- CI-26 "I"D U2J ICBFB > HALT > V2BO2 CLEAR A CLEAR B CLEAR B 732, CLEAR CLEAR ERLA 20 OUT/IN 0 SKS 20 ( LOW FOR ERL ) S KS 0 ( LOW FOR OUT OF MODCOMP ) CI OTB C3 - ADB 16 C3-8 ADB1 > 30 SKS 30 ( LOW FOR MOD READY) MOD READY DRL+ " I C3-7 ADB 1 > OCP C3- ADB C3-6 ADB C3- ADB II > II UJ 02 UJ06 2 UJI3 J1 _11 UJ0 Vc c Wv-- II C3-3 ADB I 0 OCP 30 UJ K pf C 3-2 ADB 0 C3-1 ADB 08 >1" j" IK LOW FOR POWER ON 2 p 702 OCP 00 OCP OCP 20 OCP 0 UIP 2r vcc"rb "I"E "1"Fill"G 1 II 8 "En "I"A "I"B "I"C CPIDA IK UM 70 C 2-23 MODCOMP 116 LINK Sheet I of 3 00 pf U L 70 FIG. I OTBA
17 BUFFER 1 BUFFER 2 OTBA > 0 2 > > > > > > I I 0 > I I >-- 7 I 7 B VIP 717 VIN A C 717 B VIM A 1 DTLM > 00 > > > > 0 INB C2 01 I < < qvj 3 < 03 0 if < c(tj 703 OPEN COLLECTOR DFB V J 2 8 VJ 0 3 <. V J < 60( V J 07 7< V J 0 8 II 8 < V J 0 3 < </ 3J I < V 3 J I < 8.0E/3J 11 < V3 J < 1 6 1< V 2J 30E2J < 0( i2j111l V IL A IT c V IK B II 1 ---> 1 --> < V 2J VIJ A 2 A 0 I I I < < 0 3 < < 1 2 I I 6, 3 1 V 3M 0 UDCM CLEAR B 8 CLEAR B 70 V 2P OTP 2 V 2P DATA OUT/IN READY V2P DAL DAL MODCOMP 116 LINK Sheet 2of 3 FIG
18 708 LDCMR 8 DFB07> V3 ;) (V308) CMPT B "I"A OUT/1N "I" C 1 MOD READY ISLM07 (V30) PIL F/F 77 C VK 0 MOD READY _ F/F U2N C _r V3M 6 PILlS 70 3 LDCMR 6 OUDCM INDCM 70 ACK _FL CLEAR "I"A < SIRSTN -u- 1 V3M V3N V3K 708 "I C (UI F08) C3-2 ACK 3 0> II II uc A CLEAR B 732 C3-21 > V2M II EOBLK ISLMI2 STS I R0_ 0 (UIE01) I " C SI REQ CMPT ACK 1 1 (V2002) CMPT A U3N F/F OCP0A > 1.:1: UN 2 UIJ UIJ06 - C3-18 C3-I C2-2 C I UIJI3 11 UIJ READY F/F 732 DAL V3N EOBLKA 602 V K UIH OCP 00 LDCMR 732 CLEAR A 702 CLEAR B I II 732 "I" C C 702 DFB08 (V3B) TERM (U3L 0) V3N MOD 708 OUT/IN DATARS 2 6 " 1 "C UIL V3N (11 L (UC 03) UIL OUDCM EOBLKA DMP REQ MOD F/F "I A READY -L A DCM 6 Q U2M C UIM PIL 1 EOBLK 702 DIL F/F 708 PIL 1 77 _ DCMA 6 70 UIL 8 "l Ao 2 ERLA 732 "I c 732 CMPT B 6 ERL 1 CLEAR B 732 "I"C 732 DAL OUT/ IN F/F D READY RRL OCP II 20 DATA READY OCP "I"E 0 C P OUT/IN < Vcc _ 77 OCP C P DC-1 (V2 D) ISLMI < U2M C3-1> U1J LDC MR B (UB0) DRID pF C3-1> V2L V L OTP 7K CM PT A.01 pf CLEAR B CMPT CMPTB OCP 20 LDCMRA II II ERL Vcc C3-16 > J1_ 1 1, C3-17> - V2 L V 2 V31) 3 > - ERL LDCMR< 70 -If DC-2 rit-1,3 2 U J LDCMRN U3N U3N "I" E 7K UJ02 11 III 1 --LIL0 270 pf U J _FL 1 C3-22 < I U H 6 3K DCMA II C3-23 < V2 N II i ll LDCMRA < LDCMRB < 6 (M OIL 0 (V2DI0 ) ISLMI 77 ERL -o "I" B o TERM U, DAL 0 70 F/F (V6 B)> UJ0 C3-2> U2L c 6 3 ERL OUDCM 732 U3N V2K V3L V3L > DAL HALT C3-2> 11,111, DCM L DA L0 ISLMI3 (V200)< _11_ EOBLKA < Q77 D "I" B "I"B > DAL OCP0 EOBLK 70 > C C2-22> V2K - -1_11R.L 70 V3L 708 V2P) j1; RRLLDCMR B I : CLEAR 702 _ F/F "1- U2L FIG. 3 MODCOMP 116 LINK Sheet 3 of 3 1 EOBLK U3N -< EOBLKN (V6 D 08) IN DCM < --t_r 3 -< LDCMRN (U2DII) <DFB06 (V3806) OUDCMN ( V6E06) U3N -< INDCMN 70 (V6 F06) 1
19 ADB 7 II > 6> RI RI 7 > R R2 -- R ADB+ 3 7 > 0 1 > ADB > R I 11 > 11 R 1 3 > 2 R > R )3 ADB+ > 6 1 > 7 1 >8 16 OTB+ 737 OTB- OTB > > 2 I R6 18 > )3 2 R6 3 1 > 8 R7 io -2-0-)o > 3 II > 11 R7 > 21> >6 R8 6 22> 1 )06 1 >7 6 R > > R -"" 2> 11 1 > 8 R OTB 2 > 2 T IT Y > 60 RIO 26> RIO 27> R11 28> R11 (2 27> R 30> R 31> RI3 II 16 32> RI3-7> > 62 II >63 >6 >6 1 >66 1 >67 16 FRONT OF BOARD PIN I - RI 08 + R2 RI3 R3 RI2 R 21 Rh R RIO 16 1 II R6 6 R R7 7 R DCC R88-1-1K BACK 70 FRONT 3 DECOUPLE CHIPS 17,18,1,20,22,23,2 WITH. 2 2/, F > H + DIL0 i3 1 16, RI 737 DIL 0+ 2 )0 3 > MODCOMP LINK BUFFER CARD I FIG.
20 18 - INB-A INB- R > RIO > )1 RI NB- 1 2 R2 2 3>-i II DRLI- 0 1 DRL- MSTCL- 6 RI DRL2-1 RRL- 6> PIN I 0 8 R23 R3 3 >1 R >1 R 6>1 R6 6 7> R7 7 8> R8 8 ) R2 1 3 RhI >1 3 II 62> 1 RI2 >20 63> 1 RI3 >21 6>1 RI > ) 1 RI > > 1 > > 1 RRL A >8 RRL-A >1 RRL B > RRL+ B OCP 1> RIB 8830 R20 OTP- 0> RI 8830 R2I R16 R INB-A II I 0 >2 II >26 >27 II >28 >2 >30 1 >31 1 >32 16 >6 MSTCL+A )11 MSTCL-A 7 MSTCL+B MSTCL-B > OCP+A > OCP-A > OCP+B > OCP-8 >2 OTP +A > OTP -A >3 OTP+B >8 OTP-B 16 R8 -I-1K R8 _ 1 1 K RI R2 R3 R R R6- R7 R8- -(K R RI2 _ RI I RIO R R RI RI RI6 RI7 R18 RI R20 7 R8- (-(K R2 R23 R22 8 R BACK 70 FRONT 3 DECOUPLE CHIPS 17,18,1,21, 22,23,2 116 MODCOMP LINK BUFFER CARD 2 FIG.
NATIONAL RADIO ASTRONOMY OBSERVATORY DDP-116/M0DC0MP DATA LINK AT THE MO-FT TELESCOPE
NATIONAL RADIO ASTRONOMY OBSERVATORY GREEN BANK, WEST VIRGINIA ELECTRONICS DIVISION INTERNAL REPORT NO. 157 DDP-116/M0DC0MP DATA LINK AT THE MO-FT TELESCOPE GEORGE H. PATTON APRIL 1975 NUMBER OF COPIES:
More informationBUSES IN COMPUTER ARCHITECTURE
BUSES IN COMPUTER ARCHITECTURE The processor, main memory, and I/O devices can be interconnected by means of a common bus whose primary function is to provide a communication path for the transfer of data.
More informationExperiment 8 Introduction to Latches and Flip-Flops and registers
Experiment 8 Introduction to Latches and Flip-Flops and registers Introduction: The logic circuits that have been used until now were combinational logic circuits since the output of the device depends
More informationLogic Devices for Interfacing, The 8085 MPU Lecture 4
Logic Devices for Interfacing, The 8085 MPU Lecture 4 1 Logic Devices for Interfacing Tri-State devices Buffer Bidirectional Buffer Decoder Encoder D Flip Flop :Latch and Clocked 2 Tri-state Logic Outputs
More informationINC 253 Digital and electronics laboratory I
INC 253 Digital and electronics laboratory I Laboratory 9 Sequential Circuit Author: ID Co-Authors: 1. ID 2. ID 3. ID Experiment Date: Report received Date: Comments For Instructor Full Marks Pre lab 10
More informationChapter 2. Digital Circuits
Chapter 2. Digital Circuits Logic gates Flip-flops FF registers IC registers Data bus Encoders/Decoders Multiplexers Troubleshooting digital circuits Most contents of this chapter were covered in 88-217
More information82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE
Y Y Y Y Y 82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE Compatible with all Intel and Most Other Microprocessors High Speed Zero Wait State Operation with 8 MHz 8086 88 and 80186 188 24 Programmable I
More informationLAB #4 SEQUENTIAL LOGIC CIRCUIT
LAB #4 SEQUENTIAL LOGIC CIRCUIT OBJECTIVES 1. To learn how basic sequential logic circuit works 2. To test and investigate the operation of various latch and flip flop circuits INTRODUCTIONS Sequential
More informationS6B CH SEGMENT DRIVER FOR DOT MATRIX LCD
64 CH SEGMENT DRIVER FOR DOT MATRIX LCD June. 2000. Ver. 0.0 Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by
More informationDIGITAL ELECTRONICS MCQs
DIGITAL ELECTRONICS MCQs 1. A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register. A. 1 B. 2 C. 4 D. 8
More informationIntroduction. Serial In - Serial Out Shift Registers (SISO)
Introduction Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They are a group of flip-flops connected in a chain so that the output from one flip-flop becomes
More informationVTU NOTES QUESTION PAPERS NEWS RESULTS FORUMS Registers
Registers Registers are a very important digital building block. A data register is used to store binary information appearing at the output of an encoding matrix.shift registers are a type of sequential
More informationFLIP-FLOPS AND RELATED DEVICES
C H A P T E R 5 FLIP-FLOPS AND RELATED DEVICES OUTLINE 5- NAND Gate Latch 5-2 NOR Gate Latch 5-3 Troubleshooting Case Study 5-4 Digital Pulses 5-5 Clock Signals and Clocked Flip-Flops 5-6 Clocked S-R Flip-Flop
More information64CH SEGMENT DRIVER FOR DOT MATRIX LCD
64CH SEGMENT DRIVER FOR DOT MATRIX LCD INTRODUCTION The (TQFP type: S6B2108) is a LCD driver LSI with 64 channel output for dot matrix liquid crystal graphic display systems. This device consists of the
More informationSEQUENTIAL LOGIC. Satish Chandra Assistant Professor Department of Physics P P N College, Kanpur
SEQUENTIAL LOGIC Satish Chandra Assistant Professor Department of Physics P P N College, Kanpur www.satish0402.weebly.com OSCILLATORS Oscillators is an amplifier which derives its input from output. Oscillators
More informationChapter 18. DRAM Circuitry Discussion. Block Diagram Description. DRAM Circuitry 113
DRAM Circuitry 113 Chapter 18 DRAM Circuitry 18-1. Discussion In this chapter we describe and build the actual DRAM circuits in our SK68K computer. Since we have already discussed the general principles
More informationCHAPTER 1 LATCHES & FLIP-FLOPS
CHAPTER 1 LATCHES & FLIP-FLOPS 1 Outcome After learning this chapter, student should be able to; Recognize the difference between latches and flipflops Analyze the operation of the flip flop Draw the output
More informationHandout 16. by Dr Sheikh Sharif Iqbal. Memory Interface Circuits 80x86 processors
Handout 16 Ref: Online course on EE-390, KFUPM by Dr Sheikh Sharif Iqbal Memory Interface Circuits 80x86 processors Objective: - To learn how memory interface blocks, such as Bus-controller, Address bus
More informationNote 5. Digital Electronic Devices
Note 5 Digital Electronic Devices Department of Mechanical Engineering, University Of Saskatchewan, 57 Campus Drive, Saskatoon, SK S7N 5A9, Canada 1 1. Binary and Hexadecimal Numbers Digital systems perform
More informationChapter 6. Flip-Flops and Simple Flip-Flop Applications
Chapter 6 Flip-Flops and Simple Flip-Flop Applications Basic bistable element It is a circuit having two stable conditions (states). It can be used to store binary symbols. J. C. Huang, 2004 Digital Logic
More informationLogic Design II (17.342) Spring Lecture Outline
Logic Design II (17.342) Spring 2012 Lecture Outline Class # 03 February 09, 2012 Dohn Bowden 1 Today s Lecture Registers and Counters Chapter 12 2 Course Admin 3 Administrative Admin for tonight Syllabus
More informationAsynchronous (Ripple) Counters
Circuits for counting events are frequently used in computers and other digital systems. Since a counter circuit must remember its past states, it has to possess memory. The chapter about flip-flops introduced
More informationChapter 4. Logic Design
Chapter 4 Logic Design 4.1 Introduction. In previous Chapter we studied gates and combinational circuits, which made by gates (AND, OR, NOT etc.). That can be represented by circuit diagram, truth table
More informationDigital Systems Laboratory 3 Counters & Registers Time 4 hours
Digital Systems Laboratory 3 Counters & Registers Time 4 hours Aim: To investigate the counters and registers constructed from flip-flops. Introduction: In the previous module, you have learnt D, S-R,
More informationDigital Circuits 4: Sequential Circuits
Digital Circuits 4: Sequential Circuits Created by Dave Astels Last updated on 2018-04-20 07:42:42 PM UTC Guide Contents Guide Contents Overview Sequential Circuits Onward Flip-Flops R-S Flip Flop Level
More informationCombinational vs Sequential
Combinational vs Sequential inputs X Combinational Circuits outputs Z A combinational circuit: At any time, outputs depends only on inputs Changing inputs changes outputs No regard for previous inputs
More informationEngineering College. Electrical Engineering Department. Digital Electronics Lab
Engineering College Electrical Engineering Department Digital Electronics Lab Prepared by: Dr. Samer Mayaleh Eng. Nuha Odeh 2009/2010-1 - CONTENTS Experiment Name Page 1- Measurement of Basic Logic Gates
More informationPhysics 120 Lab 10 (2018): Flip-flops and Registers
Physics 120 Lab 10 (2018): Flip-flops and Registers 10.1 The basic flip-flop: NAND latch This circuit, the most fundamental of flip-flop or memory circuits, can be built with either NANDs or NORs. We will
More informationTechnical Note
ESD-TR-f. 6-453 ESD RECORD COPY 1211 N DIVISION ESD ACCESSION LIST Call No. AL 531^8 Technical Note 1966-24 S. B. Russell Haystack Display Translator 10 October 1966 s Division Contract AF 19(628)-5]
More informationECB DIGITAL ELECTRONICS PROJECT BASED LEARNING PROJECT REPORT ON 7 SEGMENT DIGITAL STOP WATCH USING DECODER
ECB2212 - DIGITAL ELECTRONICS PROJECT BASED LEARNING PROJECT REPORT ON 7 SEGMENT DIGITAL STOP WATCH USING DECODER SUBMITTED BY ASHRAF HUSSAIN (160051601105) S SAMIULLAH (160051601059) CONTENTS >AIM >INTRODUCTION
More informationTopic D-type Flip-flops. Draw a timing diagram to illustrate the significance of edge
Topic 1.3.2 -type Flip-flops. Learning Objectives: At the end of this topic you will be able to; raw a timing diagram to illustrate the significance of edge triggering; raw a timing diagram to illustrate
More informationChapter Contents. Appendix A: Digital Logic. Some Definitions
A- Appendix A - Digital Logic A-2 Appendix A - Digital Logic Chapter Contents Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic A. Introduction A.2 Combinational
More informationFlip-Flops and Related Devices. Wen-Hung Liao, Ph.D. 4/11/2001
Flip-Flops and Related Devices Wen-Hung Liao, Ph.D. 4/11/2001 Objectives Recognize the various IEEE/ANSI flip-flop symbols. Use state transition diagrams to describe counter operation. Use flip-flops in
More information0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1 1 Stop bits. 11-bit Serial Data format
Applications of Shift Registers The major application of a shift register is to convert between parallel and serial data. Shift registers are also used as keyboard encoders. The two applications of the
More informationANALOG I/O MODULES AD268 / DA264 / TC218 USER S MANUAL
UM-TS02 -E026 PROGRAMMABLE CONTROLLER PROSEC T2-series ANALOG I/O MODULES AD268 / DA264 / TC218 USER S MANUAL TOSHIBA CORPORATION Important Information Misuse of this equipment can result in property damage
More informationAnalogue Versus Digital [5 M]
Q.1 a. Analogue Versus Digital [5 M] There are two basic ways of representing the numerical values of the various physical quantities with which we constantly deal in our day-to-day lives. One of the ways,
More informationDALHOUSIE UNIVERSITY Department of Electrical & Computer Engineering Digital Circuits - ECED 220. Experiment 4 - Latches and Flip-Flops
DLHOUSIE UNIVERSITY Department of Electrical & Computer Engineering Digital Circuits - ECED 0 Experiment - Latches and Flip-Flops Objectives:. To implement an RS latch memory element. To implement a JK
More informationIntroduction. NAND Gate Latch. Digital Logic Design 1 FLIP-FLOP. Digital Logic Design 1
2007 Introduction BK TP.HCM FLIP-FLOP So far we have seen Combinational Logic The output(s) depends only on the current values of the input variables Here we will look at Sequential Logic circuits The
More informationChapter. Sequential Circuits
Chapter Sequential Circuits Circuits Combinational circuit The output depends only on the input Sequential circuit Has a state The output depends not only on the input but also on the state the circuit
More informationKW11-L line time clock manual
DEC-ll HKWB-D KW11-L line time clock manual DIGITAL EQUIPMENT CORPORATION MAYNARD, MASSACHUSETTS 1st Edition February 1971 2nd Printing (Rev) December 1971 3rd Printing July 1972 4th Printing October 1972
More informationPESIT Bangalore South Campus
SOLUTIONS TO INTERNAL ASSESSMENT TEST 3 Date : 8/11/2016 Max Marks: 40 Subject & Code : Analog and Digital Electronics (15CS32) Section: III A and B Name of faculty: Deepti.C Time : 11:30 am-1:00 pm Note:
More informationReview of Flip-Flop. Divya Aggarwal. Student, Department of Physics and Astro-Physics, University of Delhi, New Delhi. their state.
pp. 4-9 Krishi Sanskriti Publications http://www.krishisanskriti.org/jbaer.html Review of Flip-Flop Divya Aggarwal Student, Department of Physics and Astro-Physics, University of Delhi, New Delhi Abstract:
More informationSlide 1. Flip-Flops. Cross-NOR SR flip-flop S R Q Q. hold reset set not used. Cross-NAND SR flip-flop S R Q Q. not used reset set hold 1 Q.
Slide Flip-Flops Cross-NOR SR flip-flop Reset Set Cross-NAND SR flip-flop Reset Set S R reset set not used S R not used reset set 6.7 Digital ogic Slide 2 Clocked evel-triggered NAND SR Flip-Flop S R SR
More informationAIM: To study and verify the truth table of logic gates
EXPERIMENT: 1- LOGIC GATES AIM: To study and verify the truth table of logic gates LEARNING OBJECTIVE: Identify various Logic gates and their output. COMPONENTS REQUIRED: KL-31001 Digital Logic Lab( Main
More informationEKT 121/4 ELEKTRONIK DIGIT 1
EKT 121/4 ELEKTRONIK DIGIT 1 Kolej Universiti Kejuruteraan Utara Malaysia Bistable Storage Devices and Related Devices Introduction Latches and flip-flops are the basic single-bit memory elements used
More informationD Latch (Transparent Latch)
D Latch (Transparent Latch) -One way to eliminate the undesirable condition of the indeterminate state in the SR latch is to ensure that inputs S and R are never equal to 1 at the same time. This is done
More informationNan Ya NT5DS32M8AT-7K 256M DDR SDRAM
Nan Ya NT5DS32M8AT-7K 256M DDR SDRAM Circuit Analysis 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM
More informationMODULAR DIGITAL ELECTRONICS TRAINING SYSTEM
MODULAR DIGITAL ELECTRONICS TRAINING SYSTEM MDETS UCTECH's Modular Digital Electronics Training System is a modular course covering the fundamentals, concepts, theory and applications of digital electronics.
More informationMODULE 3. Combinational & Sequential logic
MODULE 3 Combinational & Sequential logic Combinational Logic Introduction Logic circuit may be classified into two categories. Combinational logic circuits 2. Sequential logic circuits A combinational
More informationPrinciples of Computer Architecture. Appendix A: Digital Logic
A-1 Appendix A - Digital Logic Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic A-2 Appendix A - Digital Logic Chapter Contents A.1 Introduction A.2 Combinational
More informationCounters
Counters A counter is the most versatile and useful subsystems in the digital system. A counter driven by a clock can be used to count the number of clock cycles. Since clock pulses occur at known intervals,
More informationFlip-Flops. Because of this the state of the latch may keep changing in circuits with feedback as long as the clock pulse remains active.
Flip-Flops Objectives The objectives of this lesson are to study: 1. Latches versus Flip-Flops 2. Master-Slave Flip-Flops 3. Timing Analysis of Master-Slave Flip-Flops 4. Different Types of Master-Slave
More informationR.G.O. 32 BIT CAMAC COUNTER MODULE USER MANUAL
R.G.O. 32 BIT CAMAC COUNTER MODULE USER MANUAL C.S. Amos / D.J. Steel 16th August 1993 Copyright R.G.O. August 1993 1. General description. 3 2. Encoder formats 3 2.1 A quad B type encoders... 3 2.2 Up/down
More informationT 2 : WR = 0, AD 7 -AD 0 (μp Internal Reg.) T 3 : WR = 1,, M(AB) AD 7 -AD 0 or BDB
Lecture-17 Memory WRITE Machine Cycle: It also requires only T 1 to T 3 states. The purpose of memory write machine cycle is to store the contents of any of the 8085A register such as the accumulator into
More informationClock Domain Crossing. Presented by Abramov B. 1
Clock Domain Crossing Presented by Abramov B. 1 Register Transfer Logic Logic R E G I S T E R Transfer Logic R E G I S T E R Presented by Abramov B. 2 RTL (cont) An RTL circuit is a digital circuit composed
More informationReport on 4-bit Counter design Report- 1, 2. Report on D- Flipflop. Course project for ECE533
Report on 4-bit Counter design Report- 1, 2. Report on D- Flipflop Course project for ECE533 I. Objective: REPORT-I The objective of this project is to design a 4-bit counter and implement it into a chip
More informationUNIT-3: SEQUENTIAL LOGIC CIRCUITS
UNIT-3: SEQUENTIAL LOGIC CIRCUITS STRUCTURE 3. Objectives 3. Introduction 3.2 Sequential Logic Circuits 3.2. NAND Latch 3.2.2 RS Flip-Flop 3.2.3 D Flip-Flop 3.2.4 JK Flip-Flop 3.2.5 Edge Triggered RS Flip-Flop
More informationUniversity of Victoria. Department of Electrical and Computer Engineering. CENG 290 Digital Design I Lab Manual
University of Victoria Department of Electrical and Computer Engineering CENG 290 Digital Design I Lab Manual INDEX Introduction to the labs Lab1: Digital Instrumentation Lab2: Basic Digital Components
More informationDIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES
DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES 1 Learning Objectives 1. Explain the function of a multiplexer. Implement a multiplexer using gates. 2. Explain the
More informationCounter dan Register
Counter dan Register Introduction Circuits for counting events are frequently used in computers and other digital systems. Since a counter circuit must remember its past states, it has to possess memory.
More informationSolution to Digital Logic )What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it,
Solution to Digital Logic -2067 Solution to digital logic 2067 1.)What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it, A Magnitude comparator is a combinational
More informationDistributed by: www.jameco.com --3-4242 The content and copyrights of the attached material are the property of its owner. E2O2-27-X3 Semiconductor MSM2C55A-2RS/GS/VJS This version: Jan. 99 Previous version:
More informationInfineon HYB18T512160AF-3.7 DDR2 SDRAM Circuit Analysis
March 13, 2006 Infineon HYB18T512160AF-3.7 DDR2 SDRAM Circuit Analysis For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology,
More informationECE 2274 Pre-Lab for Experiment Timer Chip
ECE 2274 Pre-Lab for Experiment 6 555 Timer Chip Introduction to the 555 Timer The 555 IC is a popular chip for acting as multivibrators. Go to the web to obtain a data sheet to be turn-in with the pre-lab.
More informationDigital Fundamentals. Lab 5 Latches & Flip-Flops CETT Name: Date:
Richland College School of Engineering & Technology Rev. 0 B. Donham Rev. 1 (7/2003) J. Horne Rev. 2 (1/2008) J. Bradbury Rev. 3 (7/2015) J. Bradbury Digital Fundamentals CETT 1425 Lab 5 Latches & Flip-Flops
More information64CH SEGMENT DRIVER FOR DOT MATRIX LCD INTRODUCTION FEATURES 100 QFP-1420C
INTRODUCTION The KS0108B is a LCD driver LSl with 64 channel output for dot matrix liquid crystal graphic display systems. This device consists of the display RAM, 64 bit data latch, 64 bit drivers and
More informationOutline Dimension. View Angle
320 x 234 Pixels LCD Color Monitor The is a compact full color TFT LCD module, whose driving board is capable of converting composite video signals to the proper interface of LCD panel and is suitable
More information2.6 Reset Design Strategy
2.6 Reset esign Strategy Many design issues must be considered before choosing a reset strategy for an ASIC design, such as whether to use synchronous or asynchronous resets, will every flipflop receive
More informationEECS150 - Digital Design Lecture 2 - CMOS
EECS150 - Digital Design Lecture 2 - CMOS January 23, 2003 John Wawrzynek Spring 2003 EECS150 - Lec02-CMOS Page 1 Outline Overview of Physical Implementations CMOS devices Announcements/Break CMOS transistor
More informationCSE 352 Laboratory Assignment 3
CSE 352 Laboratory Assignment 3 Introduction to Registers The objective of this lab is to introduce you to edge-trigged D-type flip-flops as well as linear feedback shift registers. Chapter 3 of the Harris&Harris
More informationDIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) COUNTERS
COURSE / CODE DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) COUNTERS One common requirement in digital circuits is counting, both forward and backward. Digital clocks and
More informationFinal Project [Tic-Tac-Toe]
Final Project [Tic-Tac-Toe] (In 2 dimension) ECE 249 Session: 3-6pm TA: Jill Cannon Joseph S Kim Ghazy Mahub Introduction As a final project for ECE 249, we will develop a multi-player tic-tac-toe game
More informationNS8050U MICROWIRE PLUSTM Interface
NS8050U MICROWIRE PLUSTM Interface National Semiconductor Application Note 358 Rao Gobburu James Murashige April 1984 FIGURE 1 Microwire Mode Functional Configuration TRI-STATE is a registered trademark
More informationA Combined Combinational-Sequential System
A Combined Combinational-Sequential System Object To construct a serial transmission circuit with a comparator to check the output. Parts () 7485 4-bit magnitude comparators (1) 74177 4-bit binary counter
More informationEE241 - Spring 2005 Advanced Digital Integrated Circuits
EE241 - Spring 2005 Advanced Digital Integrated Circuits Lecture 21: Asynchronous Design Synchronization Clock Distribution Self-Timed Pipelined Datapath Req Ack HS Req Ack HS Req Ack HS Req Ack Start
More informationSequential Logic Basics
Sequential Logic Basics Unlike Combinational Logic circuits that change state depending upon the actual signals being applied to their inputs at that time, Sequential Logic circuits have some form of inherent
More informationA MISSILE INSTRUMENTATION ENCODER
A MISSILE INSTRUMENTATION ENCODER Item Type text; Proceedings Authors CONN, RAYMOND; BREEDLOVE, PHILLIP Publisher International Foundation for Telemetering Journal International Telemetering Conference
More information1. Keyboard and Panel Switch Scanning DX7 CIRCUIT DESCRIPTION The 4 bits BO ~ B3 from the sub-cpu (6805S) are input to the decoder (40H138). The decoder output is sent to the keyboard transfer contacts
More informationCHAPTER 6 COUNTERS & REGISTERS
CHAPTER 6 COUNTERS & REGISTERS 6.1 Asynchronous Counter 6.2 Synchronous Counter 6.3 State Machine 6.4 Basic Shift Register 6.5 Serial In/Serial Out Shift Register 6.6 Serial In/Parallel Out Shift Register
More informationDigital Fundamentals: A Systems Approach
Digital Fundamentals: A Systems Approach Latches, Flip-Flops, and Timers Chapter 6 Traffic Signal Control Traffic Signal Control: State Diagram Traffic Signal Control: Block Diagram Traffic Signal Control:
More informationEE 367 Lab Part 1: Sequential Logic
EE367: Introduction to Microprocessors Section 1.0 EE 367 Lab Part 1: Sequential Logic Contents 1 Preface 1 1.1 Things you need to do before arriving in the Laboratory............... 2 1.2 Summary of material
More informationIT T35 Digital system desigm y - ii /s - iii
UNIT - III Sequential Logic I Sequential circuits: latches flip flops analysis of clocked sequential circuits state reduction and assignments Registers and Counters: Registers shift registers ripple counters
More informationRensselaer Polytechnic Institute Computer Hardware Design ECSE Report. Lab Three Xilinx Richards Controller and Logic Analyzer Laboratory
RPI Rensselaer Polytechnic Institute Computer Hardware Design ECSE 4770 Report Lab Three Xilinx Richards Controller and Logic Analyzer Laboratory Name: Walter Dearing Group: Brad Stephenson David Bang
More informationChapter 8. The MAP Circuit Discussion. The MAP Circuit 53
The MAP Circuit 53 Chapter 8 The MAP Circuit 8-1. Discussion In the preceding chapter, we described the connections to the 68000 microprocessor and actually got it to the point where it ran. It is now
More informationSequential Digital Design. Laboratory Manual. Experiment #3. Flip Flop Storage Elements
The Islamic University of Gaza Engineering Faculty Department of Computer Engineering Spring 2018 ECOM 2022 Khaleel I. Shaheen Sequential Digital Design Laboratory Manual Experiment #3 Flip Flop Storage
More informationVIVO-D203(M) Quick installation and programming guide. Elements of the complete installation
VIVO-D203(M) Quick installation and programming guide English WARNING This quick guide is a summary of the complete installation manual. The manual contains safety warnings and other explanations which
More informationComputer Architecture and Organization
A-1 Appendix A - Digital Logic Computer Architecture and Organization Miles Murdocca and Vincent Heuring Appendix A Digital Logic A-2 Appendix A - Digital Logic Chapter Contents A.1 Introduction A.2 Combinational
More informationLecture 2: Digi Logic & Bus
Lecture 2 http://www.du.edu/~etuttle/electron/elect36.htm Flip-Flop (kiikku) Sequential Circuits, Bus Online Ch 20.1-3 [Sta10] Ch 3 [Sta10] Circuits with memory What moves on Bus? Flip-Flop S-R Latch PCI-bus
More informationVU Mobile Powered by S NO Group
Question No: 1 ( Marks: 1 ) - Please choose one A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register.
More informationTIME SEQUENCE GENERATOR ( GIUSEPPE )
SLAC-TN-70-10 Boris Bertolucci May 1970 A DIGITAL TIME SEQUENCE GENERATOR ( GIUSEPPE ) Abstract A circuit, which starts at T = 0 with an input pulse and puts out 10 pulses which start at arbitrarily variable
More informationNT7108. Neotec Semiconductor Ltd. 新德科技股份有限公司 NT7108 LCD Driver. Copyright: NEOTEC (C)
Copyright: NEOTEC (C) 2002 http:// All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical,
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 7 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter
More informationLogic and Computer Design Fundamentals. Chapter 7. Registers and Counters
Logic and Computer Design Fundamentals Chapter 7 Registers and Counters Registers Register a collection of binary storage elements In theory, a register is sequential logic which can be defined by a state
More informationName Of The Experiment: Sequential circuit design Latch, Flip-flop and Registers
EEE 304 Experiment No. 07 Name Of The Experiment: Sequential circuit design Latch, Flip-flop and Registers Important: Submit your Prelab at the beginning of the lab. Prelab 1: Construct a S-R Latch and
More informationLATCHES & FLIP-FLOP. Chapter 7
LATCHES & FLIP-FLOP Chapter 7 INTRODUCTION Latch and flip flops are categorized as bistable devices which have two stable states,called SET and RESET. They can retain either of this states indefinitely
More informationChapter 7 Counters and Registers
Chapter 7 Counters and Registers Chapter 7 Objectives Selected areas covered in this chapter: Operation & characteristics of synchronous and asynchronous counters. Analyzing and evaluating various types
More informationSystem IC Design: Timing Issues and DFT. Hung-Chih Chiang
System IC esign: Timing Issues and FT Hung-Chih Chiang Outline SoC Timing Issues Timing terminologies Synchronous vs. asynchronous design Interfaces and timing closure Clocking issues Reset esign for Testability
More informationCPS311 Lecture: Sequential Circuits
CPS311 Lecture: Sequential Circuits Last revised August 4, 2015 Objectives: 1. To introduce asynchronous and synchronous flip-flops (latches and pulsetriggered, plus asynchronous preset/clear) 2. To introduce
More informationDecade Counters Mod-5 counter: Decade Counter:
Decade Counters We can design a decade counter using cascade of mod-5 and mod-2 counters. Mod-2 counter is just a single flip-flop with the two stable states as 0 and 1. Mod-5 counter: A typical mod-5
More informationDev Bhoomi Institute Of Technology Department of Electronics and Communication Engineering PRACTICAL INSTRUCTION SHEET
Dev Bhoomi Institute Of Technology Department of Electronics and Communication Engineering PRACTICAL INSTRUCTION SHEET LABORATORY MANUAL EXPERIMENT NO. 1 ISSUE NO. : ISSUE DATE: REV. NO. : REV. DATE :
More information