Clock Domain Crossing. Presented by Abramov B. 1

Transcription

1 Clock Domain Crossing Presented by Abramov B. 1

2 Register Transfer Logic Logic R E G I S T E R Transfer Logic R E G I S T E R Presented by Abramov B. 2

3 RTL (cont) An RTL circuit is a digital circuit composed of: (R) registers of FFs responding to the edge of a clock signal (T) Transfer of wires are the connecting elements (L) Combinatorial Logic gates. Presented by Abramov B. 3

4 RTL (cont) A logic path in RTL circuit is a set of transfer and logic elements connected to each other. A logic path starts at the registers Q output and ends at the registers D input. Presented by Abramov B. 4

5 RTL (cont) Clock Domain in a RTL circuit such that: Registers =>R The clock signal is the same clock signal as for all other Registers. Transfers =>T is part of a Logic path that starts and ends at Registers. Logics => L is agate in a Logic path that starts and ends at RRs. Presented by Abramov B. 5

6 RTL (cont) Clock Speed is limited by the flip-flop delay (clock to output), combinational delay, and setup time. Presented by Abramov B. 6

7 Bridge path Bridge path : A bridge path in an RTL circuit is a logic path that starts at registers Q outputs of one clock domain and ends at registers D inputs of the second clock domain. Bridge Path rule: Bridge path must be sampled with a register clocked by the target domain s clock. Presented by Abramov B. 7

8 Clock Skew Clock Skew : is the difference measured in time between the clock edge (rising or falling edge) of two FFs. Data Delay : is a difference measured in time between the beginning and end of a logic path. Clock domain Rule : CLOCK SKEW << DATA DELAY Critical in shift registers, counters and combinatorial systems. Presented by Abramov B. 8

9 Clock Tree Example H-Tree Most of VLSI circuit signal propagation delay is caused by the wiring Same distance from clock source to all X s CLK Chip X X X X X X X X X X X X X X X X Presented by Abramov B. 9

10 Meta-Stability What are the cases in which meta-stability occurs? When the input signal is an asynchronous signal. When the clock skew/slew is too much (rise and fall time are more than the tolerable values). When interfacing two domains operating at two different frequencies or at the same frequency but with different phase. When the combinational delay is such that flip-flop data input changes in the critical window (setup + hold window) Digital components recover from meta-stable states quickly but the end value is indeterminate Presented by Abramov B. 10

11 Meta-Stability Presented by Abramov B. 11

12 Meta-Stability No other connection to these points Asynchronous Input D SET Q D SET Q Clock CLR Q CLR Q Edge detection can be placed at this point Reset from clock tree Presented by Abramov B. 12

13 Meta-Stability Presented by Abramov B. 13

14 Meta-Stability MTBF Mean Time Between Failures MTBF = clk e ct 2 MET f f C dat 1 f clk = Clock frequency f dat =The average frequency of asynchronous data changes t MET = Time allowed for the FF to settle in a stable state C 1 C 2 = probability of meta-stability catching setup/hold time window =Technology dependent. Describes the speed with which the meta-stable condition is being resolved Presented by Abramov B. 14

15 CDC failure Difficulties causes when interfacing two or more asynchronous clock domains Synchronization failure Un-reliable data transfers Transaction never happen Transaction Happen too many times Transaction delivered wrong data Presented by Abramov B. 15

16 CDC Feedback Although synchronizing a feedback signal is a very safe technique to acknowledge that the first control signal was recognized and sampled into the new clock domain, there is considerable delay associated with synchronizing control signals in both directions before releasing the control signal. Presented by Abramov B. 16

17 CDC -Edge detection Clk Sig_in Sig_in events changes for a long time period. Our aim is to detect moment of change (either rise-detect or fail-detect) and to create one-clock length signal that will advice about sig_in changes. Use this one-cycle edge detection output to control data capture and other necessary functions avoids multiple samples or counts per clock/data input pair Presented by Abramov B. 17

18 CDC -Edge detection (cont) Edge detect only performed after 2 nd Meta DFF Signal from other clock domain D SET Q D SET Q D SET Q CLR Q CLR Q CLR Q Reset from clock tree Clock Presented by Abramov B. 18

19 CDC -Edge detection (cont) Presented by Abramov B. 19

20 Synchronizing Fast Signals Into Slow Clock Domains (Fast 2 Slow) Presented by Abramov B. 20

21 Fast 2 Slow One potential solution to this problem is to assert control signals for a period of time that exceeds the cycle time of the sampling clock. The assumption is that the control signal will be sampled at least once and possibly twice by the receiver clock. Presented by Abramov B. 21

22 Fast 2 Slow Comb Logic D en srst D D Fast clock side ==N srst Counter en Slow clock side N > Tslow Tfast Presented by Abramov B. 22

23 Fast 2 Slow A second possible solution to this problem is pulse extracting (stretch) Presented by Abramov B. 23

24 Fast 2 Slow Lengthened pulse to guarantee that the control signal will be sampled Presented by Abramov B. 24

25 Using acknowledge feedback flag Fast 2 Slow Clock A - fast 1 SET Q Q SET 1 req Clock domain A Clock domain B Parallel data bus Flag D en CLR Q Q CLR D en Clock B - slow ack Disadvantages: Global reset is not used Asynchronous solution Uncertainty in timing constrain boundaries Presented by Abramov B. 25

26 Fast 2 Slow Better than previous solution, but still asynchronous Presented by Abramov B. 26

27 Fast 2 Slow The synchronous decision of a transfers of single pulses between two clock domains problem applicable as well as in FPGA and in ASIC is below resulted completely : Clock A domain - fast One-shot pulse Clock B domain - slow Comb logic T D D D Presented by Abramov B. 27

28 Two simultaneously required control signals A register in the new clock domain requires both a load signal and an enable signal in order to load a data value into the register. If both the load and enable signals are being sent from one clock domain, there is a chance that a small skew between the control signals could cause the two signals to be synchronized into different clock cycles within the new clock domain. Presented by Abramov B. 28

29 Two simultaneously required control signals Presented by Abramov B. 29

30 Two simultaneously required control signals Solution - Consolidating control signals before passing them between clock domains Presented by Abramov B. 30

31 Two simultaneously required control signals Presented by Abramov B. 31

32 Two phase-shifted sequencing control signals Presented by Abramov B. 32

33 Two phase-shifted sequencing control signals Presented by Abramov B. 33

34 Two phase-shifted sequencing control signals The solution to the problem is to send only one control signal into the new clock domain and generate the second phaseshifted sequential control signal within the new clock domain. Presented by Abramov B. 34

35 Control Buses synchronizing between clock domains Presented by Abramov B. 35

36 One-Hot Checker Q: How to check the one-hot code? A: Use dual-rail code! The dual-rail code for 4 bit example: Y1, Y2, Y3, Y4-the outputs from second register of receive clock domain, in which coded by one-hot code. = 0 y1 + y2 y3 y4 r 1 = y3 + y4 + y1 y 2 r + The result of checking XOR between outputs of these symmetric functions. The dual-rail checker should be simply cascaded for any width of checked word. Presented by Abramov B. 36

37 One-Hot Checker 8 bitone-hot code checker architecture Presented by Abramov B. 37

38 Control Buses synchronizing between clock domains Clock domain crossing with data XOR de-correlator/correlator ACLOCK Domain BCLOCK Domain n EC 2 n n 2 n DC XOR XOR REG REG REG 2 n REG REG Presented by Abramov B. 38