PHYSICS 5620 LAB 9 Basic Digital Circuits and Flip-Flops

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1 PHYSICS 5620 LAB 9 Basic Digital Circuits and Flip-Flops Objective Construct a two-bit binary decoder. Study multiplexers (MUX) and demultiplexers (DEMUX). Construct an RS flip-flop from discrete gates. Study the D-latch and J-K flip-flop. Explore the applications of using latches, decoders, MUX s, and DEMUX s. Introduction In this lab we explore some relatively simple digital circuits, many of which are available in a single chip. We consider flip-flops, which are the basic building blocks of all memory systems and study the encoders/decoders, multiplexers (data selectors) and demultiplexers (data distributors). We will explore some applications of flip-flops, latches and MUX s/demux s. Decoders and Encoders A decoder circuit takes information presented in one form and converts it into another form. There are many different kinds of decoders. The most common examples are decoders that convert binary numbers into BCD (binary coded decimal) numbers (IC chips 74184) and BCD numbers into binary numbers (IC chips 74185). Another commonly found decoder circuit is a BCD to seven segment decoder used in driving the signal for seven-segment LED displays. An encoder is the opposite of a decoder. Multiplexers and Demultiplexers A multiplexer or data selector is the electrical analog of a rotary multiposition mechanical switch. It can select any of several input lines and direct that input line to a single output terminal. A MUX has n input selection lines (address lines) and 2 n input lines which can be connected to the single output line. For example, an 8-input MUX has n = 3 selection (address) lines and can connect any one of the 8 inputs to the single output. The inverse of the multiplexer is the demultiplexer or data distributor. It is also like a rotary mechanical switch except the information flow is from the single input to one of the 2 n output lines selected by n address lines. Flip-Flops and Latches A flip-flop is essentially any circuit with two output terminals and two stable voltage states (one higher than the other) for each terminal. A flip-flop is a 1

2 basic binary storage element which holds or latches binary information indefinitely (as long as power is delivered to the circuit) until directed by an input signal to switch the states. These devices are very useful in detecting occurrences of an event and counting the number of events occurred. There is no general agreement on which names should be used for these devices. Some refer to them as flip-flops, and others call them latches. Experiment 9.1 Two-Bit Binary Decoder A A 2x4 Decoder B B Figure 1: 2 Bit Binary Decoder. Construct the two-bit binary decoder in Figure 1 using four NAND gates and two NOT gates. Connect the outputs D 0,D 1,D 2,D 3 to 4 LED s with 220Ω series resistors. Measurement 1 Determine the truth table by observing the LED indicators for all input combinations. 9.2 An Eight Input Multiplexer (MUX) The 74LS151 MUX has eight data input lines and three address lines to select the desired data input, as in Figure 2. There is also an enable (E) input and only when this is connected to ground (LOW) the selected input is connected to the output line. This type of signal is called active low. Connect the circuit as shown. Connect the output Q to one of the LED indicators and E to ground so that the selected input is always passed on to the output line. Select an address (000 to 111) by setting the address lines. Connect 5Hz TTL pulses to all input lines in 2

3 V Q 5 Q 6 Outputs 2 Inputs D4 D5 D6 D7 8x1 Mux A2 A1 A0 Output Inputs D4 D5 D6 D7 E A0 A1 A2 GND Figure 2: Eight Input MUX: 74LS151. succession and see which one is passed on to the output line. When you connect the TTL pulses to the line selected the LED should blink at 5Hz Measurement 2 Fill in a complete truth table for the address lines and the input/output data lines. Applications We can think of using standard gates, encoders/decoders, and MUX s/demux s in several interesting applications. Here are some examples: 9.3 Gating Pulses You can control one pulse with another by a technique called gating. One pulse can be used to control, or gate, one or more other pulses. Connect one AND gate input to a 1Hz TTL clock output and the other AND gate input to a wire which you can connect either to +5V or ground. Connect the output of the AND gate to one LED indicator and the clock to another LED indicator. Include a 220Ω resistor in series with the LED. Measurement 3 Sketch the output for the control signal shown in Figure 3. Describe your observations. 3

4 CLOCK CONTROL OUTPUT time (t) Figure 3: Pulse Gating. 9.4 Prime Number Detector Circuit Here is a logic circuit, Figure 4, using basic gates that takes in a 3-bit binary number A 2 A 1 A 0 and produces a single output X that is true if the input represents a prime number between 0 and 7. A 2 A 1 A 0 X Figure 4: Prime Number Detector Circuit. Measurement 4 Connect and check the circuit. Report your observations in a truth table that includes binary numbers that you put in, its equivalent decimal number and the output, X. Question 1 Using first the truth table and then the logic schematic, show that X = A 2 A 1 +A 0. Question 2 Can you think of a way to implement the above prime number detector using a 1 8 DEMUX(74138 IC)? Draw its circuit diagram. 4

5 A n B n C on C in S n Figure 5: Full Adder Circuit. 9.5 Full Adder All modern digital computers are essentially very high speed adding machines and memory circuits designed to handle numbers in binary form. This often requires addition of two digits and a carry from a previous stage (a total of three binary digits) and produces a sum and carry-out bits. We can accomplish this by a digital circuit that is usually called a full adder. A half adder adds only two digits and doesn t take a carry-in. It is only good for adding the least significant digits of two binary numbers. Measurement 5 Construct the full adder in Figure 5 and check the truth table. Question 3 Work out the Boolean expressions for C on and S n from the logic circuit. Flip-Flops 9.6 The Simple RS Flip-Flop with Two NAND Gates S Q R Q' Figure 6: RS Flip-Flop. Construct an RS flip-flop from two NAND gates of the 7400 IC as shown in Figure 6. Connect the outputs Q and Q to two LED indicators. 5

6 Measurement 6 By applying HIGH and LOW logical levels to S and R inputs, determine and write out the truth table. The RS flip-flop constructed from NAND gates changes state by bringing LOW the input of the NAND gate which had both inputs HIGH. Hence the bars on the inputs R and S. Question 4 Does a HIGH to both S and R change the output Q and Q from their previous levels. Explain your answer. Question 5 What happens when both S and R are LOW? Should such a condition be allowed in a circuit? Explain. 9.7 The Clocked Data Latch or D-Flip-Flop The output of the RS flip-flop responds immediately to input changes, except for a small delay (gate delay) caused by the time taken for the current to flow through the transistor switches. These uncontrolled delays can play havoc in complex digital circuits. This problem is solved by having a system clock. In clocked digital circuits the changes occur through the system, in unison, only when the clock allows it to. The output of the clocked flip-flops respond to input only when the clock pulse (CLK) input changes. The 7474 (see data sheet) is a dual D-latch that passes data from input (D) when the CLKchanges from LOW to HIGH. For this reason it is called a positive edge triggered or rising edge triggered latch. The 7474 IC also is provided with switches for immediate response. These are labeled as PR and CLR. Again, the inversion bars on PRand CLRindicate that these inputs are active low. Construct the circuit with one of the D-latches from the 7474 IC as shown. The clock pulses can be easily created by a push button switch. Connect a 1kΩ resistor between +5V and the normally-closed position of the push button. Use +5V and 0V as the input to D and connect CLKto the normally-open position of the push button. Connect the outputs Q and Q to two LED indicators. Measurement 7 Verify that the input does not change the output until CLKgoes HIGH. Check that Q goes HIGH immediately if you make PR LOW and Q goes LOW immediately if you make CLR LOW. Draw a timing diagram for the operation of the D-latch. 9.8 The JK Flip-Flop The simple RS flip-flop constructed from NAND gates cannot handle both inputs simultaneously LOW since it produces unpredictable results. The JK flip-flop overcomes this problem. 6

7 The JK flip-flop has two inputs, labeled J and K, that affect the outputs Q and its complement Q synchronously with the clock inputs. Some JK flip-flops have preset and clear inputs that make the output go HIGH or LOW immediately. These are also called direct (pre-)set and direct clear inputs. The 7476 IC (see data sheet) is a dual JK latch and has direct preset and clear inputs. This JK latch is negative-edge or falling-edge triggered. This is indicated by a small open circle at the CLKinput. Connect the J and K inputs to +5V or 0V and CLKto a push button switch with normallyclosed pin to 0V and normally-open pin to +5V. Connect Q and Q to an LED indicator and 220Ω series resistor. Table 1: Truth Table for testing the JK Flip-Flop. J K Q n Q n+1 Q n Measurement 8 Complete the truth table, Table 1, for all input combinations, pushing the switch to toggle the clock pulse and cause the flip-flop to change state. Note that Q n is the value of Q before the clock cycles and Q n+1 is the state of the output after the clock cycles. Question 6 Summarize your observations about the behavior of the JK flip-flop as follows: The output changes when CLKgoes. When both J = K = 0, the output. When J = 0 and K = 1, the output. When J = 1 and K = 0, the output. When J = K = 1, the output. 7