EE260: Digital Design, Spring /3/18. n Combinational Logic: n Output depends only on current input. n Require cascading of many structures

Transcription

1 EE260: igital esig, prig 208 4/3/8 EE 260: Itroductio to igital esig equetial Logic Elemets ao Zheg epartmet of Electrical Egieerig Uiversity of Hawaiʻi at Māoa equetial ircuits ombiatioal Logic: Output depeds oly o curret iput Able to perform useful operatios (add/subtract/multiply/ ) equire cascadig of may structures ostly ad iflexible equetial ircuits (cot.) equetial ircuits (cot.) equetial Logic: Output depeds ot oly o curret iput but also o past iput values tore iformatio betwee operatios (o eed for cascadig) Need some type of memory to remember the past iput values ircuits that we have leared so far Iformatio torig ircuits Timed tates equetial Logic: ocept equetial Logic circuits remember past iputs ad past circuit state. Outputs from the system are fed back as ew iputs (usually with delay). The storage elemets are circuits that are capable of storig biary iformatio: memory. ychroous vs. Asychroous machies There are two types of sequetial circuits: ychroous (latch mode) sequetial circuit: the behavior ca be defied from kowledge of its sigal at discrete istats of time. This type of circuits achieves sychroizatio by usig a timig sigal called the clock. Asychroous (fudametal mode) sequetial circuit: the behavior is depedet o the order of iput sigal chages over cotiuous time, ad output ca chage at ay time (clockless). hapter 0: equetial Logic Elemets

2 EE260: igital esig, prig 208 4/3/8 lock igal ychroous equetial ircuits: Flip flops as state memory lock geerator: Periodic trai of clock pulses ifferet duty cycles The flip-flops receive their iputs from the combiatioal circuit ad also from a clock sigal with pulses at fixed itervals of time, as show i the timig diagram. torig Elemets iscrete Evet imulatio a t chage the stored value! Iverters I order to uderstad the time behavior of a sequetial circuit we use discrete evet simulatio. ules: Gates modeled by a ideal (istataeous) fuctio ad a fixed gate delay Ay chage i iput values is evaluated to see if it causes a chage i output value hages i output values are scheduled for the fixed gate delay after the iput chage At the time for a scheduled output chage, the output value is chaged alog with ay iputs it drives uffers imulated NAN Gate Example: A 2-Iput NAN gate with a 0.5 s. delay: F(Istataeous) A ELA 0.5 s. F Assume A ad have bee for a log time At time t=0, A chages to a 0 at t= 0.8 s, back to. Gate elay Models uppose gates with delay s are represeted for = 0.2 s, = s, = 0.5 s, respectively: t (s) A F(I) F ommet 0 0 A== for a log time 0 Þ 0 Ü 0 0 F(I) chages to Ü 0 F chages to after a 0.5 s delay 0.8 Ü 0 Þ 0 F(Istataeous) chages to Þ 0 F chages to 0 after a 0.5 s delay hapter 6: equetial ircuits 3-Apr-8 PJF hapter 0: equetial Logic Elemets 2

3 EE260: igital esig, prig 208 4/3/8 ircuit elay Model osider a simple 2-iput multiplexer: With fuctio: 0.2 = A for = 0.5 = for = 0 A A Glitch is due to delay of iverter What if A coected to? ircuit becomes: With fuctio: = for =, ad (t) depedet o (t 0.9) for = 0 torig tate 0.2 The simple combiatioal circuit has ow become a sequetial circuit because its output is a fuctio of a time sequece of iput sigals. is stored value i shaded area 0.5 torig tate (otiued) imulatio example as iput sigals chage with time. hages occur every 00 s, so that the teths of s delays are egligible. Time ommet 0 0 remembers 0 = whe = 0 Now remembers = for = No chage i whe chages 0 0 = whe = remembers = 0 for = No chage i whe chages represet the state of the circuit, ot just a output. torig tate (otiued) uppose we place a iverter i the feedback path. 0.2 The followig behavior results: The circuit is said ommet to be ustable. 0 0 = whe = For = 0, the circuit has become 0 Now remembers A what is called a oscillator. a be 0 0,. s later used as crude clock. 0,. s later 0 0,. s later latch (NO versio) -- : set-reset, bistable elemet with two extra iputs; ote the udefied output for ==. -- eadig the logic: = (+ ) ; = (+) ==?? Udefied output, because Whe ==, both outputs go to zero. If both iputs ow go to 0, the state of the flip flop is depeds o which iput remais a loger before makig trasitio to 0. Hece, udefied state. MUT be avoided. hapter 0: equetial Logic Elemets 3

4 EE260: igital esig, prig 208 4/3/8 Latch (NAN versio) Latch (NAN versio) et et 0 Hold X NAN X NAN Latch (NAN versio) Latch (NAN versio) et 0 eset 0 Hold et 0 eset 0 Hold 0 Hold X NAN X NAN Latch (NAN versio) Latches 0 0 X NAN isallowed 0 0 et 0 0 eset 0 Hold 0 Hold hapter 0: equetial Logic Elemets 4

5 EE260: igital esig, prig 208 4/3/8 Latch with lock sigal Latch with lock sigal (cot.) LK Latch is sesitive to iput chages ONL whe = LK tore eset et 0 0 isallowed X X tore Latch Latch (cot.) Oe way to elimiate the udesirable idetermiate state i the flip flop is to esure that iputs ad are ever simultaeously. This is doe i the latch: LK LK X LK tore 0 0 eset 0 0 et isallowed X X tore Latch with Trasmissio Gates = à TG closes ad TG2 opes à = ad = =0 à TG opes ad TG2 closes à Hold ad 2 Flip-Flops Latches are trasparet (= ay chage o the iputs is see at the outputs immediately). This causes sychroizatio problems! olutio: use latches to create flip-flops that ca respod (update) ONL o PEIFI times (istead of AN time). hapter 0: equetial Logic Elemets 5

6 EE260: igital esig, prig 208 4/3/8 Alteratives i FF choice Type of FF JK Type of triggerig Utriggered (asychroous) Level-triggered (=) Edge-triggered (risig or fallig edge of ) Master-lave FF cofiguratio usig latches Eables level-triggered behavior Master-lave FF cofiguratio usig latches (cot.) Master-lave J-K Flip-Flop LK tore 0 0 eset 0 0 et isallowed X X tore Whe =, master is eabled ad stores ew data, slave stores old data. Whe =0, master s state passes to eabled slave (=), master ot sesitive to ew data (disabled). Flip-Flop Problem The chage i the flip-flop output is delayed by the pulse width which makes the circuit slower ad/or are permitted to chage while = uppose = 0 ad goes to ad the back to 0 with remaiig at 0 The master latch sets to A is trasferred to the slave uppose = 0 ad goes to ad back to 0 ad goes to ad back to 0 The master latch sets ad the resets A 0 is trasferred to the slave Flip-Flop olutio Use edge-triggerig istead of master-slave A edge-triggered flip-flop igores the pulse while it is at a costat level ad triggers oly durig a trasitio of the clock sigal Edge-triggered flip-flops ca be built directly at the electroic circuit level, or A master-slave flip-flop which also exhibits edgetriggered behavior ca be used. hapter 0: equetial Logic Elemets 6

7 EE260: igital esig, prig 208 4/3/8 Edge-triggered Flip-Flops Attach level-triggered to level-triggered, usig complemeted clocks. -Type Positive Edge-Triggered Flip-Flop: Positive-Edge Triggered Flip-Flop Formed by addig iverter to clock iput chages to the value o applied at the positive clock edge withi timig costraits to be specified Our choice as the stadard flip-flop for most sequetial circuits Positive Edge-Triggered J-K Flip-Flop tadard Graphics ymbols Latches -latch -latch -latch with = -latch with =0 tadard Graphics ymbols (cot.) tadard Graphics ymbols (cot.) Master-lave Flip Flops Edge-triggered Flip Flops J K J K J K J K Triggered Triggered Triggered JK Triggered JK Triggered Triggered Triggered JK Triggered JK hapter 0: equetial Logic Elemets 7

8 EE260: igital esig, prig 208 4/3/8 haracteristic Tables efies the logical properties of a flip-flop (such as a truth table does for a logic gate). (t) preset state at time t (t+) ext state at time t+ haracteristic Tables (cot.) JK Flip-Flop J K (t+) Operatio 0 0 (t) No chage/hold 0 0 eset 0 et (t) omplemet haracteristic Tables (cot.) Flip-Flop (t+) Operatio 0 0 (t) No chage/hold 0 0 eset 0 et? Udefied/Ivalid haracteristic Tables (cot.) Flip-Flop (t+) Operatio 0 0 et eset haracteristic Equatio: (t+) = (t) haracteristic Tables (cot.) T Flip-Flop T (t+) Operatio 0 (t) Hold (t) omplemet Obtaied by JK Flip-Flop with J=K=T haracteristic Equatio: (t+) = T (t) + T(t) irect Iputs At power up or at reset, all or part of a sequetial circuit usually is iitialized to a kow state before it begis operatio This iitializatio is ofte doe outside of the clocked behavior of the circuit, i.e., asychroously. irect ad/or iputs that cotrol the state of the latches withi the flip-flops are used for this iitializatio. For the example flip-flop show 0 applied to resets the flip-flop to the 0 state 0 applied to sets the flip-flop to the state hapter 0: equetial Logic Elemets 8

9 EE260: igital esig, prig 208 4/3/8 Asychroous et/eset Asychroous et/eset (cot.) May times it is desirable to asychroously (i.e., idepedet of the clock) set or reset FFs. Example: At power-up to that we ca start from a kow state. Asychroous set == direct set == Preset Asychroous reset == direct reset == lear J K IEEE stadard graphics symbol for JK- FF with direct set & reset idicates that cotrols all other iputs whose label starts with. I this case, cotrols J ad K. Fuctio Table J K (t+) 0 X X X Preset 0 X X X 0 lear 0 0 X X X Udefied 0 0 (t) Hold 0 0 eset 0 et (t) -- omplemet Flip-Flop Timig Parameters Flip-Flop Timig Parameters (cotiued) t s - setup time t h - hold time t w - clock pulse width t px - propagatio delay t PHL - High-to- Low t PLH - Low-to- High t pd - max (t PHL, t PLH ) t s - setup time Master-slave - Equal to the width of the triggerig pulse Edge-triggered - Equal to a time iterval that is geerally much less tha the width of the the triggerig pulse t h - hold time - Ofte equal to zero t px - propagatio delay ame parameters as for gates except Measured from clock edge that triggers the output chage to the output chage hapter 0: equetial Logic Elemets 9