Slide 1. Flip-Flops. Cross-NOR SR flip-flop S R Q Q. hold reset set not used. Cross-NAND SR flip-flop S R Q Q. not used reset set hold 1 Q.
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1 Slide Flip-Flops Cross-NOR SR flip-flop Reset Set Cross-NAND SR flip-flop Reset Set S R reset set not used S R not used reset set 6.7 Digital ogic
2 Slide 2 Clocked evel-triggered NAND SR Flip-Flop S R SR inputs disabled reset SR inputs set enabled indeterminate R S NAND enable gates SR flip-flop 6.7 Digital ogic 2
3 Slide 3 Edge-Triggered SR Flip-Flops We can make the level triggered flip-flop more flexible (in terms of timing control) by turning it into an edge-triggered flip-flop. An edge-triggered flip-flop only samples the inputs during either a positive or negative clock edge. This conversion can be done by taking the clock signal and running it through a level-triggered, pulse generator network and taking the corresponding output as the clock signal. Positive edge-triggered delay gate Y Z Negative edge-triggered delay gate Z Y Y Z Y 6.7 Digital ogic Z 3
4 Slide 4 evel and Edge Triggered Flip-Flop Symbols no triangle means level-triggered triangle means edge-triggered S R no bubbles means active- IG input S R S R bubble next to triangle means negative edge-triggered input inverted output (complement) S R edge-triggered S R S R 6.7 Digital ogic 4 no bubble next to triangle means positive edge-triggered input
5 Slide 5 D-Type Flip-Flops Basic D-type flip-flop or latch D (data) S D Reset Set D R SR flip-flop logic symbol D NAND made into an inverter 6.7 Digital ogic 5
6 Slide 6 Divide by Two Circuit Note: Edge Detector D D At clock pulse edge, goes to D So every time there is a clock pulse, is set to the old value of D. Therefore, changes (as does D) but by the time D changes, the edge is past. 6.7 Digital ogic 6
7 Slide 7 Stop-Go Indicator D D D green 3Ω red ED 3Ω green ED red 6.7 Digital ogic 7
8 Slide 8 Divide-by-Two Counter In D In/2 D = 6.7 Digital ogic 8
9 Slide 9 Synchronizer A stop start D B A D B oldold Set Set Reset 6.7 Digital ogic 9
10 Slide Synchronizer 2 We see timing is important, so we want to synchronize signals. On/Off D out clock edge D clock off on off ined up with clock, but not result of pulse. 6.7 Digital ogic
11 Slide J Flip-Flops J Clock (C) pulse generator Z Positive edge-trigger positive edge-trigger negative edge-trigger C 6.7 Digital ogic J J C Negative edge-trigger
12 Slide 2 J Flip-Flops 2 R S R in is (,) output is high; S in is (,) output is high. all outputs are high. The problem is that you can not this condition. The input, can only outputs of (,) or (,). 6.7 Digital ogic 2
13 Slide 3 Positive edge-trigger C J Reset Set Toggle J Flip-Flops 3 Negative edge-trigger C J Reset Set Toggle 6.7 Digital ogic 3
14 Slide 4 J Flip-Flop with Preset and Clear CR J 6.7 Digital ogic 4
15 Slide 5 J Flip-Flop with Preset and Clear (Negative Edge-Triggered) CR J J C CR, Preset Clear not used Reset Set Toggle = state of before IG-to-OW edge of clock. 6.7 Digital ogic 5
16 Slide 6 J Flip-Flop with Preset and Clear (Positive Edge-Triggered) CR J J C CR, Preset Clear not used Reset Set Toggle = state of before OW-to-IG edge of clock. 6.7 Digital ogic 6
17 Slide 7 MOD-6 Ripple Counter/divide-by-2,4,8,6 Counter +5V J CR J CR J CR J CR CR divide-by-2 divide-by-4 divide-by-8 divide-by-6 CR (SB) (MSB) Digital ogic
18 Slide 8 MOD-6 Ripple Counter 2 +5V J J J J CR CR CR CR CR 2 3 This circuit will count to up to 5 and then will disable (all bits = ). Note: If one uses the s as the counting bits instead of the s, the Counter will count down from 5 and disable when is reached. 6.7 Digital ogic 8
19 Slide 9 MOD-6 Synchronous Counter +5V J J J J CR CR CR CR CR divide-by-2 divide-by-4 divide-by-8 divide-by-6 CR (SB) (MSB) Digital ogic
20 Slide 2 4-Bit Counter IC The 7493 s internal structure consists of four J flip-flops connected to provide separate MOD-2 and MOD-8 sections. Both of these are clocked by separate clock inputs. The MOD-2 uses C p as its clock input while MOD-8 uses C p. 4 C p C p MR MR MR count count count 6.7 Digital ogic 2
21 Slide Digital ogic Presettable 4-bit Binary Up/Down Counter CP U CP D MR P D D D 2 D TC U TC D MR P C pu C pd D D D 2 D TC U TC D Count up Count down Reset Parallel load count up count down Inputs Outputs = IG voltage level; = OW voltage level; = don t care; = OW-to-IG voltage transition
22 Slide 22 Block Diagrams of Various Shift Registers Serial in / Serial out: Serial in Serial out Parallel in / Serial out: Parallel in Serial out Serial in / Parallel out: Serial in Parallel out 6.7 Digital ogic 22
23 Slide 23 Creating Devices t on t off t on Some device creating power - There are two modes for destruction.) Short term t on is too long. Instantaneous heat load too high. Assume no heat dissipation during t on. 2.) long term - duty cycle t on /t off too high. Test for 2 conditions t on <t max t on /t off < duty cycle n-bits MSB SB overflow counter zero? up down reset clock-t c period If overflow trigger relay ON t c 2 n =t max If zero disable, clock until clock/n next edge of ON ON 6.7 Digital ogic ON 23
24 Slide 24 Problem Explain why mon-stable is not so useful. Solve problem using: x clock flip/flops, simple logic x up/down counter borrow carry clear 6.7 Digital ogic 24
25 Slide 25 4-bit Serial in/serial out Shift Registers Serial in Shift Right Serial out Serial Input D 3 3 f-f D 2 2 f-f D f-f D f-f Serial Output clock Serial out Shift eft Serial in Serial Output D f-f D f-f D 2 2 f-f 2 D 3 3 f-f 3 Serial Input clock 6.7 Digital ogic 25
26 Slide 26 Parallel-to-Serial Shift Register SIFT/OAD SIFT OAD D D D 2 D 3 inhibit D f-f D f-f D 2 2 f-f 2 D 3 3 f-f 3 Serial output Clock Clock inhibit SIFT/OAD D D D 2 D 3 Serial out Inhibit Serial Shift 6.7 Digital ogic 26
27 Slide 27 J Parallel-to-Serial Shift Register oad/shift D D 2 D 3 D J J J J Serial output clock 6.7 Digital ogic 27
28 Slide 28 8-Bit Serial-to-Parallel Data Converter +5V Serial data input clock 9 MR 2 D Sb D Sa 4 V CC D D D 2 D 3 D 4 D 5 D 6 D bit Parallel word GND 7 Divide-by-8 counter GND Octal D-type Flip-flop 6.7 Digital ogic 28
29 Slide 29 8-Bit Parallel-to-Serial Interface +5V Parallel in ASCII & Parallel load Clock enable clock D D D 2 D 3 D 4 D 5 D 6 D 7 P 5 CE 2 6 V CC 7 7 SB comes out first 9 7 Serial Device DS GND Digital ogic 29
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