Digital Fundamentals: A Systems Approach

Transcription

1 Digital Fundamentals: A Systems Approach Latches, Flip-Flops, and Timers Chapter 6

2 Traffic Signal Control

3 Traffic Signal Control: State Diagram

4 Traffic Signal Control: Block Diagram

5 Traffic Signal Control: Timing Circuits

6 Latches A latch is a temporary storage device that has two stable states (bistable). It is a basic form of memory. The S-R (Set-Reset) latch is the most basic type. It can be constructed from NOR gates or NAND gates. With NOR gates, the latch responds to active-high inputs; with NAND gates, it responds to active-low inputs.

7 Latches The active-high S-R latch is in a stable (latched) condition when both inputs are LOW. Assume the latch is initially RESET (Q = 0) and the inputs are at their inactive level (0). To SET the latch (Q = 1), a momentary HIGH signal is applied to the S input while the R remains LOW. To RESET the latch (Q = 0), a momentary HIGH signal is applied to the R input while the S remains LOW.

8 Latches The active-low S-R latch is in a stable (latched) condition when both inputs are HIGH. Assume the latch is initially RESET (Q = 0) and the inputs are at their inactive level (1). To SET the latch (Q = 1), a momentary LOW signal is applied to the S input while the R remains HIGH. To RESET the latch a momentary LOW is applied to the R input while S is HIGH. Never apply an active set and reset at the same time (invalid).

9 Latches The three modes of basic S-R operation

10 Gated S-R Latch A gated latch is a variation on the basic latch. The gated latch has an additional input, called enable (EN) that must be HIGH in order for the latch to respond to the S and R inputs.

11 Gated D Latch The D latch is an variation of the S-R latch but combines the S and R inputs into a single D input as shown: A simple rule for the D latch is: Q follows D when the EN is active.

12 Flip-flops A flip-flop differs from a latch in the manner it changes states. A flip-flop is a clocked device, in which only the clock edge determines when a new bit is entered. The active edge can be positive or negative.

13 Edge-Triggered Flip-flops The output from an edgetriggered flip-flop changes on the positive-going or negative-going edge of its clock signal. A bubble on the clock input indicates that it is a negative-edge triggered flip-flop.

14 Edge-Triggered D Flip-flops The data bit at the D-input is transferred to the component output on the edge of the clock signal. Once triggered, the output (Q) equals the last value at the D input until a new value is triggered in.

15 J-K Flip-flops The values at the J and K inputs to a J-K flip-flop determine its output state. The results of the four possible input combinations of J and K are shown.

16 Flip-flop Asynchronous Inputs Synchronous (clocked) inputs are transferred on the triggering edge of the clock. Most flip-flops have other inputs that are asynchronous, meaning they operate independently of the clock. Asynchronous flip-flop inputs are normally labeled preset (PRE) and clear (CLR). These inputs are usually active LOW. A J-K flip flop with active LOW preset and CLR is shown. Note that the asynchronous inputs always override the synchronous inputs.

17 Flip-Flop Frequency Division Flip-flops can be used as frequency dividers, as shown below. The D and J-K flip flops on the left are wired as divide-by-2 circuits. The J-K flip-flops on the right are cascaded to form a divide-by-4 circuit.

18 Flip-flops can be used to count the number of clock signals they receive as shown here. Each CLK input triggers the flip-flops, which are wired to toggle whenever triggered. The Q A and Q B outputs indicate the number of CLK inputs received. Flip-Flop Counters

19 Traffic Signal Control: Sequential Logic Diagram

20 Flip-Flop Propagation Delay Propagation delay time is specified for the rising and falling outputs. It is measured between the 50% level of the clock to the 50% level of the output transition. Propagation delay (t PLH ) is measured as shown in (a). Propagation delay (t PHL ) is measured as shown in (b).

21 Flip-flop Propagation Delay Another propagation delay time specification is the time required for an asynchronous input to cause a change in the output. Again it is measured from the 50% levels.

22 Flip-flop Set-up Time Another time-related specification is flip-flop set-up time. This is the minimum time between the arrival of an input to the D (or J-K) flip-flop and the CLK signal.

23 Flip-flop Hold Time Another time-related specification is flip-flop hold time. This is the minimum time over which the input to the D (or J-K) flip-flop must remain stable after the arrival of the CLK input for reliable triggering.

24 One-Shots The one-shot or monostable multivibrator is a device with only one stable state. When triggered, it goes to its unstable state for a predetermined length of time, then returns to its stable state.

25 Nonretriggerable One-Shots A nonretriggerable one-shot does not respond to any triggers that occur while in its unstable state, as shown here.

26 Retriggerable One-Shots Retriggerable one-shots respond to any trigger, even if it occurs while the component is in its unstable state. If it occurs during the unstable state, the state is extended by an amount equal to its normal output pulse width.

27 A One-Shot Sequential Timer One-shots can be wired (as shown) to form a sequential timer; a circuit that can set up a sequence of actions, such as lighting a group of lights in a particular order.

28 555 Timer One-Shot The 555 timer can be configured in various ways, including as a one-shot. The pulse width is approximately t W = 1.1R 1 C 1.

29 555 Timer Astable Multivibrator An astable multivibrator (also called a free-running multivibrator) is a circuit that produces a steady stream of output pulses as long as power is applied. In this circuit C 1 charges through R 1 and R 2 and discharges through only R 2. The output frequency is given by: f ( R R2 ) C 1

30 S-R Latch with VHDL and Verilog

31 D Flip-Flop with VHDL and Verilog

32 J-K Flip-Flop with VHDL and Verilog

33 Traffic Signal Control: Block Diagram

34 Traffic Signal Control Programming Model

35 Latch Bistable Clock D flip-flop J-K flip-flop Key Terms A bistable digital circuit used for storing a bit. Having two stable states. Latches and flipflops are bistable multivibrators. A triggering input of a flip-flop. A type of bistable multivibrator in which the output assumes the state of the D input on the triggering edge of a clock pulse. A type of flip-flop that can operate in the SET, RESET, no-change, and toggle modes.

36 Propagation delay time Set-up time Hold time Timer Key Terms The interval of time required after an input signal has been applied for the resulting output signal to change. The time interval required for the input levels to be on a digital circuit. The time interval required for the input levels to remain steady to a flip-flop after the triggering edge in order to reliably activate the device. A circuit that can be used as a one-shot or as an oscillator.

37 Quiz 1. The output of a D latch will not change if a. the output is LOW b. Enable is not active c. D is LOW d. all of the above

38 Quiz 2. The D flip-flop shown will on the next clock pulse a. set b. reset c. latch d. toggle CLK D CLK Q Q

39 Quiz 3. How many asynchronous inputs does the J-K fllipflop below have? a. 1 b. 2 c. 3 d. 4 K Q J PRE CLK Q CLR

40 Quiz 4. Assume the output from a leading-edge triggered J-K flip flop is initially HIGH. With the inputs shown, on which clock pulse with the output will go from HIGH to LOW? a. 1 b. 2 c. 3 d. 4 CLK J K

41 Quiz 5. The time interval illustrated is called a. t PHL 50% point on triggering edge b. t PLH c. set-up time CLK d. hold time Q? 50% point on LOW-to- HIGH transition of Q

42 Quiz 6. The time interval illustrated is called a. t PHL b. t PLH c. set-up time D CLK d. hold time?

43 Quiz 7. The circuit shown below is a/an a. astable multivibrator b. data storage device c. frequency multiplier HIGH HIGH d. frequency divider J Q A J Q B f out f in CLK CLK K K

44 Quiz 8. The circuit shown has parallel data inputs and outputs. What kind of circuit is it? a. An astable multivibrator b. A data storage circuit c. A frequency multiplier d. A frequency divider Clock Clear Output lines Q 0 Q 1 Q 2 Q 3

45 9. A retriggerable one-shot with an active HIGH output has a pulse width of 20 ms and is triggered from a 60 Hz line. The output will be a a. series of 16.7 ms pulses b. series of 20 ms pulses c. constant LOW d. constant HIGH Quiz

46 Quiz 10. The circuit illustrated is a a. astable multivibrator b. monostable multivibrator +V CC c. frequency multiplier d. frequency divider R 1 R 2 (7) (6) RESET DISCH THRES (4) (4) V CC OUT (3) C 1 (2) TRIG CONT GND (5) (1)

47 Answers 1. b 2. d 3. b 4. c 5. b 6. d 7. d 8. b 9. d 10. a