CHAPTER 11 LATCHES AND FLIP-FLOPS
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1 CHAPTER 11 1/25 LATCHES AND FLIP-FLOPS This chapter in the book includes: Objectives Study Guide 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop 11.6 J-K Flip-Flop 11.7 T Flip-Flop 11.8 Flip-Flop with Additional Inputs 11.9 Summary Problems Programmed Exercise
2 Objectives 2/25 Topics introduced in this chapter: 1. Explain in words the operation of S-R and gated D latches 2. Explain in words the operation of D, D-CE, S-R, J-K and T flip-flops 3. Make a table and derive the characteristic (next-state) equation for such latches and flip-flops. State any necessary restrictions on the input signals 4. Draw a timing diagram relating the input and output of such latches flip-flops 5. Show how latches and flip-flops can be constructed using gates. Analyze the operation of a flip-flop that is constructed of gates and latches
3 11.1 Introduction 3/25 Fig Fig Stable state To construct a switching circuit has a memory, must introduce feedback to circuit Unstable state
4 11.2 Set-Reset Latch 4/25 Fig Fig S=R=0 (Q=0) S=1, R=0 S=R=0 (Q=1) S=0, R=1
5 11.2 Set-Reset Latch 5/25 Fig S-R Latch (cross-coupled structure) Fig Improper S-R Latch Operation (S=R=1; prohibited)
6 11.2 Set-Reset Latch 6/25 Fig Timing Diagram for S-R Latch Table S-R Latch Next State and Output
7 11.2 Set-Reset Latch 7/25 Fig Derivation of Q + for an S-R Latch Q( t ε ) R( t)' S( t) R( t)' Q( t) R( t)'[ S( t) Q( t)] Q S RQ SR 0
8 11.2 Set-Reset Latch 8/25 Fig Switch Debouncing with an S-R Latch
9 11.2 Set-Reset Latch 9/25 Fig S R Latch (c)
10 11.3 Gated D Latch 10/25 Figure Gated D Latch
11 11.3 Gated D Latch 11/25 Figure Symbol and Truth Table for Gated Latch
12 11.4 Edge-Triggered D Flip-Flop 12/25 Figure D Flip-Flops + Q = D
13 11.4 Edge-Triggered D Flip-Flop 13/25 Figure Timing for D Flip-Flop (Falling-Edge Trigger)
14 11.4 Edge-Triggered D Flip-Flop 14/25 Figure D Flip-Flop (Rising-Edge Trigger)
15 11.4 Edge-Triggered D Flip-Flop 15/25 Figure Setup and Hold Times for an Edge-Triggered D Flip-Flop t t t su h p : the setup time : the hold time : the propagation delay
16 11.4 Edge-Triggered D Flip-Flop 16/25 Figure Determination of Minimum Clock Period Flip flop delay 5ns Inverter delay 2ns Setup time 3 ns Q 가 1 -> 0 -> 1 으로변함
17 11.5 S-R Flip-Flop 17/25 Figure S-R Flip-Flop Operation summary: S = R = 0 no state change S = 1, R = 0 set Q to 1 (after active Ck edge) S = 0, R = 1 reset Q to 0 (after active Ck edge) S = R = 1 not allowed
18 11.5 S-R Flip-Flop 18/25 Figure S-R Flip-Flop Implementation and Timing
19 11.6 J-K Flip-Flop JKQ Q Q + = JQ' + K'Q b Truth table and characteristic equation Figure J-K Flip-Flop (Q Changes on the Rising Edge) 19/25
20 11.6 J-K Flip-Flop 20/25 Figure Master-Slave J-K Flip-Flop (Q Changes on Rising Edge)
21 11.7 T Flip-Flop 21/25 Figure T Flip-Flop Q + = T'Q + TQ' = Q T Figure Timing Diagram for T Flip-Flop (Falling-Edge Trigger)
22 11.7 T Flip-Flop 22/25 Figure Implementation of T Flip-Flop Q JQ KQ TQ TQ
23 11.8 Flip-Flops with Additional Inputs 23/25 Figure D Flip-Flop with Clear and Preset b Figure Timing Diagram for D Flip-Flop with Asynchronous Clear and Preset
24 11.8 Flip-Flops with Additional Inputs 24/25 Figure D Flip-Flop with Clock Enable The characteristic equation : Q QCE DCE The MUX output : Q D QCE D in CE
25 11.9 Summary 25/25 Q S RQ SR 0 (S-R latch or flip-flop) Q GD GQ (gated D latch) Q D (D flip-flop) Q DCE QCE (D-CE flip-flop) Q JQ KQ (J-K flip-flop) Q T Q TQ TQ (T flip-flop)
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