Sequential Logic. Analysis and Synthesis. Joseph Cavahagh Santa Clara University. r & Francis. TaylonSi Francis Group. , Boca.Raton London New York \

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1 Sequential Logic Analysis and Synthesis Joseph Cavahagh Santa Clara University r & Francis TaylonSi Francis Group, Boca.Raton London New York \ CRC is an imprint of the Taylor & Francis Group, an informa business

2 CONTENTS Preface xi Chapter 1 Review of Combinational Logic Number Systems Binary Number System Octal Number System Decimal Number System Hexadecimal Number System Number Representations Sign Magnitude Diminished-Radix Complement Radix Complement Boolean Algebra Minimization Techniques Algebraic Minimization Karnaugh Maps Quine-McCluskey Algorithm Logic Symbols Analysis of Combinational Logic Synthesis of Combinational Logic Multiplexers Decoders Encoders Comparators Storage Elements SR Latch D Flip-Flop JK Flip-Flop T Flip-Flop Programmable Logic Devices Programmable Read-Only Memories Programmable Array Logic Programmable Logic Array Problems 69 Chapter 2 Analysis of Synchronous Sequential Machines Sequential Circuits Machine Alphabets Formal Definition of a Synchronous Sequential Machine 82 '

3 viii Contents 2.2 Classes of Sequential Machines Combinational Logic Registers 93.,; Counters Moore Machines Mealy Machines Asynchronous Sequential Machines Additional Definitions for Synchronous Sequential. Machines Methods of Analysis Next-State Table Present-State Map Next-State Map Input Map Output Map 140;, Timing Diagram State Diagram Analysis Examples Complete and Incomplete Synchronous Sequential Machines Complete Synchronous Sequential,Machines Incomplete Synchronous Sequential Machines Problems Chapter 3 Synthesis of Synchronous Sequential Machines Synthesis Procedure Equivalent States Synchronous Registers Parallel-In, Parallel-Out Registers Parallel-In, Serial-Out Registers '- Serial-Iri, Parallel-Out Registers Serial-In^ Serial-Out Registers Linear Feedback Shift Registers Combinational Shifter 218 ' 3.3 Synchronous Counters Modulo-8 Counter Modulo-10 Counter234 ;, " V-.-,' Johnson Counter Binary-to-Gray Code Converter Moore Machines 254,..-. : ; 3.5. Mealy Machines 277., : 3.6 Moore-Mealy Equivalence 298 b.. : Mealy-to-Moore Transformation Moore-to-Mealy Transformation Output Glitches 307

4 Contents ix Glitch Elimination Using State Code Assignment Glitch Elimination Using Storage Elements 319 ' Glitch Elimination Using Complemented Clock Glitch Elimination Using Delayed Clock Glitches and Output Maps Compendium of Output Glitches Problems 344 Chapter 4 Synthesis of Synchronous Sequential Machines Multiplexers for 8 Next-State Logic Linear-Select Multiplexers Nonlinear-Select Multiplexers Decoders for 1 Output Logic Programmable Logic Devices Programmable Read-Only Memory Programmable Array Logic 421,' '..,., Programmable Logic Array 432.,.' Field-Programmable Gate Array 437 > 4.4 > a Microprocessor-Controlled Sequential Machines 448, r..., General Considerations 449,...., Mealy Machine Synthesis 453.-, Machine State Augmentation 461, Moore and Mealy Outputs System Architecture Multiple Machines Sequential Iterative Machines Error Detection in Synchronous Sequential Machines 489 : ' : 4:7-"' Problems 500 ' " : - ' ; Chapter 5 Analysis of Asynchronous Sequential Machines Introduction Fundamental-Mode Model Methods of Analysis ; Hazards 553 : Static Hazards Dynamic Hazards Essential Hazards Multiple-Order Hazards Oscillations 578 >,.,.., :,. 5.6 Races 582 ' ''''' ' ' Noncritical Races 583, Cycles 586

5 Contents Critical Races Problems 590 Chapter 6 Synthesis of Asynchronous Sequential Machines Introduction Synthesis Procedure State Diagram Primitive Flow Table Equivalent States Merger Diagram Merged Flow Table Excitation' Maps and Equations Output Maps and Equations Logic Diagram Synthesis Examples Mealy Machine with Two Inputs and One Output Mealy Machine with Two Inputs and One Output Using a Programmable Logic Array (PLA) Moore Machine with One Input and One Output Mealy Machine with Two Inputs and Two Outputs Mealy Machine with Three Inputs and One Output Mealy Machine with Two Inputs and Two Outputs Problems 777 ' Chapter 7 Pulse-Mode Asynchronous Sequential Machines Analysis Procedure ? Latches as Storage Elements ? Latches with D Flip-Flops as Storage Elements Synthesis Procedure SR Latches as Storage Elements TFlip-Flops as Storage Elements ?-r Flip-Flops as Storage Elements ? Latches with D Flip-Flops as Storage Elements Problems 850 Appendix Answers to Selected Problems 861 Index 889

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