AN EFFICIENT LOW POWER DESIGN FOR ASYNCHRONOUS DATA SAMPLING IN DOUBLE EDGE TRIGGERED FLIP-FLOPS

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1 AN EFFICIENT LOW POWER DESIGN FOR ASYNCHRONOUS DATA SAMPLING IN DOUBLE EDGE TRIGGERED FLIP-FLOPS NINU ABRAHAM 1, VINOJ P.G 2 1 P.G Student [VLSI & ES], SCMS School of Engineering & Technology, Cochin, Kerala, INDIA 2 Assistant Professor, SCMS School of Engineering & Technology, Cochin, Kerala, INDIA 1 ninuliz1190@gmail.com, 2 vinojpg@gmail.com 1346 ABSTRACT In a synchronous circuit design, power consumption and energy efficiency plays a vital role. Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power consumption of idle modules or idle cycles. An efficient technique to reduce power consumption is the use of Double Edge Triggered Flipflops (DETFF) since they can maintain the same throughput as Single Edge Triggered Flip-flops (SETFF s) while only using half of the clock frequency. Clock gating technique integrated with DETFF further reduces the power consumption but asynchronous data sampling problem (change in output between clock edges) is introduced. In order to eliminate asynchronous data sampling problem, two methods have been used and their power analysis has been estimated. In order to further reduce the power consumption, a new design of clock gated DETFF have been proposed. The designs have been implemented using Tanner EDA v13.0 tool. Keywords: Asynchronous data sampling, DETFF, Clock gating, low-power. 1. INTRODUCTION Low power has emerged as a principal theme in today s world of electronics industries. Power dissipation has become an important consideration as performance and area for VLSI Chip design [1]. As technology shrinks below 100nm, reducing power consumption and over all power management on chip are the key challenges due to increased complexity. Normally, high-performance chips will have high clock frequency, which leads to high power consumption. Therefore, less power consuming designs are needed. The clock tree and the timing components such as flip-flops and latches are the major source of power consumption in synchronous circuits. Flip-flops are the commonly used component in the digital system and are used in computational circuits and registers in pipeline structures to store the data for additional processing. In a conventional single edge-triggered (SETFF) flip-flop data moves from input to output in synchrony with one edge of the clock. Recently the use of double edge-triggered (DETFF) flip-flops has been proposed for low-power circuit s design [2]. In order to transfer data in a DET flip-flop both rising and falling edges of the clock signal are used. In this way, for a given throughput, the clock frequency can be halved with respect to a system using SET flip-flops, with a reduction of power dissipation and increasing performance. But these flip-flops also consume power due to transitions in the clock signal. In order to reduce the power consumption further, clock-gating technique has been developed to disable the clock switching when it is not required and when there is no change on the input to the flip-flop. By incorporating clock gating technique with DETFF, power consumption can be reduced further [3]. But incorporating clock gating technique with DETFF [4] introduces asynchronous data sampling between the clock edges at the output side thereby creating data miss-communication error. This paper deals with the different design implementations of clock gated DETFFs and the methods to eradicate the asynchronous sampling problem. In order to reduce the power consumption further a new design for DETFF has been proposed which consumes less average power than other designs and is suitable for high performance applications. 2. ASYNCHRONOUS DATA SAMPLING The clock gated system has the terminology as global clock signal CLK; the (internal) gated clock signal C; clock gating control signal CG; input data D; and, output data Q. The internal clock controls the gated circuits in clock gated circuits. The internal clock is separated from the global clock during gated periods. When the gating signal is in non-active state and if the internal clock is not synchronised with the global clock then the internal clock needs to switch immediately to match the global clock. Since this switching is extra and not synchronized with the external clock, creates an asynchronous data sampling, which is shown by the output changing between clock edges. An assumption is made that all transitions on Q should be synchronized with an active clock edge. Data miscommunication errors might be caused due to asynchronous data sampling. The CG signal is activated when there is a transition in D. When an external pulse is given flip-flop is triggered. The C signal maintains its value instead of generating an active edge in the gating mode. C changes after the transition on CLK in the non-gating mode. Asynchronous data transition may occur, if D changes (i.e., it enters the non-gating mode) while C is not

2 1347 equal to CLK and is shown as spikes at the output. Each clock-gating transition has the potential to create the asynchronous sampling issue but this occurs only at specific conditions. Fig.1. General Block diagram of clock gated DETFF There are certain conditions for the occurrence of asynchronous data sampling problem and it is shown in Table 1. DESIGNS CONDITIONS FOR ASYNCHRONOUS DATA SAMPLING G_DETFF D changes when CLK C DET_SRSFF D changes when CLK = O DHSCGFF D changes when CLK = O Table 1. Conditions for asynchronous data sampling 3. ANALYSIS OF ASYNCHRONOUS DATA SAMPLING ON DIFFERENT CLOCK GATED DETFF 3.1 Asynchronous Sampling in the Gated Double Edge-Triggered Flip-Flop with Transmission Gate (G_DETFF) [5] The G_DETFF contains two major parts, the T_DETFF and the clock-gating circuitry which includes a comparator and the clock-gating module. The data signal arrives into the T_DETFF and the comparator simultaneously, and the comparator checks the current data input D and the output Q. If D and Q are not equal, which means the input has changed since the last comparison, then an active gated clock signal will be generated by the clock gating circuitry, and the gated clock signal will be sent to the T_DETFF to trigger the storage. The input data will be passed through to the output. Otherwise, the entire system remains in the previous state. There are two variable factors when the flip-flop operates: 1) for the last transition before clock gating was applied which edge triggered the flip flop and 2) when clock-gating is de asserted, what was the value of the CLK. If the value of C does not equal the CLK when the circuit deactivates the clock-gating function, then the asynchronous sampling issue appears for the G-DETFF. 3.2 Asynchronous Sampling in Low-Power Double-Edge Triggered State Retention Scan Flip-Flop (DET_SRSFF) [6] The DET_SRSFF circuit is based on a prior art low power overhead level- sensitive scan mechanism. It is composed of a pulse generator, static latch and LFB (leakage feedback) to reduce leakage current. If there is a pulse during the latch mode when D=1, Q changes from 0 to 1. A pulse generator has been used to attain the double edge triggered capability and to integrate the clock-gating feature. The circuit operates normally for CG=0. Clock edges are detected using pulse generator by connecting a delay element with an XOR gate. This helps in generating a positive pulse for each clock edge. Asynchronous data transition occurs in DET_SRSFF, when there is an input change while CLK equals 0. Because when there is a change in the input, clock signal is made inactive (de-asserted). Hence in DET_SRSFF, asynchronous data transition can be observed when there is an input change before a rising edge. DET_SRSFF has no problem related to asynchronous sampling when input does not change or when changes before a falling edge. However, when input changes before a rising edge, an asynchronous pulse will be generated as soon as the gating signal is de-asserted. This unwanted pulse triggers the flip flop between clock edges where that output data signal should be held and is observed at before rising edge. 3.3 Asynchronous Sampling in the Double Edge-Triggered Half-Static Clock-Gated D-Type Flip-Flop (DHSCGFF) [7] In DHSCGFF, two flip-flops and a multiplexer are used. On comparing the value of D and Q, a clock gating signal is generated to control the signal path of the global clock to the internal clock. The clock gating signal named as R is generated by comparing the value of input D and output Q. There are two master latches and a slave latch. The upper path (Master latch 1) transmits data only on the falling edge of Clock signal, while the lower path (Master latch 2) transmits data on the rising edge of C lock signal. The actual sizes of transistors of master latch 2 can be Tam s size, balanced size, Modified 1 and Modified 2. R stays 0 when gated (inactive). So if the input data changed when CLK =0, then the value of C will change to 1 immediately, and C will follow as the complement of C. An asynchronous clock edge of C triggers the flip-flop, causing the asynchronous data sampling. After each data transition, the gated signal C goes back to 0 and stays low until the next transition.

3 METHODS TO AVOID ASYNCHRONOUS DATA SAMPLING In order to avoid asynchronous data transition in C two schemes were introduced [8]. 4.1 SCHEME 1 When the gating signal is de-asserted, connection establishes between CLK and C only when CLK=C, hence avoiding asynchronous data transition in C. In scheme1 CLK signal is controlled by comparing D and Q. If D has changed since the last clock transition and is different from Q, then CLK will pass to the second comparator to compare with the C. This CLK & C comparator controls the switch T2 between the C and CLK. The second comparator prevents the asynchronous sampling. Asynchronous sampling occurs when D changes when CLK differs from C. However, with the second CLK & C comparator, the switch T2 will stay OFF when CLK C and C will synchronize with CLK. Fig.2. Scheme SCHEME 2 In Scheme 2 also the asynchronous sampling is avoided by the asynchronous data transition in C. The C normally stays at 0. When D changes while the CLK is 1 transistor P2, the one closer to CLK, will be turned OFF immediately and C will remain the same. When CLK goes back to 0 (a falling edge), P2 is ON and because of the delay element, P1 will stay ON for the time needed to trigger the flip-flop. Here in both the schemes a transmission gate based double edge triggered flip flop (T_DETFF) [7] has been used. Fig.3: Scheme 2 5. PROPOSED DESIGN In the proposed design, the transmission gate based DETFF (T_DETFF) in the existing design has been replaced by another modified DETFF. Since, DETFF s are edge sensitive devices; data can be latched on anyone of the clock edges. Though several contributions have been made to design DETFF s, there arises certain circumstance to reduce the power consumption of DETFF s further. A high performance DETFF proposed shown in Fig 3 consumes less power and area than the other designs and will be more suitable for high performance applications. Fig.4. S-EDIT view of Modified DETFF

4 1349 In the proposed design, the modified DETFF shown above is inserted in the place of transmission gate based DETFF (T_DETFF). In the modified scheme1, CLK signal is controlled by comparing D and Q. If D has changed since the last clock transition and is different from Q, then CLK will pass to the second comparator to compare with the C and is shown in Fig 5. For modified scheme 2, C normally stays at 0. When D changes while the CLK is 1 transistor P2, the one closer to CLK, will be turned OFF immediately and C will remain the same. When CLK goes back to 0 (a falling edge), P2 is ON and because of the delay element, P1 will stay ON for the time needed to trigger the flip-flop and it is shown in Fig 6. Fig.5. S-EDIT view of Proposed Modified Scheme 1 Fig.6. S-EDIT view of Proposed Modified Scheme 2 Instead of using T_DETFF the proposed modified DETFF is used. The modified DETFF proved to be very power efficient and area efficient. 5. CIRCUIT SIMULATION, ANALYSIS AND COMPARISON The simulation results of G_DETFF, DHSCGFF, DET_SRSFF, Scheme1, Scheme 2 and the proposed designs are shown along with their waveforms. Simulation has been done using Tanner tool (S-EDIT) and the power results are shown. Power comparison of the existing and proposed DET flip-flop s are tabulated and shown. Fig.7. Waveform of Gated DETFF (G_DETFF) The output of G_DETFF shows the existence of the asynchronous sampling issue within the design. Two asynchronous transitions occurred (circled in the figure), where D changes when CLK C.

5 1350 Fig.8. Waveform of DET_SRFF From the output waveform of figure 8, it is observed that DET_SRFF design when input D changes before a rising edge, an asynchronous pulse will be generated as soon as the gating signal is de asserted. This extra pulse leads to the asynchronous transition that causes the timing issue within the clock-gated double edge triggered flip-flop. The DHSCGFF can be implemented as tam s size, balanced size, modified 1 and modified 2. According to the analysis of Tam s circuit, those asynchronous transitions should occur when CLK=0 (before the rising edge) for all input data transitions. The asynchronous transitions for Tam s circuit could fully appear (i.e., show both cases), partially appear (i.e., only one case is observed) or be hidden. In balanced sized DHSCGFF the circuit has a similar rise and fall time. In this case, one asynchronous transition appears. In Modified I the circuit demonstrates that both possible asynchronous transitions can appear. Fig.9. Waveform of DHSCGFF (Tam s size) For each waveform of scheme 1 and scheme 2, signals are placed according to the event timeline from top to bottom. For each simulation, four data switching cases have been tested respectively, from left to right: 1) D changes from 1 to 0 before a falling edge; 2) D changes from 0 to 1 before a rising edge; 3) D changes from 1 to 0 before a rising edge; and 4) D changes from 0 to 1 before a falling edge. In these designs, the asynchronous transitions have been removed but area, power and delay is consumed more. Fig.10. Waveform of Scheme 1 Fig.11.Waveform of Scheme 2

6 1351 The proposed modified DETFF is used instead of transmission gate T_DETFF in proposed scheme 1 and scheme 2 implementation. The simulation results for both schemes are shown in figure 12 and figure 13. Fig.12. Waveform of proposed scheme 1 Fig.13. Waveform of proposed scheme 2 Type of Flip-Flop No.of Transistors Average Power (Watts) Delay (Seconds) G_DETFF DHSCGFF DET_SRSFF SCHEME SCHEME PROPOSED SCHEME PROPOSED SCHEME Table 2. Comparisons of Existing and Proposed Designs No. of Transistors Average Power (Watts) SCHEME 1 SCHEME 2 PROPOSED SCHEME 1 PROPOSED SCHEME 2 Fig.14. Comparison Graph From the table it is clear that proposed scheme 2 consumes low average power and less transistor count compared to all other designs. The delay is also reduced compared to previous designs. The graph shown denotes the power and area analysis of the proposed and existing designs. On comparing with the existing designs, the proposed design consumes low power, less delay and occupies less area.

7 1352 CONCLUSIONS Due to high demand of power efficient mobile devices, various power reduction techniques have been emerged. When used separately, the DETFFs has proved to be very efficient flip-flop design in reducing power but when used or integrated with clock gating technique data miss-communication errors occurs due to asynchronous data sampling. In order to eradicate this problem several solutions have been suggested and two simple approaches were introduced to reduce the power consumed in DETFF s by eliminating the asynchronous data sampling issue. In order to reduce the power consumption further, a new design has been proposed and based on that, two designs were implemented using Tanner EDA tool. REFERENCES [1] C.-C. Yu, Low-power double edge-triggered flip-flop circuit design, in Proc. Int. Conf. Innovative Computing Information and Control (ICICIC), 2008, p [2] Hossain, L. Wronski, and A. Albicki, Low power design using double edge triggered flip-flops, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 2, no. 2, pp ,1994. [3] A. G. M. Strollo, E. Napoli, and C. Cimino, Analysis of power dissipation in double edge-triggered flipflops, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 8, no. 5, pp , Oct [4] Y. Xia and A. E. A. Almaini, Differential CMOS edge-triggered flip-flop with clock-gating, Electron. Lett., vol. 38, no. 1, pp. 9 11,2002. [5] A. Datta and M. Saint-Laurent, A low-power clock gating cell optimized for low-voltage operation in a 45- nm technology, in ACM/IEEE Int. Symp. Low-Power Electronics and Design (ISLPED), 2010, pp [6] H. Karimiyan, S. M. Sayedi, and H. Saidi, Low-power dual-edge triggered state retention scan flip-flop, IET Comput. & Dig.Techniques, vol. 4, no. 5, pp , [7] W.-S. Tam, S.-L. Siu, C.-W. Kok, and H. Wong, Double edge-triggered half-static clock-gated D-type flipflop, in Proc. IEEE Int. Conf. Electron Devices and Solid- State Circuits (EDSSC), 2010, pp [8] Asynchronous Data Sampling Within Clock-Gated Double Edge-Triggered Flip-Flops Xiaowen Wang, Student Member, IEEE, and William H. Robinson, Senior Member, IEEE, September2013