Chapter 7 Registers and Register Transfers

Size: px
Start display at page:

Download "Chapter 7 Registers and Register Transfers"

Transcription

1 Logic ad Computer Desig Fudametals Chapter 7 Registers ad Register Trasfers Part 2 Couters, Register Cells, Buses, & Serial Operatios Charles Kime & Thomas Kamiski 28 Pearso Educatio, Ic (Hyperliks are active i View Show mode) Overview Part Registers, Microoperatios ad Implemetatios Part 2 Couters, register cells, buses, & serial operatios Microoperatios o sigle register (cotiued) Couters Register cell desig Multiplexer ad bus-based trasfers for multiple registers Serial trasfers ad microoperatios Part 3 Cotrol of Register Trasfers Chapter 7 - Part 2 2

2 Couters Couters are sequetial circuits which "cout" through a specific state sequece They ca cout up, cout dow, or cout through other fixed sequeces Two distict types are i commo usage: Ripple Couters Clock coected to the flip-flop clock iput o the LSB bit flipflop For all other bits, a flip-flop output is coected to the clock iput, thus circuit is ot truly sychroous! Output chage is delayed more for each bit toward the MSB Resurget because of low power cosumptio Sychroous Couters Clock is directly coected to the flip-flop clock iputs Logic is used to implemet the desired state sequecig Chapter 7 - Part 2 3 Ripple Couter How does it work? D A Whe there is a positive edge o the clock iput of A, A complemets Clock C R The clock iput for flipflop D B B is the complemeted C R output of flip-flop A Reset Whe flip A chages from to, there is a positive edge o the clock iput of B CP A causig B to B complemet 2 3 Chapter 7 - Part 2 2

3 Ripple Couter (cotiued) The arrows show the cause-effect relatioship from the prior slide => The correspodig CP A B sequece of states => 2 3 (B,A) = (,), (,), (,), (,), (,), (,), Each additioal bit, C, D, behaves like bit B, chagig half as frequetly as the bit before it For 3 bits: (C,B,A) = (,,), (,,), (,,), (,,), (,,), (,,), (,,), (,,), (,,), Chapter 7 - Part 2 5 Ripple Couter (cotiued) These circuits are called ripple couters because each edge sesitive trasitio (positive i the example) causes a chage i the ext flip-flop s state The chages ripple upward through the chai of flip-flops, i e, each trasitio occurs after a clock-to-output delay from the stage before To see this effect i detail look at the waveforms o the ext slide Chapter 7 - Part 2 6 3

4 Ripple Couter (cotiued) Startig with C = B = A =, equivalet to (C,B,A) = 7 base, the ext clock icremets the cout to (C,B,A) = base I fie timig detail: t The clock to output delay PHL CP t PHL causes a icreasig delay from clock edge for t PHL A each stage trasitio Thus, the cout ripples t phl from least to most B sigificat bit C For bits, total worst case delay is t PHL Chapter 7 - Part 2 7 Sychroous Couters To elimiate the "ripple" effects, use a commo clock for each flip-flop ad a combiatioal circuit to geerate the ext state For a up-couter, use a icremeter => Icremeter Clock A3 A2 A A S3 S2 S S D3 D2 D D Q3 Q2 Q Q Chapter 7 - Part 2 8

5 Sychroous Couters (cotiued) Iteral details => Icremeter Iteral Logic XOR complemets each bit AND chai causes complemet of a bit if all bits toward LSB from it equal Cout Eable Forces all outputs of AND chai to to hold the state Carry Out Added as part of icremeter Coect to Cout Eable of additioal -bit couters to form larger couters Cout eable EN Clock D C D C D C D C Q Q Q 2 Q 3 Carry output CO (a) Logic Diagram-Serial Gatig Chapter 7 - Part 2 9 Sychroous Couters (cotiued) Carry chai series of AND gates through which the carry ripples Yields log path delays Called serial gatig Replace AND carry chai with ANDs => i parallel Reduces path delays Called parallel gatig Like carry lookahead Lookahead ca be used o COs ad ENs to prevet log paths i large couters Symbol for Sychroous Couter CTR EN Q Q Q 2 Q 3 CO Symbol EN Q Q C Q 2 C 2 Q 3 C 3 CO Logic Diagram-Parallel Gatig Chapter 7 - Part 2 5

6 Other Couters See text for: Dow Couter - couts dowward istead of upward Up-Dow Couter - couts up or dow depedig o value a cotrol iput such as Up/Dow Parallel Couter - Has parallel load of values available depedig o cotrol iput such as Divide-by- (Modulo ) Couter Cout is remaider of divisio by ; may ot be a power of 2 or Cout is arbitrary sequece of states specifically desiged state-by-state Icludes modulo which is the BCD couter Chapter 7 - Part 2 Couter with Parallel Add path for iput data eabled for = Add logic to: Cout D D C Q disable cout logic for = disable feedback from outputs for = eable cout logic for = ad Cout = The resultig fuctio table: D D 2 D C D Q Q 2 Cout Actio C Hold Stored Value Cout Up Stored Value D 3 D Q 3 X D C Clock Carry Output CO Chapter 7 - Part 2 2 6

7 Desig Example: Sychroous BCD Use the sequetial logic model to desig a sychroous BCD couter with D flip-flops State Table => Iput combiatios through are do t cares Curret State Q8 Q Q2 Q Next State Q8 Q Q2 Q Chapter 7 - Part 2 3 Sychroous BCD (cotiued) Use K-Maps to two-level optimize the ext state equatios ad maipulate ito forms cotaiig XOR gates: D = Q D2 = Q2 + QQ8 D = Q + QQ2 D8 = Q8 + (QQ8 + QQ2Q) The logic diagram ca be draw from these equatios A asychroous or sychroous reset should be added What happes if the couter is perturbed by a power disturbace or other iterferece ad it eters a state other tha through? Chapter 7 - Part 2 7

8 Sychroous BCD (cotiued) Fid the actual values of the six ext states for the do t care combiatios from the equatios Fid the overall state diagram to assess behavior for the do t care states (states i decimal) Preset State Next State 9 Q8 Q Q2 Q Q8 Q Q2 Q Chapter 7 - Part 2 5 Sychroous BCD (cotiued) For the BCD couter desig, if a ivalid state is etered, retur to a valid state occurs withi two clock cycles Is this adequate? If ot: Is a sigal eeded that idicates that a ivalid state has bee etered? What is the equatio for such a sigal? Does the desig eed to be modified to retur from a ivalid state to a valid state i oe clock cycle? Does the desig eed to be modified to retur from a ivalid state to a specific state (such as )? The actio to be take depeds o: the applicatio of the circuit desig group policy See pages 2 of the text Chapter 7 - Part 2 6 8

9 Coutig Modulo N The followig techiques use a -bit biary couter with asychroous or sychroous clear ad/or parallel load: Detect a termial cout of N i a Modulo-N cout sequece to asychroously Clear the cout to or asychroously i value (These lead to couts which are preset for oly a very short time ad ca fail to work for some timig coditios!) Detect a termial cout of N - i a Modulo-N cout sequece to Clear the cout sychroously to Detect a termial cout of N - i a Modulo-N cout sequece to sychroously i value Detect a termial cout ad use to preset a cout of the termial cout value mius (N - ) Alteratively, custom desig a modulo N couter as doe for BCD Chapter 7 - Part 2 7 Coutig Modulo 7: Detect 7 ad Asychroously Clear A sychroous -bit biary couter with a asychroous Clear is used to make a Modulo 7 couter Use the Clear feature to detect the cout 7 ad clear the cout to This gives a cout of,, 2, 3,, 5, 6, 7(short),, 2, 3,, 5, 6, 7(short), etc Clock DON T DO THIS! Existece of state 7 may ot be log eough to reliably reset all flip-flops to Referred to as a suicide couter! (Cout 7 is killed, but the desiger s job may be dead as well!) D3 D2 D D Q3 Q2 Q Q CP LOAD CLEAR Chapter 7 - Part 2 8 9

10 Coutig Modulo 7: Sychroously o Termial Cout of 6 A sychroous -bit biary couter with a sychroous load ad a asychroous clear is used to make a Modulo 7 couter Use the feature to detect the cout "6" ad load i "zero" This gives a cout of,, 2, 3,, 5, 6,,, 2, 3,, 5, 6,, Usig do t cares for states Clock Reset above, detectio of 6 ca be doe with = Q Q2 D3 Q3 D2 Q2 D Q D Q CP LOAD CLEAR Chapter 7 - Part 2 9 Coutig Modulo 6: Sychroously Preset 9 o Reset ad 9 o Termial Cout A sychroous, -bit biary couter with a sychroous is to be used to make a Modulo 6 couter Use the feature to preset the cout to 9 o Reset ad detectio of Reset cout Clock D3 Q3 D2 Q2 D Q D Q CP LOAD CLEAR This gives a cout of 9,,, 2, 3,, 9,,, 2, 3,, 9, If the termial cout is 5 detectio is usually built i as Carry Out (CO) Chapter 7 - Part 2 2

11 Register Cell Desig Assume that a register cosists of idetical cells The register desig ca be approached as follows: Desig represetative cell for the register Coect copies of the cell together to form the register Applyig appropriate boudary coditios to cells that eed to be differet ad cotract if appropriate Register cell desig is the first step of the above process Chapter 7 - Part 2 2 Register Cell Specificatios A register Data iputs to the register Cotrol iput combiatios to the register Example : Not ecoded Cotrol iputs:, Shift, Add At most, oe of, Shift, Add is for ay clock cycle (,,), (,,), (,,), (,,) Example 2: Ecoded Cotrol iputs: S, S All possible biary combiatios o S, S (,), (,), (,), (,) Chapter 7 - Part 2 22

12 Register Cell Specificatios A set of register fuctios (typically specified as register trasfers) Example: : A B Shift: A sr B Add: A A + B A hold state specificatio Example: Cotrol iputs:, Shift, Add If all cotrol iputs are, hold the curret register state Chapter 7 - Part 2 23 Multiplexer Approach Uses a -iput multiplexer with a variety of trasfer sources ad fuctios K K Dedicated logic Ecoder Dedicated logic k Registers or shared logic S m S MUX k k R Chapter 7 - Part 2 2 2

13 Multiplexer Approach eable by OR of cotrol sigals K, K, K - - assumes o load for Use: Ecoder + Multiplexer (show) or x 2 AND-OR to select sources ad/or trasfer fuctios K K Dedicated logic Ecoder Dedicated logic k Registers or shared logic S m S MUX k k R Chapter 7 - Part 2 25 Example : Register Cell Desig Register A (m-bits) Specificatio: Data iput: B Cotrol iputs (CX, CY) Cotrol iput combiatios (,), (,) (,) Register trasfers: CX: A B v A CY :A B + A Hold state: (,) Chapter 7 - Part

14 Example : Register Cell Desig (cotiued) Cotrol = CX + CY Sice all cotrol combiatios appear as if ecoded (,), (,), (,) ca use multiplexer without ecoder: S = CX S = CY D = A i Hold A D = A i B i + A i CY = D2 = A i B i v A i CX = Note that the decoder part of the 3-iput multiplexer ca be shared betwee bits if desired Chapter 7 - Part 2 27 Sequetial Circuit Desig Approach Fid a state diagram or state table Note that there are oly two states with the state assigmet equal to the register cell output value Use the desig procedure i Chapter 5 to complete the cell desig For optimizatio: Use K-maps for up to to 6 variables Otherwise, use computer-aided or maual optimizatio Chapter 7 - Part 2 28

15 Example Agai State Table: A i Hold CX = CY = CX = B i = Ai v Bi CX = B i = Ai + Bi CY = CY = B i = B i = Four variables give a total of 6 state table etries By usig: Combiatios of variable ames ad values Do t care coditios (for CX = CY = ) oly 8 etries are required to represet the 6 etries Chapter 7 - Part 2 29 Example Agai (cotiued) K-map - Use variable orderig CX, CY, A i B i ad assume a D flip-flop D i A i CX X X B i X X CY Chapter 7 - Part 2 3 5

16 Example Agai (cotiued) The resultig SOP equatio: D i = CX B i + CY A i B i + A i B i + CY A i Usig factorig ad DeMorga s law: D i = CX B i + A i (CY B i ) + A i (CY B i ) D i = CX B i + A i + (CY B i ) The gate iput cost per cell = = The gate iput cost per cell for the previous versio is: Per cell: 9 Shared decoder logic: 8 Cost gai by sequetial desig > 5 per cell Also, o Eable o the flip-flop makes it cost less Chapter 7 - Part 2 3 Multiplexer ad Bus-Based Trasfers for Multiple Registers Multiplexer dedicated to each register Shared trasfer paths for registers A shared trasfer object is a called a bus (Plural: buses) Bus implemetatio usig: multiplexers three-state odes ad drivers I most cases, the umber of bits is the legth of the receivig register Chapter 7 - Part

17 Dedicated MUX-Based Trasfers Multiplexer coected to each register iput produces a very flexible trasfer structure => S S MUX S L R L Characterize the simultaeous trasfers possible with this structure S MUX S2 R L2 S MUX R2 Chapter 7 - Part 2 33 Multiplexer Bus A sigle bus drive by a multiplexer lowers cost, but limits the available trasfers => Characterize the simultaeous trasfers possible with this structure Characterize the cost savigs compared to dedicated multiplexers S S S S MUX 2 L R L R L2 R2 Chapter 7 - Part 2 3 7

18 Three-State Bus The 3-iput MUX ca be replaced by a 3-state ode (bus) ad 3-state buffers Cost is further reduced, but trasfers are limited Characterize the simultaeous trasfers possible with this structure Characterize the cost savigs ad compare Other advatages? E E L R L R L2 R2 E2 Chapter 7 - Part 2 35 Serial Trasfers ad Microoperatios Serial Trasfers Used for arrow trasfer paths Example : Telephoe or cable lie Parallel-to-Serial coversio at source Serial-to-Parallel coversio at destiatio Example 2: Iitializatio ad Capture of the cotets of may flip-flops for test purposes Add shift fuctio to all flip-flops ad form large shift register Use shiftig for simultaeous Iitializatio ad Capture operatios Serial microoperatios Example : Additio Example 2: Error-Correctio for CDs Chapter 7 - Part

19 Serial Microoperatios By usig two shift registers for operads, a full adder, ad a flip flop (for the carry), we ca add two umbers serially, startig at the least sigificat bit Serial additio is a low cost way to add large umbers of operads, sice a tree of full adder cells ca be made to ay depth, ad each ew level doubles the umber of operads Other operatios ca be performed serially as well, such as parity geeratio/checkig or more complex error-check codes Shiftig a biary umber left is equivalet to multiplyig by 2 Shiftig a biary umber right is equivalet to dividig by 2 Chapter 7 - Part 2 37 Serial Adder The circuit show uses two shift registers for operads A(3:) ad B(3:) A full adder, ad oe more flip flop (for the carry) is used to compute the sum The result is stored i the A register ad the fial carry i the flip-flop Serial I Serial I /Right Shift Registers A3 A2 A A Parallel B3 B2 B B Parallel A FA B Sum Ci Cout Q D (Clock ad /Shift Cotrol ot show) With the operads ad the result i shift registers, a tree of full adders ca be used to add a large umber of operads Used as a commo digital sigal processig techique CP Chapter 7 - Part

20 Terms of Use All (or portios) of this material 28 by Pearso Educatio, Ic Permissio is give to icorporate this material or adaptatios thereof ito classroom presetatios ad hadouts to istructors i courses adoptig the latest editio of Logic ad Computer Desig Fudametals as the course textbook These materials or adaptatios thereof are ot to be sold or otherwise offered for cosideratio This Terms of Use slide or page is to be icluded withi the origial materials or ay adaptatios thereof Chapter 7 - Part

Read Only Memory (ROM)

Read Only Memory (ROM) ECE 545 igital System esig with VHL Lecture A igital Logic Reresher Part A Combiatioal Logic Buildig Blocks Cot. Problem 2 What is a size o ROM with a 4-bit address iput ad a 8-bit data output? What is

More information

Logic and Computer Design Fundamentals. Chapter 7. Registers and Counters

Logic and Computer Design Fundamentals. Chapter 7. Registers and Counters Logic and Computer Design Fundamentals Chapter 7 Registers and Counters Registers Register a collection of binary storage elements In theory, a register is sequential logic which can be defined by a state

More information

EE260: Digital Design, Spring /3/18. n Combinational Logic: n Output depends only on current input. n Require cascading of many structures

EE260: Digital Design, Spring /3/18. n Combinational Logic: n Output depends only on current input. n Require cascading of many structures EE260: igital esig, prig 208 4/3/8 EE 260: Itroductio to igital esig equetial Logic Elemets ao Zheg epartmet of Electrical Egieerig Uiversity of Hawaiʻi at Māoa equetial ircuits ombiatioal Logic: Output

More information

DIGITAL SYSTEM DESIGN

DIGITAL SYSTEM DESIGN DIGITAL SYSTEM DESIGN Buildig Block Circuit Rather tha buildig ytem at the gate level, ofte digital ytem are cotructed from higher level, but till baic, buildig block circuit. Multiplexer, decoder, flip-flop,

More information

Logistics We are here. If you cannot login to MarkUs, me your UTORID and name.

Logistics We are here. If you cannot login to MarkUs,  me your UTORID and name. Logistics We are here 8 Week If you caot logi to arkus, email me your UTORID ad ame. heck lab marks o arkus, if it s recorded wrog, cotact Larry withi a week after the lab. Quiz average: 8% Assembly Laguage

More information

Image Intensifier Reference Manual

Image Intensifier Reference Manual Image Itesifier Referece Maual Improvisio, Viscout Cetre II, Uiversity of Warwick Sciece Park, Millbur Hill Road, Covetry. CV4 7HS Tel: 0044 (0) 24 7669 2229 Fax: 0044 (0) 24 7669 0091 e-mail: admi@improvisio.com

More information

Registers, Register Transfers and Counters Dr. Fethullah Karabiber

Registers, Register Transfers and Counters Dr. Fethullah Karabiber 36 OMPUTER HARWARE Registers, Register Transfers and ounters r. Fethullah Karabiber Overview 2 Registers, Microoperations and Implementations Registers and load enable Register transfer operations Microoperations

More information

Polychrome Devices Reference Manual

Polychrome Devices Reference Manual Polychrome Devices Referece Maual Improvisio, Viscout Cetre II, Uiversity of Warwick Sciece Park, Millbur Hill Road, Covetry. CV4 7HS Tel: 0044 (0) 24 7669 2229 Fax: 0044 (0) 24 7669 0091 e-mail: admi@improvisio.com

More information

Chapter 3 Unit Combinational

Chapter 3 Unit Combinational EE 200: Digital Logic Circuit Design Dr Radwan E Abdel-Aal, COE Logic and Computer Design Fundamentals Chapter 3 Unit Combinational 5 Registers Logic and Design Counters Part Implementation Technology

More information

ELEN Electronique numérique

ELEN Electronique numérique ELEN0040 - Electronique numérique Patricia ROUSSEAUX Année académique 2014-2015 CHAPITRE 6 Registers and Counters ELEN0040 6-277 Design of a modulo-8 binary counter using JK Flip-flops 3 bits are required

More information

Advanced Devices. Registers Counters Multiplexers Decoders Adders. CSC258 Lecture Slides Steve Engels, 2006 Slide 1 of 20

Advanced Devices. Registers Counters Multiplexers Decoders Adders. CSC258 Lecture Slides Steve Engels, 2006 Slide 1 of 20 Advanced Devices Using a combination of gates and flip-flops, we can construct more sophisticated logical devices. These devices, while more complex, are still considered fundamental to basic logic design.

More information

Line numbering and synchronization in digital HDTV systems

Line numbering and synchronization in digital HDTV systems Lie umberig ad sychroizatio i digital HDTV systems D. (VURT) I cotrast to aalogue televisio systems where lie umberig is covetioally liked to the vertical sychroizatio, digital televisio offers the possibility

More information

Working with PlasmaWipe Effects

Working with PlasmaWipe Effects Workig with PlasmaWipe Effects Workig with PlasmaWipe Effects PlasmaWipe effects are real-time plug-i effects that use gradiet image bitmaps to create wipes ad segmet effects. There are 64 preset effects,

More information

Quality improvement in measurement channel including of ADC under operation conditions

Quality improvement in measurement channel including of ADC under operation conditions Quality improvemet i measuremet chael icludig of ADC uder operatio coditios 1 Romuald MASNICKI, 2 Jausz MINDYKOWSKI 1, 2 Gdyia Maritime iversity, ul. Morska 81-83, 81-225 Gdyia, POLAND, tel. (+48 58) 6109

More information

Energy-Efficient FPGA-Based Parallel Quasi-Stochastic Computing

Energy-Efficient FPGA-Based Parallel Quasi-Stochastic Computing Article Eergy-Efficiet FPGA-Based Parallel Quasi-Stochastic Computig Ramu Seva, Prashathi Metku * ad Misu Choi Departmet of Computer Egieerig, Missouri Uiversity of Sciece & Techology, 4 Emerso Electric

More information

MODULE 3. Combinational & Sequential logic

MODULE 3. Combinational & Sequential logic MODULE 3 Combinational & Sequential logic Combinational Logic Introduction Logic circuit may be classified into two categories. Combinational logic circuits 2. Sequential logic circuits A combinational

More information

UNIVERSITI TEKNOLOGI MALAYSIA

UNIVERSITI TEKNOLOGI MALAYSIA SULIT Faculty of Computing UNIVERSITI TEKNOLOGI MALAYSIA FINAL EXAMINATION SEMESTER I, 2016 / 2017 SUBJECT CODE : SUBJECT NAME : SECTION : TIME : DATE/DAY : VENUES : INSTRUCTIONS : Answer all questions

More information

L-CBF: A Low-Power, Fast Counting Bloom Filter Architecture

L-CBF: A Low-Power, Fast Counting Bloom Filter Architecture L-CBF: A Low-Power, Fast Coutig Bloom Filter Architecture Elham Safi, Adreas Moshovos, ad Adreas Veeris Electrical ad Computer Egieerig Departmet Uiversity of Toroto {elham, moshovos, veeris@eecg.utoroto.ca}

More information

CODE GENERATION FOR WIDEBAND CDMA

CODE GENERATION FOR WIDEBAND CDMA ST JOURAL OF SYSTEM RESEARCH - VOL1 - UMBER 1 CODE GEERATIO FOR WIDEBAD CDMA Daiele Lo Iacoo Ettore Messia Giuseppe Avelloe Agostio Galluzzo Fracesco Pappalardo STMicroelectroics This paper presets a overview

More information

CHAPTER 4: Logic Circuits

CHAPTER 4: Logic Circuits CHAPTER 4: Logic Circuits II. Sequential Circuits Combinational circuits o The outputs depend only on the current input values o It uses only logic gates, decoders, multiplexers, ALUs Sequential circuits

More information

CHAPTER 4: Logic Circuits

CHAPTER 4: Logic Circuits CHAPTER 4: Logic Circuits II. Sequential Circuits Combinational circuits o The outputs depend only on the current input values o It uses only logic gates, decoders, multiplexers, ALUs Sequential circuits

More information

MODEL QUESTIONS WITH ANSWERS THIRD SEMESTER B.TECH DEGREE EXAMINATION DECEMBER CS 203: Switching Theory and Logic Design. Time: 3 Hrs Marks: 100

MODEL QUESTIONS WITH ANSWERS THIRD SEMESTER B.TECH DEGREE EXAMINATION DECEMBER CS 203: Switching Theory and Logic Design. Time: 3 Hrs Marks: 100 MODEL QUESTIONS WITH ANSWERS THIRD SEMESTER B.TECH DEGREE EXAMINATION DECEMBER 2016 CS 203: Switching Theory and Logic Design Time: 3 Hrs Marks: 100 PART A ( Answer All Questions Each carries 3 Marks )

More information

Decade Counters Mod-5 counter: Decade Counter:

Decade Counters Mod-5 counter: Decade Counter: Decade Counters We can design a decade counter using cascade of mod-5 and mod-2 counters. Mod-2 counter is just a single flip-flop with the two stable states as 0 and 1. Mod-5 counter: A typical mod-5

More information

1. Convert the decimal number to binary, octal, and hexadecimal.

1. Convert the decimal number to binary, octal, and hexadecimal. 1. Convert the decimal number 435.64 to binary, octal, and hexadecimal. 2. Part A. Convert the circuit below into NAND gates. Insert or remove inverters as necessary. Part B. What is the propagation delay

More information

Vignana Bharathi Institute of Technology UNIT 4 DLD

Vignana Bharathi Institute of Technology UNIT 4 DLD DLD UNIT IV Synchronous Sequential Circuits, Latches, Flip-flops, analysis of clocked sequential circuits, Registers, Shift registers, Ripple counters, Synchronous counters, other counters. Asynchronous

More information

Logic Design. Flip Flops, Registers and Counters

Logic Design. Flip Flops, Registers and Counters Logic Design Flip Flops, Registers and Counters Introduction Combinational circuits: value of each output depends only on the values of inputs Sequential Circuits: values of outputs depend on inputs and

More information

Organic Macromolecules and the Genetic Code A cell is mostly water.

Organic Macromolecules and the Genetic Code A cell is mostly water. Orgaic Macromolecules ad the Geetic Code A cell is mostly water. The rest of the cell cosists mostly of carbobased molecules. Orgaic chemistry is the study of carbo compouds. Copyright 2007 Pearso Educatio

More information

Manual RCA-1. Item no fold RailCom display. tams elektronik. n n n

Manual RCA-1. Item no fold RailCom display. tams elektronik. n n n Maual RCA-1 Item o. 45-02016 1-fold RailCom display Eglish RCA-1 Table of cotets 1. Gettig started...3 2. Safety istructios...5 3. Backgroud iformatio: RailCom...6 4. Operatig mode of the RCA-1...8 5.

More information

What Does it Take to Build a Complete Test Flow for 3-D IC?

What Does it Take to Build a Complete Test Flow for 3-D IC? What Does it Take to Build a Complete Test Flow for 3-D IC? Brio Keller, Bassilios Petrakis, Cadece Thaks to : Sadeep Goel, TSMC EDPS, Moterey, CA April 5-6, 202 Ackowledgemets TSMC Ashok Mehta imec Erik

More information

Chapter 2. Digital Circuits

Chapter 2. Digital Circuits Chapter 2. Digital Circuits Logic gates Flip-flops FF registers IC registers Data bus Encoders/Decoders Multiplexers Troubleshooting digital circuits Most contents of this chapter were covered in 88-217

More information

NIIT Logotype YOU MUST NEVER CREATE A NIIT LOGOTYPE THROUGH ANY SOFTWARE OR COMPUTER. THIS LOGO HAS BEEN DRAWN SPECIALLY.

NIIT Logotype YOU MUST NEVER CREATE A NIIT LOGOTYPE THROUGH ANY SOFTWARE OR COMPUTER. THIS LOGO HAS BEEN DRAWN SPECIALLY. NIIT Logotype The NIIT logotype is always preseted i a fixed cofiguratio. The desig of the logotype is based o a typeface called Egyptia. The letters N I I T has bee specially desiged ad letter-spaced.

More information

Principles of Computer Architecture. Appendix A: Digital Logic

Principles of Computer Architecture. Appendix A: Digital Logic A-1 Appendix A - Digital Logic Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic A-2 Appendix A - Digital Logic Chapter Contents A.1 Introduction A.2 Combinational

More information

MC9211 Computer Organization

MC9211 Computer Organization MC9211 Computer Organization Unit 2 : Combinational and Sequential Circuits Lesson2 : Sequential Circuits (KSB) (MCA) (2009-12/ODD) (2009-10/1 A&B) Coverage Lesson2 Outlines the formal procedures for the

More information

... clk. 10 Registers and counters

... clk. 10 Registers and counters igitl Logic/esig. L. 10 My 2, 2006 10 Registers d couters 10.1 Registers The simplest -bit register is collectio of flip-flops triggered by commo clock. I wou prefer to cll it just -bit flip-flop, sice

More information

Analogue Versus Digital [5 M]

Analogue Versus Digital [5 M] Q.1 a. Analogue Versus Digital [5 M] There are two basic ways of representing the numerical values of the various physical quantities with which we constantly deal in our day-to-day lives. One of the ways,

More information

NewBlot PVDF 5X Stripping Buffer

NewBlot PVDF 5X Stripping Buffer NewBlot PVDF 5X Strippig Buffer Developed for: Odyssey Family of Imagers Please refer to your maual to cofirm that this protocol is appropriate for the applicatios compatible with your model of Odyssey

More information

Chapter 4. Logic Design

Chapter 4. Logic Design Chapter 4 Logic Design 4.1 Introduction. In previous Chapter we studied gates and combinational circuits, which made by gates (AND, OR, NOT etc.). That can be represented by circuit diagram, truth table

More information

PowerStrip Automatic Cut & Strip Machine

PowerStrip Automatic Cut & Strip Machine Automatic Cut & Strip Machie 2 Fully automatic wire processig requires precisio techology tailored to your specific eeds. The combies the utmost i precisio ad performace which cover a ubeatable rage of

More information

Computer Architecture and Organization

Computer Architecture and Organization A-1 Appendix A - Digital Logic Computer Architecture and Organization Miles Murdocca and Vincent Heuring Appendix A Digital Logic A-2 Appendix A - Digital Logic Chapter Contents A.1 Introduction A.2 Combinational

More information

UNIT-3: SEQUENTIAL LOGIC CIRCUITS

UNIT-3: SEQUENTIAL LOGIC CIRCUITS UNIT-3: SEQUENTIAL LOGIC CIRCUITS STRUCTURE 3. Objectives 3. Introduction 3.2 Sequential Logic Circuits 3.2. NAND Latch 3.2.2 RS Flip-Flop 3.2.3 D Flip-Flop 3.2.4 JK Flip-Flop 3.2.5 Edge Triggered RS Flip-Flop

More information

Logic Design II (17.342) Spring Lecture Outline

Logic Design II (17.342) Spring Lecture Outline Logic Design II (17.342) Spring 2012 Lecture Outline Class # 03 February 09, 2012 Dohn Bowden 1 Today s Lecture Registers and Counters Chapter 12 2 Course Admin 3 Administrative Admin for tonight Syllabus

More information

Chapter 5 Sequential Circuits

Chapter 5 Sequential Circuits Logic and Computer Design Fundamentals Chapter 5 Sequential Circuits Part 2 Sequential Circuit Design Charles Kime & Thomas Kaminski 28 Pearson Education, Inc. (Hyperlinks are active in View Show mode)

More information

Counter dan Register

Counter dan Register Counter dan Register Introduction Circuits for counting events are frequently used in computers and other digital systems. Since a counter circuit must remember its past states, it has to possess memory.

More information

~~ 7/'1.J DATE COURSE OUTLINE PROGRAM: ELECTRONIC/ELECTRICAL/COMPUTER TECHNICIAN SEMESTER: DATE: JANUARY 1993 DATE

~~ 7/'1.J DATE COURSE OUTLINE PROGRAM: ELECTRONIC/ELECTRICAL/COMPUTER TECHNICIAN SEMESTER: DATE: JANUARY 1993 DATE SAULT COLLEGE OF APPLIED ARTS & TECHNOLOGY SAULT STE. MARIE, ONTARIO COURSE OUTLINE./ COURSE NAME: DIGITAL ELECTRONICS : ELN-1S7 PROGRAM: ELECTRONIC/ELECTRICAL/COMPUTER TECHNICIAN SEMESTER: TWO DATE: JANUARY

More information

Chapter Contents. Appendix A: Digital Logic. Some Definitions

Chapter Contents. Appendix A: Digital Logic. Some Definitions A- Appendix A - Digital Logic A-2 Appendix A - Digital Logic Chapter Contents Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic A. Introduction A.2 Combinational

More information

Logic Devices for Interfacing, The 8085 MPU Lecture 4

Logic Devices for Interfacing, The 8085 MPU Lecture 4 Logic Devices for Interfacing, The 8085 MPU Lecture 4 1 Logic Devices for Interfacing Tri-State devices Buffer Bidirectional Buffer Decoder Encoder D Flip Flop :Latch and Clocked 2 Tri-state Logic Outputs

More information

NH 67, Karur Trichy Highways, Puliyur C.F, Karur District UNIT-III SEQUENTIAL CIRCUITS

NH 67, Karur Trichy Highways, Puliyur C.F, Karur District UNIT-III SEQUENTIAL CIRCUITS NH 67, Karur Trichy Highways, Puliyur C.F, 639 114 Karur District DEPARTMENT OF ELETRONICS AND COMMUNICATION ENGINEERING COURSE NOTES SUBJECT: DIGITAL ELECTRONICS CLASS: II YEAR ECE SUBJECT CODE: EC2203

More information

Module -5 Sequential Logic Design

Module -5 Sequential Logic Design Module -5 Sequential Logic Design 5.1. Motivation: In digital circuit theory, sequential logic is a type of logic circuit whose output depends not only on the present value of its input signals but on

More information

Digital Fundamentals: A Systems Approach

Digital Fundamentals: A Systems Approach Digital Fundamentals: A Systems Approach Counters Chapter 8 A System: Digital Clock Digital Clock: Counter Logic Diagram Digital Clock: Hours Counter & Decoders Finite State Machines Moore machine: One

More information

STx. Compact HD/SD COFDM Transmitter. Features. Options. Accessories. Applications

STx. Compact HD/SD COFDM Transmitter. Features. Options. Accessories. Applications Compact HD/SD COFDM Trasmitter Features SD ad HD ecodig 200mW RF output power Optimized for size Superior broadcast grade video Wide selectio of video iputs MPEG-4 Part-10/H.264 Two moo audio chaels Very

More information

MODU LE DAY. Class-A, B, AB and C amplifiers - basic concepts, power, efficiency Basic concepts of Feedback and Oscillation. Day 1

MODU LE DAY. Class-A, B, AB and C amplifiers - basic concepts, power, efficiency Basic concepts of Feedback and Oscillation. Day 1 DAY MODU LE TOPIC QUESTIONS Day 1 Day 2 Day 3 Day 4 I Class-A, B, AB and C amplifiers - basic concepts, power, efficiency Basic concepts of Feedback and Oscillation Phase Shift Wein Bridge oscillators.

More information

EECS 270 Midterm 1 Exam Closed book portion Winter 2017

EECS 270 Midterm 1 Exam Closed book portion Winter 2017 EES 270 Midterm 1 Exam losed book portion Winter 2017 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. NOTES: 1. This part of

More information

CSC Computer Architecture and Organization

CSC Computer Architecture and Organization S 37 - omputer Architecture and Organization Lecture 6: Registers and ounters Registers A register is a group of flip-flops. Each flip-flop stores one bit of data; n flip-flops are required to store n

More information

WINTER 15 EXAMINATION Model Answer

WINTER 15 EXAMINATION Model Answer Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model answer and the answer written by candidate

More information

Counters

Counters Counters A counter is the most versatile and useful subsystems in the digital system. A counter driven by a clock can be used to count the number of clock cycles. Since clock pulses occur at known intervals,

More information

Asynchronous (Ripple) Counters

Asynchronous (Ripple) Counters Circuits for counting events are frequently used in computers and other digital systems. Since a counter circuit must remember its past states, it has to possess memory. The chapter about flip-flops introduced

More information

Slide 1. Flip-Flops. Cross-NOR SR flip-flop S R Q Q. hold reset set not used. Cross-NAND SR flip-flop S R Q Q. not used reset set hold 1 Q.

Slide 1. Flip-Flops. Cross-NOR SR flip-flop S R Q Q. hold reset set not used. Cross-NAND SR flip-flop S R Q Q. not used reset set hold 1 Q. Slide Flip-Flops Cross-NOR SR flip-flop Reset Set Cross-NAND SR flip-flop Reset Set S R reset set not used S R not used reset set 6.7 Digital ogic Slide 2 Clocked evel-triggered NAND SR Flip-Flop S R SR

More information

1. a) For the circuit shown in figure 1.1, draw a truth table showing the output Q for all combinations of inputs A, B and C. [4] Figure 1.

1. a) For the circuit shown in figure 1.1, draw a truth table showing the output Q for all combinations of inputs A, B and C. [4] Figure 1. [Question 1 is compulsory] 1. a) For the circuit shown in figure 1.1, draw a truth table showing the output Q for all combinations of inputs A, B and C. Figure 1.1 b) Minimize the following Boolean functions:

More information

Mullard INDUCTOR POT CORE EQUIVALENTS LIST. Mullard Limited, Mullard House, Torrington Place, London Wel 7HD. Telephone:

Mullard INDUCTOR POT CORE EQUIVALENTS LIST. Mullard Limited, Mullard House, Torrington Place, London Wel 7HD. Telephone: Mullard INDUCTOR POT CORE EQUIVALENTS LIST Mullard Limited, Mullard House, Torrigto Place, Lodo Wel 7HD. Telephoe: 01-580 6633 INDUCTOR POT CORE EQUIVALENTS LIST Mullard Limited have bee maufacturig ferrite

More information

Switching Theory And Logic Design UNIT-IV SEQUENTIAL LOGIC CIRCUITS

Switching Theory And Logic Design UNIT-IV SEQUENTIAL LOGIC CIRCUITS Switching Theory And Logic Design UNIT-IV SEQUENTIAL LOGIC CIRCUITS Sequential circuits Classification of sequential circuits: Sequential circuits may be classified as two types. 1. Synchronous sequential

More information

Long and Fast Up/Down Counters Pushpinder Kaur CHOUHAN 6 th Jan, 2003

Long and Fast Up/Down Counters Pushpinder Kaur CHOUHAN 6 th Jan, 2003 1 Introduction Long and Fast Up/Down Counters Pushpinder Kaur CHOUHAN 6 th Jan, 2003 Circuits for counting both forward and backward events are frequently used in computers and other digital systems. Digital

More information

Lecture 12. Amirali Baniasadi

Lecture 12. Amirali Baniasadi CENG 24 Digital Design Lecture 2 Amirali Baniasadi amirali@ece.uvic.ca This Lecture Chapter 6: Registers and Counters 2 Registers Sequential circuits are classified based in their function, e.g., registers.

More information

EECS 270 Midterm 2 Exam Closed book portion Fall 2014

EECS 270 Midterm 2 Exam Closed book portion Fall 2014 EECS 270 Midterm 2 Exam Closed book portion Fall 2014 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: Page # Points

More information

Voice Security Selection Guide

Voice Security Selection Guide Voice Security Selectio Guide Hoppig Code Voice Iversio with ANI Voice Security Frequecy Domai Split-bad Voice Iversio Double Iversio Radio Ecryptio Rollig Code Voice Scramblers Rollig Double Iversio Frequetly

More information

ELE2120 Digital Circuits and Systems. Tutorial Note 8

ELE2120 Digital Circuits and Systems. Tutorial Note 8 ELE2120 Digital Circuits and Systems Tutorial Note 8 Outline 1. Register 2. Counters 3. Synchronous Counter 4. Asynchronous Counter 5. Sequential Circuit Design Overview 1. Register Applications: temporally

More information

1. True/False Questions (10 x 1p each = 10p) (a) I forgot to write down my name and student ID number.

1. True/False Questions (10 x 1p each = 10p) (a) I forgot to write down my name and student ID number. CprE 281: Digital Logic Midterm 2: Friday Oct 30, 2015 Student Name: Student ID Number: Lab Section: Mon 9-12(N) Mon 12-3(P) Mon 5-8(R) Tue 11-2(U) (circle one) Tue 2-5(M) Wed 8-11(J) Wed 6-9(Y) Thur 11-2(Q)

More information

2 Specialty Application Photoelectric Sensors

2 Specialty Application Photoelectric Sensors SMARTEYE X-PRO XP10 XP10 -- Extremely High Speed Sesor 2 Specialty Applicatio Photoelectric Sesors 2-119 Specialty Applicatio Photoelectric Sesors 2 SMARTEYE X-PRO XP10 Extremely High Speed (10µs) Photoelectric

More information

RS flip-flop using NOR gate

RS flip-flop using NOR gate RS flip-flop using NOR gate Triggering and triggering methods Triggering : Applying train of pulses, to set or reset the memory cell is known as Triggering. Triggering methods:- There are basically two

More information

WINTER 14 EXAMINATION

WINTER 14 EXAMINATION Subject Code: 17320 WINTER 14 EXAMINATION Model Answer Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2)

More information

Apollo 360 Map Display User s Guide

Apollo 360 Map Display User s Guide Apollo 360 Map Display User s Guide II Morrow Ic. 2345 Turer Road S.E. Salem, Orego 97309 November 1996 P/N 560-0119-00 Apollo 360 Map Display No part of this documet may be reproduced i ay form or by

More information

Registers and Counters

Registers and Counters Registers and Counters A register is a group of flip-flops which share a common clock An n-bit register consists of a group of n flip-flops capable of storing n bits of binary information May have combinational

More information

UNIT III. Combinational Circuit- Block Diagram. Sequential Circuit- Block Diagram

UNIT III. Combinational Circuit- Block Diagram. Sequential Circuit- Block Diagram UNIT III INTRODUCTION In combinational logic circuits, the outputs at any instant of time depend only on the input signals present at that time. For a change in input, the output occurs immediately. Combinational

More information

Chapter 6 Registers and Counters

Chapter 6 Registers and Counters EEA051 - Digital Logic 數位邏輯 Chapter 6 Registers and Counters 吳俊興國立高雄大學資訊工程學系 January 2006 Chapter 6 Registers and Counters 6-1 Registers 6-2 Shift Registers 6-3 Ripple Counters 6-4 Synchronous Counters

More information

ASYNCHRONOUS COUNTER CIRCUITS

ASYNCHRONOUS COUNTER CIRCUITS ASYNCHRONOUS COUNTER CIRCUITS Asynchronous counters do not have a common clock that controls all the Hipflop stages. The control clock is input into the first stage, or the LSB stage of the counter. The

More information

9311 EN. DIGIFORCE X/Y monitoring. For monitoring press-fit, joining, rivet and caulking operations Series 9311 ±10V DMS.

9311 EN. DIGIFORCE X/Y monitoring. For monitoring press-fit, joining, rivet and caulking operations Series 9311 ±10V DMS. DIGIFORCE X/Y moitorig For moitorig press-fit, joiig, rivet ad caulkig operatios Series 9311 ±10V DMS Compatible sesors Piezo Poti Flexible Fieldbus itegratio by PROFIBUS, PROFINET or EtherNet/IP Automatic

More information

Switching Circuits & Logic Design, Fall Final Examination (1/13/2012, 3:30pm~5:20pm)

Switching Circuits & Logic Design, Fall Final Examination (1/13/2012, 3:30pm~5:20pm) Switching Circuits & Logic Design, Fall 2011 Final Examination (1/13/2012, 3:30pm~5:20pm) Problem 1: (15 points) Consider a new FF with three inputs, S, R, and T. No more than one of these inputs can be

More information

RS flip-flop using NOR gate

RS flip-flop using NOR gate RS flip-flop using NOR gate Triggering and triggering methods Triggering : Applying train of pulses, to set or reset the memory cell is known as Triggering. Triggering methods:- There are basically two

More information

Fall 2000 Chapter 5 Part 1

Fall 2000 Chapter 5 Part 1 ECE/CS 352 Digital Systems Fundamentals Fall 2000 Chapter 5 Part 1 Tom Kaminski & Charles R. Kime ECE/CS 352 Digital System Fundamentals T. Kaminski & C. Kime 1 Registers A register is a collection of

More information

DIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute

DIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 27.2.2. DIGITAL TECHNICS Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 6. LECTURE (ANALYSIS AND SYNTHESIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS) 26/27 6. LECTURE Analysis and

More information

Manual Industrial air curtain

Manual Industrial air curtain Maual Idustrial air curtai Model IdAC2 Versio 6.0 Origial Maual Eglish a INDUSTRIAL AIR CURTAIN... Cotets 1 Itroductio 4 1.1 About this maual 4 1.2 How to read this maual 4 1.3 About the uit 5 1.4 Compoets

More information

Sequential Digital Design. Laboratory Manual. Experiment #7. Counters

Sequential Digital Design. Laboratory Manual. Experiment #7. Counters The Islamic University of Gaza Engineering Faculty Department of Computer Engineering Spring 2018 ECOM 2022 Khaleel I. Shaheen Sequential Digital Design Laboratory Manual Experiment #7 Counters Objectives

More information

PROBABILITY AND STATISTICS Vol. I - Ergodic Properties of Stationary, Markov, and Regenerative Processes - Karl Grill

PROBABILITY AND STATISTICS Vol. I - Ergodic Properties of Stationary, Markov, and Regenerative Processes - Karl Grill PROBABILITY AND STATISTICS Vol. I Ergodic Properties of Statioary, Markov, ad Regeerative Processes Karl Grill ERGODIC PROPERTIES OF STATIONARY, MARKOV, AND REGENERATIVE PROCESSES Karl Grill Istitut für

More information

Midterm Exam 15 points total. March 28, 2011

Midterm Exam 15 points total. March 28, 2011 Midterm Exam 15 points total March 28, 2011 Part I Analytical Problems 1. (1.5 points) A. Convert to decimal, compare, and arrange in ascending order the following numbers encoded using various binary

More information

R13 SET - 1 '' ''' '' ' '''' Code No: RT21053

R13 SET - 1 '' ''' '' ' '''' Code No: RT21053 SET - 1 1. a) What are the characteristics of 2 s complement numbers? b) State the purpose of reducing the switching functions to minimal form. c) Define half adder. d) What are the basic operations in

More information

Review of digital electronics. Storage units Sequential circuits Counters Shifters

Review of digital electronics. Storage units Sequential circuits Counters Shifters Review of digital electronics Storage units Sequential circuits ounters Shifters ounting in Binary A counter can form the same pattern of 0 s and 1 s with logic levels. The first stage in the counter represents

More information

Scanned by CamScanner

Scanned by CamScanner NAVEEN RAJA VELCHURI DSD & Digital IC Applications Example: 2-bit asynchronous up counter: The 2-bit Asynchronous counter requires two flip-flops. Both flip-flop inputs are connected to logic 1, and initially

More information

Chapter 6. Flip-Flops and Simple Flip-Flop Applications

Chapter 6. Flip-Flops and Simple Flip-Flop Applications Chapter 6 Flip-Flops and Simple Flip-Flop Applications Basic bistable element It is a circuit having two stable conditions (states). It can be used to store binary symbols. J. C. Huang, 2004 Digital Logic

More information

Manual Comfort Air Curtain

Manual Comfort Air Curtain Maual Comfort Air Curtai Model SesAir Versio 1.0- North America Origial Maual Eglish a COMFORT AIR CURTAIN... Cotets 1 Itroductio 4 1.1 About this maual 4 1.2 How to read this maual 4 1.3 About the uit

More information

Registers and Counters

Registers and Counters Registers and Counters Clocked sequential circuit = F/Fs and combinational gates Register Group of flip-flops (share a common clock and capable of storing one bit of information) Consist of a group of

More information

Video Cassette Recorder

Video Cassette Recorder 3-865-427-12(1) Video Cassette Recorder Operatig Istructios SLV-L49 MX SLV-L52 PA/PC SLV-L59 CL/CS/PR/VZ SLV-X55 MX SLV-L69HF MX SLV-L72HF PA/PC SLV-L79HF CL/CS/VZ SLV-L89HF CL/CS/MX/VZ SLV-X66HF MX 1999

More information

CprE 281: Digital Logic

CprE 281: Digital Logic CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Registers and Counters CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev

More information

Asynchronous counters

Asynchronous counters Asynchronous counters In the previous section, we saw a circuit using one J-K flip-flop that counted backward in a two-bit binary sequence, from 11 to 10 to 01 to 00. Since it would be desirable to have

More information

Internet supported Analysis of MPEG Compressed Newsfeeds

Internet supported Analysis of MPEG Compressed Newsfeeds Proceedigs of the IASTED Iteratioal Coferece Iteret ad Multimedia Systems ad Applicatios October 18-21, 1999 Nassau, Bahamas Iteret supported Aalysis of MPEG Compressed Newsfeeds Guido FALKEMEIER, Gerhard

More information

,..,,.,. - z : i,; ;I.,i,,?-.. _.m,vi LJ

,..,,.,. - z : i,; ;I.,i,,?-.. _.m,vi LJ ,..,,.,. - z : i,; ;I.,i,,?-.. _.m,vi 5.. :. 5 LJ Page Itroductio 2 TalkTolO32 Set Keys... 3 Feature Descriptio... 4 Feature Selectio... 5 Feature Programmig... 6 System Programmig Chart... 7 Power Fail

More information

R13. II B. Tech I Semester Regular Examinations, Jan DIGITAL LOGIC DESIGN (Com. to CSE, IT) PART-A

R13. II B. Tech I Semester Regular Examinations, Jan DIGITAL LOGIC DESIGN (Com. to CSE, IT) PART-A SET - 1 Note: Question Paper consists of two parts (Part-A and Part-B) Answer ALL the question in Part-A Answer any THREE Questions from Part-B a) What are the characteristics of 2 s complement numbers?

More information

Logic Design Viva Question Bank Compiled By Channveer Patil

Logic Design Viva Question Bank Compiled By Channveer Patil Logic Design Viva Question Bank Compiled By Channveer Patil Title of the Practical: Verify the truth table of logic gates AND, OR, NOT, NAND and NOR gates/ Design Basic Gates Using NAND/NOR gates. Q.1

More information

VU Mobile Powered by S NO Group

VU Mobile Powered by S NO Group Question No: 1 ( Marks: 1 ) - Please choose one A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register.

More information

CS/ECE 250: Computer Architecture. Basics of Logic Design: ALU, Storage, Tristate. Benjamin Lee

CS/ECE 250: Computer Architecture. Basics of Logic Design: ALU, Storage, Tristate. Benjamin Lee CS/ECE 25: Computer Architecture Basics of Logic esign: ALU, Storage, Tristate Benjamin Lee Slides based on those from Alvin Lebeck, aniel, Andrew Hilton, Amir Roth, Gershon Kedem Homework #3 ue Mar 7,

More information

Registers and Counters

Registers and Counters Registers and Counters ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Registers Shift Registers

More information

FE REVIEW LOGIC. The AND gate. The OR gate A B AB A B A B 0 1 1

FE REVIEW LOGIC. The AND gate. The OR gate A B AB A B A B 0 1 1 FE REVIEW LOGIC The AD gate f A, B AB The AD gates output will achieve its active state, ACTIVE HIGH, when BOTH of its inputs achieve their active state, ACTIVE E HIGH. A B AB f ( A, B) AB m (3) The OR

More information