NEW MEXICO STATE UNIVERSITY Electrical and Computer Engineering Department. EE162 Digital Circuit Design Fall Lab 5: Latches & Flip-Flops

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1 NEW MEXICO STATE UNIVERSITY Electrical and Computer Engineering Department EE162 Digital Circuit Design Fall 2012 OBJECTIVES: Lab 5: Latches & Flip-Flops The objective of this lab is to examine and understand several aspects of two of the most basic sequential logic elements: latches and flip-flops. You will build a cross-coupled NAND latch, debounced switch, and two clocked S-R latches that will be combined to make a basic D flip-flop. You will use knowledge about sequential logic and timing gained in lectures, reading, and assignments. EQUIPMENT REQUIRED: Oscilloscope (with probe) Function Generator (with cables) Four 74LS00 Quad 2-Input NAND gate IC One 74LS10 Triple 3-Input NAND gate IC One 74LS04 Hex Inverter IC Wire Kits Logic Probe Blue or black pen Lab Notebook Calculator Breadboard Power Supply (with wall adaptor) Breadboard (You will be responsible for bringing the italicized items to this lab.) PREPARATION/PRE-LAB: PLEASE NOTE that students who do not have a complete pre-lab at the BEGINNING of their lab session will not be able to complete the exercise and will therefore be asked to leave the lab. Read and understand the entire lab handout and the relevant sections (Ch ) of the Roth textbook. For the cross-coupled NAND latch (Figure 1) and the clocked S-R latch (Figure 3) described in the manual below, construct a truth table which shows all inputs at a given time t and the resulting output a short time later, t + (where represents a short time period).

2 Print a lab coversheet from the course website and fill in your name, the date of the lab, the lab number and title, and circle your lab section. Also, bring all of your own lab equipment, as listed in the section above. LAB EXERCISE: 1. Cross-Coupled NAND Latch A. For the circuit of Figure 1, set up a transition table summarizing the operation of the circuit. This table needs to show all possible current value combinations for A, B, X, and Y in a truth table, and also show the resulting next values for X and Y. Figure 1 B. Use the circuit to build a bounceless switch as shown in Figure 2. Mechanical switches typically bounce when switched meaning when they transition from open to closed or vice versa; they make several very fast transitions. For example, a switch may transition open -> closed -> open -> closed when it should simply close once. Q1: Explain why the circuit in Figure 2 is bounceless and compare its to a mechanical switch. NOTE: Do not disassemble your bounceless switch; you will use it in the next section. Figure 2

3 2. Clocked S-R Latch A. Set up the circuit shown in Figure 3. Figure 3 B. Using your transition table for the circuit from your pre-lab, test the circuit using your bounceless switch as the CLOCK input. Compare your predicted transition table with the actual operation. Q2: What constraints must be imposed on the inputs S-R? (In other word, what are the inputs allowed to be?) Q3: In what way does the clock change the performance of the S-R latch? 3. Clocked S-R Master-Slave Flip-Flop A. Work with another student and connect two of the clocked S-R latches constructed in Part 2 in series. The end product should be similar to what is shown in Figure on page 304 of the textbook. The clock of the second latch (slave) must be the complement of the clock of the first (master) latch. B. Test the flip-flop using the bounceless switch as a clock. Record your observations. Q4: When does the output change values? Q5: How does it differ from the clocked S-R latch of Part 2? Q6: What is the advantage of this over the clocked S-R latch of Part 2?

4 4. Edge-Triggered D Flip-Flop A. A very common flop-flop in digital systems is the edge-triggered D flip-flop, shown in Figure 4. Construct this circuit. Figure 4 B. Explain in a few sentences how the circuit operates and why it is called edge-triggered. C. Test the flip-flop using the bounceless switch as a clock and record your results. Q7: When does the output change values? D. The minimum setup time is defined as the time interval during which the input data at D must be stable before the clock changes. The minimum hold time is defined as the interval during which the data at input D must be maintained after the clock changes. Q8: What is the active clock transition for this circuit? (In other words, which clock edge is it triggered by?) E. Connect a 74LS00 NAND gate as an inverter as shown in Figure 5. Connect the function generator output directly to the D input of your circuit and the inverted clock signal to the CLOCK input of your D flip-flop. F. Measure the set-up time given by this configuration on the scope by displaying the D and CLOCK inputs on the two channels. The setup

5 time is measured from the point the D input signal crosses 2.5 V to the point where the rising clock edge crosses 2.5 V. LAB REPORT: Figure 5 Q9: What is your measured setup time? Q10: What output would you expect in the ideal case of zero minimum setup time? Q11: Which output value did you observe? G. If you observed a setup time violation in part F, add an additional inverter to the CLOCK input to increase the CLOCK delay. This will increase the setup time. H. Check if a setup time violation still occurs. I. Determine how many inverters are required to meet the setup time. You will need to include the TA Verification Lab Cover Sheet or you will receive no credit for your report. (The TA will specify which parts he will verify.) Each individual is required to submit a lab report. Use the format specified in the "Lab Report Information" document available on the class web page. In your report, answer ALL questions, requested descriptions, and requested explanations in all parts of this handout. Be as complete and precise as possible. Be sure to include the following in your lab report: Completed lab cover sheet with TA verification. Graded pre-lab Your observations from each step of the lab exercise. Any plots and tables required in the lab write-up (scan your lab notebook or draw them in by hand)

6 GRADING SCHEME: Pre-Lab (20 points): Specifications given at the beginning of this manual Lab Check-Off (40 points): Working NAND latch (8 points) Working Bounceless switch (8 points) Working S-R latch (8 points) Working S-R flip-flop (8 points) Working D flip-flop (with setup time) (8 points) Lab report (40 points) There are 11 questions are numbered in boldface with a label beginning with Q within this manual. The correct answer to each is worth 3 points. Results for each step clearly stated (total of 5 points) Introduction and Conclusion with emphasis on your personal experience (total of 2 points)