VHDL Design and Implementation of FPGA Based Logic Analyzer: Work in Progress

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VHDL Design and Implementation of FPGA Based Logic Analyzer: Work in Progress Nor Zaidi Haron Ayer Keroh +606-5552086 zaidi@utem.edu.

1 VHDL Design and Implementation of FPGA Based Logic Analyzer: Work in Progress Nor Zaidi Haron Ayer Keroh Masrullizam Mat Ibrahim Ayer Keroh Amir Shah Abdul Aziz Ayer Keroh ABSTRACT This paper presents a Field Programable Logic Devices (FPGA) based logic analyzer controller. An 8-channel logic analyzer controller has been designed using Xilinx ISE Webpack programming tools and downloaded into Xilinx Spartan XC3S200-4FT256 FPGA chip. The controller circuit controls analog to digital converter MAX186 and generates measurement signal on 600 x 480 VGA monitor. The motivation of this project is to explore the capability of designing entire digital system in a single FPGA chip. The logic analyzer controller is written in Very High Speed Integrated Circuit Hardware Description Language (VHDL) source code and schematic capture. The behavioral simulation performance is carried out using ModelSim XE simulator. The implementation synthesis of the controller is also presented. Keywords Logic Analyzer, FPGA, VHDL, System on Chip. 1. INTRODUCTION Logic analyzers are widely used for testing digital or logic circuits. The continue improvement of this test equipment are owed to the emergence of microprocessor [1,2]. The most popular is a typical standalone logic analyzer. The capability of this logic analyzer to capture and display high speed signals makes it the first choice in universities and manufacturer. Nevertheless, the high performance standalone logic analyzer comes with it highly cost budget. For example, TDS2000B logic analyzer manufactured by Tektronix is simply in thousand of dollar. Another typical design is PC based logic analyzer which utilizing the processing power of computer. The system consists of data acquisition card for capturing analog input signal and converts them into digital, central processing unit for computing digitized data and monitor screen for displaying the measured signals. The PC based logic analyzer comes with lower price compare to the standalone logic analyzer [3]. However, the main drawback of PC based logic analyzer is its dependability to software that limits its performance. FPGAs have been utilized to implement digital systems since its introduction in 1985[4] by Xilinx Inc. The initial application of FPGA to serve as prototyping module of VLSI chips and glue logic to the microprocessor based circuits has change into commercial design. The advent of the semiconductor technology enables millions of gates to form this chip. This fact realizes the methodology of designing in single chip or known as System on Chip (SoC) design. The paper is organized as follows: Section 2 describes the FPGA based logic analyzer system. The implementation of logic analyzer controller in FPGA is discussed in Section 3. The FPGA implementation result is reported in Section 4. The result of data acquisition process simulated using ModelSim XE simulation tool is illustrated in Section 5 whilst Section 6 shows the synthesis result of the controller. Conclusion is presented in Section SYSTEM OVERVIEW The proposed FPGA based logic analyzer is illustrated in Figure 1. It consists of an analog digital converter, an FPGA and a monitor screen. Figure 1. Specification of the system. 2.1 Analog to Digital Converter MAX186 ADC is used to convert signals captured by external probe into 12-bit digital stream data. The eight channels ADC is capable to sample maximum of 133KHz signal. The MAX186 ADC has an internal 4.096V reference voltage [5]. The connection between MAX186 and FPGA is depicted in Figure 2. Both chips share common 5V supply. The clock of the ADC is supplied by frequency divider designed in FPGA. Channel multiplexing is determined by data that inserted in DIN. The 12-bit digitized data is passed to FPGA through pin DOUT. 143

2 Figure 2. MAX186 ADC and FPGA. 2.2 Logic Analyzer Controller This is the main part of this project. The FPGA top-down design approach is utilized. The entire design is organized by subdividing it into smaller units in design phase. Figure 3 shows the top view of the controller. The controller operates as sequencer, frequency divider, data acquisition, shift register, data comparison, data storage, address generator and video generation. The brief explanation on this part is discussed in part 3. horizontal pixels. Most monitors, including VGA, use a serial scheme to set the color of each pixel. This means that the VGA controller sends the color information for each pixel one at a time, rather than being able to set all of the colors at once in a parallel scheme. This color information for each pixel is provided by a RGB (Red, Green, Blue) triplet. Three analog signals are used represent relative amounts of red, green and blue that composes the color [6]. The idea of displaying the eight channels is shown in Figure 4. Each of the channel takes horizontal and vertical coordinates (x,y). For example, channel 0 occupied coordinate (0,50) to (640,50). Channel 1 position is along the horizontal line of 100 i.e. (0,100) to (640,100). Each of the data stored in memory represents each pixel from coordinate 128 to 640 in horizontal line. The eight channel lines are drawn in vertical coordinates. VGA monitor operates by drawing pixel from left to right. This is the reason data is organized in such way in memory. When the converter is enables, it read memory locations where sampled signal in channel 0 is stored and draw pixel from (128, 50) to (640, 50). The next sweep draws pixel generated from the sampled bit for channel 1. This continues until all eight channels are displayed. DAQ Controller Frequency Divider Sequencer VGA Controller 8Kbit Memory Comparator Shift Register Address Generator Figure 3. Logic analyzer controller block diagram designed in FPGA. 2.3 Monitor Screen The third main element is video graphic array (VGA) converter that takes buffered bit in memory and change into video format to be displayed on 600 x 480 monitor screen. The VGA monitor can be thought of as a grid of pixels (picture elements which can be individually set to a specific color). It contains 480 rows of 640 Figure 4. VGA display. 2.4 System Operation The logic analyzer operates in two modes; capture and display. Figure 5 depicts the diagram of this operation. The system starts to operate when it is turned on. Capture mode is executed where data are captured, compared and stored. It will only go into display mode after all memories have been written. During display mode, stored signals are retrieved and drawn in monitor screen. Each mode will perform The operation returns to capture mode upon completing drawing the signals. This repetitive operation is executed until the system is turned off. Any disturbance such as resetting the system will go into default state i.e capture modes. Figure 5. FSM model for logic analyzer operation. 144

3 3. LOGIC ANALYZER CONTROLLER DESIGN The controller performs numerous functions such as frequency divider, ADC channel multiplexing, serial to parallel signal shifting, comparison and storage. The global frequency 50 MHz is divided by 25 to have 2 MHz frequency to drive MAX186 ADC. The ADC has maximum operating frequency 3.2 MHz. Signal capture is performed by multiplexing the ADC. Simple three bits control signal are asserted into ADC to select which channel is activated in one time. It means that if the control signal is 000, channel 0 will capture the signal. In the other hand, if 111 is supplied to ADC, signal is captured by channel 8. These control bits are stored in read only memory (ROM) and will be called when needed. The incoming 12 bits digitized data is shifted from series into parallel form before it is compared to determine the logic level; either 1 or 0. From the [2], logic 0 is defined as to , logic 1 is determined as to and undefined logic between the range. This is valid for CMOS logic level and not for TTL and other logic level. The result of this comparison is stored in 40962x1 memories in sequence of N+8. The organization is made in such way to make it easy when it comes to display the signal on monitor screen. Figure 6 shows how compared signals are stored in the memory. During the first capture, compared signal from channel 0 to 7 is written in locations 0 to 7 in sequence. In the next sweep, locations 8 to 15 accommodate the results of captured signals. This operation is repeated until all locations of the memory have been occupied. similar sequence with the write operation above i.e. N+8. The display is continued until all signals are retrieved and drawn before the operation is deactivate and go into capture mode. 4. DESIGN FLOW VHDL source code and schematic design entry used to design logic analyzer controller. Xilinx ISE [7] programming tool is utilized in this process. Each units in the controller is written using VHDL source code; a hardware design language that describe how hardware behaves. Schematic capture combines all units and connection is made. The system is verified using Modelsim; a third party supporting behavioral simulation tools comes with Xilinx ISE. Test bench waveform is inserted as input stimuli to the combined unit or usually called as device under test (DUT). The design entry and behavioral verification block diagram is illustrated in Figure Data 0 1 Data 1 1 Channel 0 Figure 7. Design entry and behavioral verification flow. 2 Data 2 1 Channel Data 3 1 Data 4 1 Channel Data 5 1 Data 6 1 Data 7 1 Data 0 2 Channel 3 8 Data l Data 2 2 Data 3 2 Data 4 2 Figure 6. Memory organization. When this happened, the ADC is disabled so that no signal capture is performed. Now, the system goes into display mode. VGA controller is activated and the stored data is read out and manipulated to be displayed on monitor screen. Data is drawn in sequence from channel 0 1, 2 and so on until channel 7. Each data represent a pixel which will produce a logic level line that determines the measured signal. Therefore, every channel is drawn by 512 ( ) pixels. Data is read from memory in the 5. SIMULATION RESULT 145

Figure 8. Data acquisition waveform. Simulation result shown in Figure 8 is the data acquisition operation where adc_control_byte select signal from channel 0, 1 and 2 to be read from MAX186 ADC.

After shifting (data_test) and compare operation is performed, a bit data is produced and stored into memory. The adc_strb_test signal is the starting point of conversion of ADC. 6.

4 Figure 8. Data acquisition waveform. Simulation result shown in Figure 8 is the data acquisition operation where adc_control_byte select signal from channel 0, 1 and 2 to be read from MAX186 ADC. Three input signal is set for each channel; logic 1 for channel 0, logic 0 for channel 1 and high impedence Z for channel 2. After shifting (data_test) and compare operation is performed, a bit data is produced and stored into memory. The adc_strb_test signal is the starting point of conversion of ADC. 6. SYNTHESIS RESULT The behavioral verified design is then underwent FPGA design flow such as synthesis, optimization, mapping, placement, routing, bitstream generation and programming as shown in Figure 9. Figure 10. RTL schematic of logic analyzer controller. Table 1 tabulates the synthesize report. The synthesized logic analyzer controller utilized only 4% of the available slices (basic unit that produced from 4-input look up table and slice flip-flops). Together with the slice, flip-flip and 4-input look up table made up of 2% and 4% from the obtainable logic respectively. About 13% of input output blocks is bonded, 8% of the bus RAM is used and 37% global clock is connected. Table 1. Logic analyzer synthesize report. 7. SUMMARY AND FUTURE WORK In this paper, we described the current progress FPGA based logic analyzer design ad implementation. The work has accomplished approximately 70% of the whole system. Further progress is to complete the entire hardware system by connecting FPGA and ADC to VGA monitor. The performance of the complete system will be carried out in order to validate it functionality. Figure 9. Xilinx FPGA design flow. The connected units are synthesized to produces logic gates and flip-flop connection. This is due to the fact that FPGA is formed basically from logic gates and flip-flops. Figure 10 depicted the synthesized register transfer level schematic circuits. 8. ACKNOWLEDGMENTS This work was supported by the ; grant number PJP/2006/FKEKK(16)-S REFERENCES [1] B.J. Hammond Development in Logic Analyzer Instrumentation in Electronic Product Manufacture, IEE Colloquium on, London, UK, May 1989, Page(s): 2/1-2/3. [2] N. Hyder Logic Analysers: Principle and Application Techniques for Testing and Measuring Digital Systems, IEE Colloquium on, London, UK, Oct 1988, Page(s): 1/1-1/2. [3] B.H Lee, R.Z. Makki, C. Roheb A VLSI based logic analyzer interface for a microprocessor development system System 146

5 Theory, Proceedings., Twenty-Third Southeastern Symposium on, Columbia, SC, USA, March 1991, Page(s): [4] Maya Gokhale, Paul S. Graham Reconfigurable Computing: Accelerating Computation with Field-Programmable Gate Arrays Springer Publishing, February [5] Maxim, MAX186 ADC datasheet, [6] Amr Mohamed Reda Mallah, et al. VHDL Implemented of Digital Oscilloscope Using FPGA Department of Communications and Electronics, Faculty of Engineering, Alexandria University. [7] Xilinx Inc., Xilinx ISE Webpack v8.21, download.xilinx.com 147

Design of VGA Controller using VHDL for LCD Display using FPGA

International OPEN ACCESS Journal Of Modern Engineering Research (IJMER) Design of VGA Controller using VHDL for LCD Display using FPGA Khan Huma Aftab 1, Monauwer Alam 2 1, 2 (Department of ECE, Integral