Muon Trigger Flavor Board (MTFB) Design and Specifications

Muon Trigger Flavor Board (MTFB) Design and Specifications Issue 2.41 December 11, 1998 Prepared by: Ken Johns, Freedy Nang, Kevin Davis, Rob McCroskey, and David Fein University of Arizona Tucson, Arizona

1 Introduction... 5 2 General Description... 6 3 MTC05... 10 3.1 CFMTC05... 10 3.2 EFMTC05... 10 4 MTC10... 11 4.1 CFMTC10... 11 4.1.1 Inputs/Outputs... 11 4.1.2 JTAG BST Connection... 12 4.1.3 FPGA Design... 12 4.1.4 FPGA Timing/Fitting... 12 4.1.5 Power Requirements... 13 4.1.6 Super Project CF MTC10... 14 4.1.7 LED s... 14 4.1.8 FPGA Testing... 14 4.2 EFMTC10... 14 5 Conclusions... 15 6 Appendix A MTCxx Card Input... 16 7 Appendix B Pinouts for the MTFB (P1 P6)... 18 8 Appendix C CF MTC10 FPGA I/O... 26 8 References... 45

Figure 1 - MTCxx Card and Flavor Board Outline... 5 Figure 2 - Possible layout of the CF MTC10 MTFB. The connectors are placed on the underside of the board. The total board space is 10 in. x 6 in. Drawing is to scale... 8 Figure 3 - How the MTFB might look on the a proposed MTCxx Card. The MTFB is shown as the grey board outline in the center of the MTCxx. Only the connectors on the MTFB are drawn. Note that there are two (2) 40-pin TFM connectors draw on the MTCxx. The extra connector (P7) is used only by the MTM board... 9 Figure 4 - Overview of the CF MTC10 MTFB FPGA Logic... 11 Figure 5 A CENT Top Level Design... 29 Figure 6 - A CENT Timing Diagram... 30 Figure 7 - B CENT Top Level Design... 31 Figure 8 B CENT Timing Diagram... 32 Figure 9 - C CENT Top Level Design... 33 Figure 10 - C CENT Timing Diagram... 34 Figure 11 - TRIG1 Top Level Design... 35 Figure 12 - TRIG1 Timing Diagram... 36 Figure 13 - TRIG2 Top Level Design... 37 Figure 14 - TRIG2 Timing Diagram... 38 Figure 15 - TRIG3 Top Level Design... 39 Figure 16 - TRIG3 Timing Diagram... 40 Figure 17 - Octant Sum Top Level Design... 41 Figure 18 - Octant Sum Timing Diagram... 42 Figure 19 - Super Project CF MCT10 Top Level Design... 43 Figure 20 - Super Project CF MTC10 Timing Diagram... 44 Table 1 - The six connectors used between the MTFB and the MTCxx... 6 Table 2 Summary of MTFB FPGA Requirements... 7 Table 3 - Package Type and Dimensions for Proposed FPGAs... 7 Table 4 - Summary of FPGA Fitting Parameters... 13 Table 5 - CF MTC10 FPGA Power Consumption Estimates... 14 Table 6 - CF MTC05 Card Input (Octants 0,1,2,3,4,7)... 16 Table 7 - CF MTC05 Card Input (Octants 5,6)... 16 Table 8 - CF MTC10 Card Input (Octants 0,1,2,3,4,7)... 16 Table 9 - CF MTC10 Card Input (Octants 5,6)... 16 Table 10 - EF MTC05 Card Input... 16 Table 11 - EF MCT10 Card Input... 17 Table 12 - Summary of CF MTC10 FPGA Signals... 28

1 Introduction The actual trigger functions of the Level 1 Muon Trigger (L1MU) system are performed by the Muon Trigger Cards (MTCxx s) and their associated Muon Trigger Flavor Boards (MTFB s). The L1MU system is divided into eight octants for each of the three geographical regions (CF, EFN, and EFS). Further, there are two MTCxx cards for each octant. Generally, one MTCxx card makes use of L1 Central Fiber Tracking Trigger (L1CFT) tracks and scintillator counter hits (called 05 logic) while the other MTCxx card makes use of wire chamber hits (CF) or mini-drift tubes (EF) and scintillator counter hits (called 10 logic). The L1MU system is described further in Refs. [1] and [2]. To maximize flexibility and to minimize the engineering effort, the MTCxx card is uniform throughout the L1MU system. Different logic inputs, outputs, and algorithms are accommodated by the use of a MTFB, which connects to a MTCxx. Thus, the MTFB changes the flavor of each MTCxx. Distinct MTFB s are needed for different regions (e.g. CF versus EFN), different trigger algorithms (e.g. 05 versus 10 ), and perhaps even different octants (e.g. top and sides versus bottom octants). Figure 1 shows the overall design of the MTCxx and MTFB. See Ref. [3] for a full description of the MTCxx card. This document describes the design and logic of each flavor of the MTFB. Figure 1 - MTCxx Card and Flavor Board Outline 5

2 General Description The MTFBs reside on the MTCxx cards, which are 9u x 400-mm VME cards with 16 available serial inputs (and receiver cards) along with a complete VME interface. While the MTCxx cards will all be identical, the serial inputs to these boards will differ depending on which flavor board the MTCxx is housing. For instance, the CF MTC05 cards only require 13 serial inputs of which 10 are from the CFT, 2 from the APHI counters, and one for the CMSC C hits. A complete list of the serial inputs for each flavor card is given in Appendix A. While not all flavors of the MTFB use all the possible inputs and outputs to the MTCxx, the total number of I/O pins on the MTFB is determined by the maximum number of I/O pins needed by any flavor of MTFB (since the I/O specifications are the same for all MTFBs). Below is a description of the total number of I/O pins requires to satisfy any flavor of MTFB: Serial Inputs = 16 x 16 = 256 lines 53 MHz RF Clock Start FLEX Chip Download = 13 lines Power GND Additional Timing Signals (i.e. BC, DAV) Output Trigger Decision = 36 lines Output Supplemental Data = 16 lines Test Points = 29 lines With up to 16 serial inputs required per MTCxx, many pins are needed to connect the MTCxx and the MTFB. One connector that fills our requirements is the SAMTEC MOLC/FOLC family of connectors. These are 4 row, 0.050 x 0.050 micro strip connectors which have up to 50 rows (for a total of 200 pins). In addition, the mating height for these connectors is 0.250 from PCB-to-PCB (for SMD). The connectors also have a current rating of 1A per pin. (The MOLC connectors go on the MTFB while the FOLC are on the MTCxx cards.) In addition, we have added P6 to transfer the test point data. P6 is from the SAMTEC TFM/SFM family of connectors which has two rows of pins. Appendix B shows the complete pin outs for the MTCxx to MTFB connection. See also Reference [3]. To facilitate the large number of pins, we are using six SAMTEC connectors. Table 1 shows the characteristics of each of these connectors. CONNECTOR LABEL ROWS PINS/ROW TOTAL # PINS P/N P1 4 25 100 MOLC-125-02-S-Q-LC P2 4 25 100 MOLC-125-02-S-Q-LC P3 4 25 100 MOLC-125-02-S-Q-LC P4 4 25 100 MOLC-125-02-S-Q-LC P5 4 35 140 MOLC-135-02-S-Q-LC P6 2 20 40 TFM-120-02-S-D-LC Table 1 - The six connectors used between the MTFB and the MTCxx This gives a total of 580 pins. P1 P4 are used for the deserialized data. Each P1 P4 connector carries four serial cables worth of data. P5 is used for timing, trigger decisions, FPGA downloading, and other I/O functions. P6 is used to transfer the test point signals from the MTFB to the MTCxx and then to the front panel connector (p/n 3M 3433). 6

To determine the maximum area needed to facilitate the FPGAs, passive devices, and connectors used on the MTFB (all flavors of the MTFB have the same dimensions), the size and number of each type of FPGA needs to be determined. Table 2 gives preliminary estimates for the number of each type of FPGA used on each flavor of the MTFB. MTFB Name Altera FPGA Part # Quantity CF MTC05 Same as EF MTC05 7 Total CF MTC10 10K50VRC240-2 6 10K30ATC144-3 1 EF MTC05 10K30AQC240-2 4 10K30AQC240-3 1 10K100ARC240-3 1 10K10AQC208-3 1 EF MTC10 Same as CF MTC10 7 Total Table 2 Summary of MTFB FPGA Requirements From Table 2, we see that the total number of FPGAs needed on each flavor of MTFB is the same. In addition, the total space requirements of the FPGAs are approximately the same for each flavor. Given this, an estimate of the dimensions of the MTFB can be made. Table 3 gives the dimensions and package types of the proposed FPGAs. Altera Device # Package Name Description Dimensions(WxLxD)(in) 10K50V/100ARC240 QFP Power Quad Flat Pack 1.352 x 1.352 x 0.161 10K30ATC144 TQFP Thin Plastic Quad Flat Pack 0.866 x 0.866 x 0.060 10K10AQC208 QFP Power Quad Flat Pack 1.195 x 1.196 x 0.161 Table 3 - Package Type and Dimensions for Proposed FPGAs Figure 2 shows an example layout of the CF MTC10 MTFB, while Figure 3 shows how the MTFB would sit on the MTCxx card. Both of these figures are drawn to scale, where the dimensions of the MTFB are 12 x 6. The connectors in Figures 2 and 3 are located on the underside of the board. Finally, we see that because of the relatively small size of the MTFB, any delays on signals between FPGAs should be small. (If we assume 2 ns/foot, then a 3 inch trace between FPGAs results in a delay of 500 ps.) The loading of the FPGA s on the MTFBs will be done in the same way as the FPGAs are loaded on the Muon Trigger Crate Manager (MTCM). This involves using flash memory on the MTCxx cards to store the FPGA programs and then use the passive serial download (see Ref.[3]). This method uses four (4) control lines that are chained amongst all the FPGAs, and one unique enable line for each FPGA on the board. Using the information from Table 2 and the size of each FPGA program 1, the total memory needed to store the FPGA programs is 0.5Mb for the CFMTC10 and 0.61Mb for the EFMTC05. The total memory dedicated to the FPGA download on the MTCxx card is 1Mb. 1 See http://www.altera.com/html/atlas/soln/929.html 7

Figure 2 - Layout of the CF MTC10 MTFB. The connectors are placed on the underside of the board. The total board space is 10 in. x 6 in. Drawing is to scale. 8

Figure 3 - How the MTFB might look on the a proposed MTCxx Card. The MTFB is shown as the grey board outline in the center of the MTCxx. Only the connectors on the MTFB are drawn. Note that there are two (2) 40-pin TFM connectors draw on the MTCxx. The extra connector (P7) is used only by the MTM board. 9

3 MTC05 Some introduction here explaining what the inputs are to the MTC05 cards (ef = pix + cft, cf=scint+cft). 3.1 CFMTC05 3.2 EFMTC05 10

4 MTC10 Some general comments in here on the inputs to the mtc10 (cf = scint + pdt, ef = pixel + mdt). 4.1 CFMTC10 4.1.1 Inputs/Outputs The specific inputs and outputs of the CF MTC10 Flavor board and each of the FPGAs are shown in Figure 4 and listed in Appendix B. Also included in Appendix B are descriptions of the input and output of each of the FPGAs shown in Figure 4. Figure 4 - Overview of the CF MTC10 MTFB FPGA Logic The inputs to the CF MTC10 MTFB are broken down into the following components: PDTA = 16x3 = 48 lines PDTB = 16x5 = 80 lines PDTC = 16x5 = 80 lines CMSCA = 16x2 = 32 lines CMSCC = 16 lines CLOCK START 11

FLEX Chip Download = 11 lines. The total number of output lines from the CF MTC10 MTFB is 24 and is broken down into the following components: Six 2-bit Counters = 6x2 = 12 lines ACENT(Supplemental Data) = 12 lines 4.1.2 JTAG BST Connection The total number of interconnects between the FPGA s on the CF MTC10 MTFB is rather large (>500). In order to test the connectivity between these pins, the JTAG IEEE 1149.1 boundary-scan architecture is incorporated for each of the FPGA s. The boundary-scan test (BST) uses four signals brought in through the external connector J1. J1 is a 10-pin (2 x 5) female plug (i.e. standard JTAG connector). More details will be provided in future revisions as the software for developing this testing is brought online. 4.1.3 FPGA Design We are using Altera field programmable gate arrays (FPGAs) to form the trigger decisions. From Figure 4, we see that the CF MTC10 MTFB utilizes 7 FPGAs. The function of each of these FPGAs is described below. The complete listing of all the inputs and outputs to each FPGA is given in Appendix C. A CENT - Receives A-layer PDT hits and APHI counter hits and calculates A-layer centroids with APHI confirmation. B CENT - Receives B-layer PDT hits and APHI counter hits and calculates B-layer centroids with APHI confirmation. C CENT - Receives C-layer PDT hits and CMSC C (Cosmic Cap) hits and calculates C-layer centroids with CMSC C confirmation. TRIG1 - Finds A, AB.or.AC, and AB.or.AC.or.BC triggers using centroid information that correspond to the A-centroid range [1,48]. Also or s A-centroids by 12 to give 4 bits of A-cent. The triggers are all 2-bit counters. TRIG2 - Finds A, AB.or.AC, and AB.or.AC.or.BC triggers using centroid information that correspond to the A-centroid range [49,96]. Also or s A-centroids by 12 to give 4 bits of A-cent. The triggers are all 2-bit counters. TRIG3 - Finds A, AB.or.AC, and AB.or.AC.or.BC triggers using centroid information that correspond to the A-centroid range [97,144]. Also or s A-centroids by 12 to give 4 bits of A-cent. The triggers are all 2-bit counters. OCTANT SUM - Receives input from TRIG1, TRIG2, and TRIG3 and calculates the final 2-bit counters for the A, AB.or.AC, and AB.or.AC.or.BC triggers. Also forms final 12-bit counter for A- centroids. 4.1.4 FPGA Timing/Fitting Given the current trigger logic and CF MTC10 FPGA design, we have calculated the timing and available logic cells (LC s) for each of the FPGAs. The overall L1 muon trigger design specifies that the CF MTC10 has at most 7 ticks (1 tick = 132 ns) to form its trigger decision. Using the simulator supplied with the MAX-plus II (V9.01) Altera package, we can calculate the time required for each FPGA to form a 12

decision. We find that the centroid finding FPGAs (A CENT, B CENT, and C CENT) only require 2 ticks (264 ns) to form their centroids. The trigger finding FPGAs (TRIG1, TRIG2, and TRIG3) also require 3 ticks (396 ns) to form the trigger decisions. Finally, the summing FPGA (OCTANT SUM) requires 1 tick (132 ns) to form the final trigger decision that is passed to the MTC Mother board. This gives a total time of only 6 ticks, or 792 ns, to form the CF MCT10 trigger. As a side note, the multiplexers and demultiplexers take up a large fraction of the time spent in the FPGAs. The actual centroid finding and trigger finding routines tend to be very fast ( 40 ns). Included at the end of this document are sample timing diagrams of each FPGA along with the top level design sheet. Because the centroid finding and trigger forming routines are quite large, we have to use larger FPGAs. Table 2 summarizes which Altera FPGAs are used and what percentage of their logic cells (LC s) are occupied. We see that none of the FPGAs use more than 64% of available logic cells. All FPGAs were optimized for speed (optimization value = 10). FPGA Name Altera Part # # of Input Pins # of Output Pins % of Logic Cells Used A CENT 10K50VRC240-2 82 28 64 B CENT 10K50VRC240-2 114 44 58 C CENT 10K50VRC240-2 98 44 60 TRIG1 10K50VRC240-2 82 14 39 TRIG2 10K50VRC240-2 90 14 62 TRIG3 10K50VRC240-2 74 14 41 OCTANT SUM 10K30ATC144-3 31 56 2 Table 4 - Summary of FPGA Fitting Parameters Also shown in Table 4 are the required number of input and output pins for each FPGA. The centroid and trigger finding FPGAs have an available 189 user I/O pins while the summing FPGA has an available 68 user I/O pins. In all cases we still have many unused I/O pins. Because of this fact, along with the relative amount of free LC s available on each FPGA, we feel that we have good flexibility in any possible changes that may occur to the logic without having to make changes to the flavor board. 4.1.5 Power Requirements We can estimate the current requirements of each of the FPGA s used on the CF MTC10 MTFB (operating at +3.3V). Using the formula from Ref. [4], where P = P INT + P IO = (I STANDBY + I ACTIVE ) x V CC + P IO, P IO = I/O power (not determined yet depends on load characteristics), I STANDBY = 10 ma, and I ACTIVE = K * freq * N * tog LC. Here, K is a constant depending on the device (K=45 (10K50V), K=32(10K30A)), freq is the maximum frequency used in MHz, N is the total number of logic cells used, and tog LC is the fraction of logic cells that change level during each clock cycle. This is typically 12.5% according to [4]. Using this formula, we derive the estimates for power consumption for each of the FPGA s used on the CF MTC10 MTFB shown in Table 4. 13

FPGA Name Altera Part # Power, P(mW) A CENT 10K50VRC240-2 1800 B CENT 10K50VRC240-2 1640 C CENT 10K50VRC240-2 1700 TRIG1 10K50VRC240-2 1100 TRIG2 10K50VRC240-2 1760 TRIG3 10K50VRC240-2 1160 OCTANT SUM 10K30ATC144-3 10 Table 5 - CF MTC10 FPGA Power Consumption Estimates This gives us a total power consumption of approximately 9.2W for the CF MTC10 MTFB. 4.1.6 Super Project CF MTC10 The MAX+PLUS II application allows for the simulation of multiple projects. That is, we are able to simulate all seven of the FPGA s in one project. Thus, the timing for the entire CF MTC10 MTFB can be simulated. The multiple project simulation combines the timing from each of the individual FPGA s into an overall timing for the MTFB, where the delay time for signals that migrate between FPGA s is zero. This should not be a problem as we anticipate the delay time to be on the order of a few hundred ps. Figure 20 shows the timing for the entire CF MTC10 MTFB for a given set of inputs. More test vectors are needed to fully test the timing. Figure 20 shows that the final output from the CF MTC10 MTFB arrives in 6 ticks (6 x 132 ns). The top-level design of the CF MTC10 MTFB is shown in Figure 19. This figure also shows the paths of all the signals in-between each FPGA. 4.1.7 LED s The LED s used to monitor the MTFB functions are mounted on the MTCxx front panel. A description of these LEDs can be found in the MTCxx functional description note. 4.1.8 FPGA Testing To produce the timing diagrams of each of the FPGAs shown at the end of this document, test vectors were created to simulate the inputs to the FPGAs. The test vectors are comprised of all possible combinations of TRUE logic found in the logic AND/OR network of each FPGA. For each 132ns bunch, one logic element was tested to see if it produced a TRUE output at the correct time. Note that only one TRUE logic element was tested at a time. Given that all the TRUE logic elements were tested, any combination of these elements that may occur within the same 132ns bunch crossing, should give the desired result. 4.2 EFMTC10 14

5 Conclusions 15

6 Appendix A MTCxx Card Input Cables Strobes Definition 10 6 x 16 6 CFT tracks from each of 10 sectors 2 6 x 16 45 APHI counter hits per cable 1 6 x 16 40x2 CMSC C counter hits (from MCEN) Table 6 - CF MTC05 Card Input (Octants 0,1,2,3,4,7) Cables Strobes Definition 10 6 x 16 6 CFT tracks from each of 10 sectors 1 6 x 16 45 APHI counter hits 1 6 x 16 36x2 CMSC B counter hits (from MCEN) 1 6 x 16 18x2 CMSC C counter hits (from MCEN) Table 7 - CF MTC05 Card Input (Octants 5,6) Cables Strobes Definition 3 6 x 16 96 A PDT hits 5 6 x 16 72 B PDT hits 5 6 x 16 72 C PDT hits 1 6 x 16 45 APHI counter hits 1 6 x 16 40x2 CMSC C counter hits (from MCEN) Table 8 - CF MTC10 Card Input (Octants 0,1,2,3,4,7) Cables Strobes Definition 3 6 x 16 96 A PDT hits 5 6 x 16 72 B PDT hits 5 6 x 16 72 C PDT hits 1 6 x 16 45 APHI counter hits 1 6 x 16 36x2 CMSC B counter hits (from MCEN) 1 6 x 16 18x2 CMSC C counter hits (from MCEN) Table 9 - CF MTC10 Card Input (Octants 5,6) Cables Strobes Definition 10 6 x 16 6 CFT tracks from each of 10 sectors 1 6 x 16 48x2 A PIXEL hits per cable (from MCEN) 1 6 x 16 48x2 B PIXEL hits per cable (from MCEN) 1 6 x 16 48x2 C PIXEL hits per cable (from MCEN) Table 10 - EF MTC05 Card Input 16

Cables Strobes Definition 3 6 x 16 A MDT Centroids (from MCEN) 4 6 x 16 B MDT Centroids (from MCEN) 4 6 x 16 C MDT Centroids (from MCEN) 1 6 x 16 48x2 A PIXEL hits per cable (from MCEN) 1 6 x 16 48x2 B PIXEL hits per cable (from MCEN) 1 6 x 16 48x2 C PIXEL hits per cable (from MCEN) Table 11 - EF MCT10 Card Input 17

7 Appendix B Pinouts for the MTFB (P1 P6) MTFB Connector P1 Pin Label Pin Label Pin Label Pin Label A1 +3.3V B1 +3.3V C1 +3.3V D1 +3.3V A2 GND B1 GND C2 GND D2 GND A3 IN1-0 B3 IN2-0 C3 IN3-0 D3 IN4-0 A4 IN1-1 B4 IN2-1 C4 IN3-1 D4 IN4-1 A5 IN1-2 B5 IN2-2 C5 IN3-2 D5 IN4-2 A6 IN1-3 B6 IN2-3 C6 IN3-3 D6 IN4-3 A7 GND B7 GND C7 GND D7 GND A8 IN1-4 B8 IN2-4 C8 IN3-4 D8 IN4-4 A9 IN1-5 B9 IN2-5 C9 IN3-5 D9 IN4-5 A10 IN1-6 B10 IN2-6 C10 IN3-6 D10 IN4-6 A11 IN1-7 B11 IN2-7 C11 IN3-7 D11 IN4-7 A12 GND B12 GND C12 GND D12 GND A13 IN1-8 B13 IN2-8 C13 IN3-8 D13 IN4-8 A14 IN1-9 B14 IN2-9 C14 IN3-9 D14 IN4-9 A15 IN1-10 B15 IN2-10 C15 IN3-10 D15 IN4-10 A16 IN1-11 B16 IN2-11 C16 IN3-11 D16 IN4-11 A17 GND B17 GND C17 GND D17 GND A18 IN1-12 B18 IN2-12 C18 IN3-12 D18 IN4-12 A19 IN1-13 B19 IN2-13 C19 IN3-13 D19 IN4-13 A20 IN1-14 B20 IN2-14 C20 IN3-14 D20 IN4-14 A21 IN1-15 B21 IN2-15 C21 IN3-15 D21 IN4-15 A22 GND B22 GND C22 GND D22 GND A23 Spare B23 Spare C23 Spare D23 Spare A24 +3.3V B24 +3.3V C24 +3.3V D24 +3.3V A25 RF-CLK B25 GND C25 BC-CLK D25 GND 18

MTFB Connector P2 Pin Label Pin Label Pin Label Pin Label A1 +3.3V B1 +3.3V C1 +3.3V D1 +3.3V A2 GND B1 GND C2 GND D2 GND A3 IN5-0 B3 IN6-0 C3 IN7-0 D3 IN8-0 A4 IN5-1 B4 IN6-1 C4 IN7-1 D4 IN8-1 A5 IN5-2 B5 IN6-2 C5 IN7-2 D5 IN8-2 A6 IN5-3 B6 IN6-3 C6 IN7-3 D6 IN8-3 A7 GND B7 GND C7 GND D7 GND A8 IN5-4 B8 IN6-4 C8 IN7-4 D8 IN8-4 A9 IN5-5 B9 IN6-5 C9 IN7-5 D9 IN8-5 A10 IN5-6 B10 IN6-6 C10 IN7-6 D10 IN8-6 A11 IN5-7 B11 IN6-7 C11 IN7-7 D11 IN8-7 A12 GND B12 GND C12 GND D12 GND A13 IN5-8 B13 IN6-8 C13 IN7-8 D13 IN8-8 A14 IN5-9 B14 IN6-9 C14 IN7-9 D14 IN8-9 A15 IN5-10 B15 IN6-10 C15 IN7-10 D15 IN8-10 A16 IN5-11 B16 IN6-11 C16 IN7-11 D16 IN8-11 A17 GND B17 GND C17 GND D17 GND A18 IN5-12 B18 IN6-12 C18 IN7-12 D18 IN8-12 A19 IN5-13 B19 IN6-13 C19 IN7-13 D19 IN8-13 A20 IN5-14 B20 IN6-14 C20 IN7-14 D20 IN8-14 A21 IN5-15 B21 IN6-15 C21 IN7-15 D21 IN8-15 A22 GND B22 GND C22 GND D22 GND A23 Spare B23 Spare C23 Spare D23 Spare A24 +3.3V B24 +3.3V C24 +3.3V D24 +3.3V A25 RF-CLK B25 GND C25 BC-CLK D25 GND 19

MTFB Connector P3 Pin Label Pin Label Pin Label Pin Label A1 +3.3V B1 +3.3V C1 +3.3V D1 +3.3V A2 GND B1 GND C2 GND D2 GND A3 IN9-0 B3 IN10-0 C3 IN11-0 D3 IN12-0 A4 IN9-1 B4 IN10-1 C4 IN11-1 D4 IN12-1 A5 IN9-2 B5 IN10-2 C5 IN11-2 D5 IN12-2 A6 IN9-3 B6 IN10-3 C6 IN11-3 D6 IN12-3 A7 GND B7 GND C7 GND D7 GND A8 IN9-4 B8 IN10-4 C8 IN11-4 D8 IN12-4 A9 IN9-5 B9 IN10-5 C9 IN11-5 D9 IN12-5 A10 IN9-6 B10 IN10-6 C10 IN11-6 D10 IN12-6 A11 IN9-7 B11 IN10-7 C11 IN11-7 D11 IN12-7 A12 GND B12 GND C12 GND D12 GND A13 IN9-8 B13 IN10-8 C13 IN11-8 D13 IN12-8 A14 IN9-9 B14 IN10-9 C14 IN11-9 D14 IN12-9 A15 IN9-10 B15 IN10-10 C15 IN11-10 D15 IN12-10 A16 IN9-11 B16 IN10-11 C16 IN11-11 D16 IN12-11 A17 GND B17 GND C17 GND D17 GND A18 IN9-12 B18 IN10-12 C18 IN11-12 D18 IN12-12 A19 IN9-13 B19 IN10-13 C19 IN11-13 D19 IN12-13 A20 IN9-14 B20 IN10-14 C20 IN11-14 D20 IN12-14 A21 IN9-15 B21 IN10-15 C21 IN11-15 D21 IN12-15 A22 GND B22 GND C22 GND D22 GND A23 Spare B23 Spare C23 Spare D23 Spare A24 +3.3V B24 +3.3V C24 +3.3V D24 +3.3V A25 RF-CLK B25 GND C25 BC-CLK D25 GND 20

MTFB Connector P4 Pin Label Pin Label Pin Label Pin Label A1 +3.3V B1 +3.3V C1 +3.3V D1 +3.3V A2 GND B1 GND C2 GND D2 GND A3 IN13-0 B3 IN14-0 C3 IN15-0 D3 IN16-0 A4 IN13-1 B4 IN14-1 C4 IN15-1 D4 IN16-1 A5 IN13-2 B5 IN14-2 C5 IN15-2 D5 IN16-2 A6 IN13-3 B6 IN14-3 C6 IN15-3 D6 IN16-3 A7 GND B7 GND C7 GND D7 GND A8 IN13-4 B8 IN14-4 C8 IN15-4 D8 IN16-4 A9 IN13-5 B9 IN14-5 C9 IN15-5 D9 IN16-5 A10 IN13-6 B10 IN14-6 C10 IN15-6 D10 IN16-6 A11 IN13-7 B11 IN14-7 C11 IN15-7 D11 IN16-7 A12 GND B12 GND C12 GND D12 GND A13 IN13-8 B13 IN14-8 C13 IN15-8 D13 IN16-8 A14 IN13-9 B14 IN14-9 C14 IN15-9 D14 IN16-9 A15 IN13-10 B15 IN14-10 C15 IN15-10 D15 IN16-10 A16 IN13-11 B16 IN14-11 C16 IN15-11 D16 IN16-11 A17 GND B17 GND C17 GND D17 GND A18 IN13-12 B18 IN14-12 C18 IN15-12 D18 IN16-12 A19 IN13-13 B19 IN14-13 C19 IN15-13 D19 IN16-13 A20 IN13-14 B20 IN14-14 C20 IN15-14 D20 IN16-14 A21 IN13-15 B21 IN14-15 C21 IN15-15 D21 IN16-15 A22 GND B22 GND C22 GND D22 GND A23 Spare B23 Spare C23 Spare D23 Spare A24 +3.3V B24 +3.3V C24 +3.3V D24 +3.3V A25 RF-CLK B25 GND C25 BC-CLK D25 GND 21

MTFB Connector P5 Pin Label Pin Label Pin Label Pin Label A1 +5V B1 +5V C1 +5V D1 +5V A2 GND B1 GND C2 GND D2 GND A3 OTB1 B3 OTB10 C3 OTB19 D3 OTB28 A4 OTB2 B4 OTB11 C4 OTB20 D4 OTB29 A5 OTB3 B5 OTB12 C5 OTB21 D5 OTB30 A6 OTB4 B6 OTB13 C6 OTB22 D6 OTB31 A7 OTB5 B7 OTB14 C7 OTB23 D7 OTB32 A8 OTB6 B8 OTB15 C8 OTB24 D8 OTB33 A9 OTB7 B9 OTB16 C9 OTB25 D9 OTB34 A10 OTB8 B10 OTB17 C10 OTB26 D10 OTB35 A11 OTB9 B11 OTB18 C11 OTB27 D11 OTB36 A12 +5V B12 +5V C12 +5V D12 +5V A13 GND B13 GND C13 GND D13 GND A14 SD1 B14 SD5 C14 SD9 D14 SD13 A15 SD2 B15 SD6 C15 SD10 D15 SD14 A16 SD3 B16 SD7 C16 SD11 D16 SD15 A17 SD4 B17 SD8 C17 SD12 D17 SD16 A18-12V B18-12V C18-12V D18-12V A19 GND B19 GND C19 GND D19 GND A20 RF-CLOCK B20 GND C20 BC-CLOCK D20 GND A21 NCE1 B21 NCE2 C21 NCE3 D21 NCE4 A22 INIT B22 GAP C22 1 st _XING D22 SYNCH-GAP A23 1 st _CLOCK B23 DAV C23 TOR D23 START A24 GND B24 GND C24 GND D24 GND A25 NCONFIG B25 NSTATUS C25 DCLOCK D25 ECLOCK A26 DATA0 B26 CONF C26 D26 EDATA A27 TDI B27 TDO C27 TCK D27 TMS A28 INT_D0 B28 INT_D1 C28 INT_D2 D28 INT_D3 A29 INT_D4 B29 INT_D5 C29 INT_D6 D29 INT_D7 A30 INT_READ B30 INT_WR C30 EN-A D30 EN-B A31 GND B31 GND C31 GND D31 GND A32 INT_A0 B32 INT_A1 C32 INT_A2 D32 INT_A3 A33 INT_A4 B33 INT_A5 C33 INT_A6 D33 INT_A7 22

Pin Label Pin Label Pin Label Pin Label A34 GND B34 GND C34 GND D34 GND A35 NCE5 B35 NCE6 C35 NCE7 D35 NCE8 23

MTFB Connector P6 Pin Label Pin Label 1 TP1 2 TP2 3 TP3 4 TP4 5 GND 6 GND 7 TP5 8 TP6 9 TP7 10 TP8 11 GND 12 GND 13 TP9 14 TP10 15 TP11 16 TP12 17 TP13 18 TP14 19 TP15 20 TP16 21 GND 22 GND 23 TP17 24 TP18 25 TP19 26 TP20 27 TP21 28 TP22 29 TP23 30 TP24 31 GND 32 GND 33 TP25 34 TP26 35 TP27 36 TP28 37 GND 38 GND 39 NCE_OUT 40 GND 24

Description of Pins IN1-[0..15] through IN16-[0..15] - Deserialized serial daughter card inputs RF-CLK 53 MHz accelerator clock START Start signal (Clock slice 6 of 6) OTB[1..36] Output Trigger Decision SD[1..16] Supplemental Data BC-CLOCK Bunch Crossing Clock INIT Initialize GAP Gap 1 st _XING First Crossing SYNCH-GAP Synch Gap 1 st _CLOCK -?? DAV - Data Available TOR -?? NCONFIG, NSTATUS, DCLOCK, DATA0, CONF - FPGA Download Signals NCE[1..8] - FPGA Download Signals (These enable each FPGA) ECLOCK, EDATA Serial EPROM Download Lines TDI, TDO, TCK, TMS JTAG Download Lines INT_D[0..7] - Internal Data Lines INT_A[0..7] - Internal Address Lines INT_READ, INT_WR - Internal Read and Write 25

8 Appendix C CF MTC10 FPGA I/O FPGA Name Signal Name Signal Description Line Description A CENT INPUTS PDTA1 A-Layer PDT hits 16 lines x 6 strobes = 96 hits PDTA2 A-Layer PDT hits 16 lines x 6 strobes = 96 hits PDTA3 A-Layer PDT hits 16 lines x 6 strobes = 96 hits CMSCA1 APHI counters 16 lines x 6 strobes = 45 hits CMSCA2 APHI counters 16 lines x 6 strobes = 45 hits CLOCK 53 MHz accelerator clock 1 line START Clock which strobes during the last of the seven 18.8ns ticks which make up the 132 ns bunch crossing. This signal is used to latch data. 1 line OUTPUTS A1 A-centroids(1-96) 16 lines x 6 strobes = 96 cents A2 A-centroids(97-144) 8 lines x 6 strobes = 48 cents Total of 144 A-centroids B CENT INPUTS PDTB1 B-layer PDT hits 16 lines x 6 strobes = 48 hits PDTB2 B-layer PDT hits 16 lines x 6 strobes = 72 hits PDTB3 B-layer PDT hits 16 lines x 6 strobes = 72 hits PDTB4 B-layer PDT hits 16 lines x 6 strobes = 72 hits PDTB5 B-layer PDT hits 16 lines x 6 strobes = 48 hits CMSCA1 CMSCA2 CLOCK START See above See above See above See above OUTPUTS B1 B-centroids(1-96) 16 lines x 6 strobes = 96 cents B2 B-centroids(97-192) 16 lines x 6 strobes = 96 cents B3 B-centroids(193-208) 8 lines x 6 strobes = 16 cents Total of 208 B-centroids C CENT INPUTS PDTC1 C-layer PDT hits 16 lines x 6 strobes = 72 hits PDTC2 C-layer PDT hits 16 lines x 6 strobes = 72 hits PDTC3 C-layer PDT hits 16 lines x 6 strobes = 72 hits PDTC4 C-layer PDT hits 16 lines x 6 strobes = 72 hits PDTC5 C-layer PDT hits 16 lines x 6 strobes = 72 hits CMSCC CPHI counters(cosmic cap) 16 lines x 6 strobes = 40 hits CLOCK See above START See above OUTPUTS C1 C-centroids(1-96) 16 lines x 6 strobes = 96 cents C2 C-centroids(97-192) 16 lines x 6 strobes = 96 cents C3 C-centroids(193-240) 8 lines x 6 strobes = 48 cents Total of 240 C-centroids 26

TRIG1 INPUTS A1 A-cent(1-96) from A CENT 16 lines x 6 strobes = 96 cents B1 B-cent(1-96) from B CENT 16 lines x 6 strobes = 96 cents B2 B-cent(97-192) from B CENT 16 lines x 6 strobes = 96 cents C1 C-cent(1-92) from C CENT 16 lines x 6 strobes = 96 cents C2 C-cent(97-192) from C CENT 16 lines x 6 strobes = 96 cents CLOCK START See above See above OUTPUTS ACENT[4..1] A-cents(1-48) or d by 12 4 bits A 2-bit counter for A-cent trig 2 bits AB.or.AC 2-bit counter for ABAC trig 2 bits AB.or.AC.or.BC 2-bit counter for ABACBC trig 2 bits TRIG2 INPUTS A1 A-cent(1-96) from A CENT 16 lines x 6 strobes = 96 cents B1 B-cent(1-96) from B CENT 16 lines x 6 strobes = 96 cents B2 B-cent(97-192) from B CENT 16 lines x 6 strobes = 96 cents C1 C-cent(1-92) from C CENT 16 lines x 6 strobes = 96 cents C2 C-cent(97-192) from C CENT 16 lines x 6 strobes = 96 cents C3 C-cent(193-240) from C CENT 8 lines x 6 strobes = 48 cents CLOCK START See above See above OUTPUTS ACENT[8..5] A-cents(49-96) or d by 12 4 bits A 2-bit counter for A-cent trig 2 bits AB.or.AC 2-bit counter for ABAC trig 2 bits AB.or.AC.or.BC 2-bit counter for ABACBC trig 2 bits TRIG3 INPUTS A2 A-cent(97-144) from A CENT 8 lines x 6 strobes = 48 cents B2 B-cent(97-192) from B CENT 16 lines x 6 strobes = 96 cents B3 B-cent(193-208) from B CENT 8 lines x 6 strobes = 16 cents C1 C-cent(1-92) from C CENT 16 lines x 6 strobes = 96 cents C2 C-cent(97-192) from C CENT 16 lines x 6 strobes = 96 cents C3 C-cent(193-240) from C CENT 8 lines x 6 strobes = 48 cents CLOCK START See above See above OUTPUTS ACENT[12..9] A-cents(97-144) or d by 12 4 bits A 2-bit counter for A-cent trig 2 bits AB.or.AC 2-bit counter for ABAC trig 2 bits AB.or.AC.or.BC 2-bit counter for ABACBC trig 2 bits OCTANT SUM INPUTS A 3 2-bit counters for A trig 6 bits AB.or.AC 3 2-bit counters for ABAC trig 6 bits AB.or.AC.or.BC 3 2-bit counters for ABACBC trig 6 bits ACENT[12..1] 12 bits of or d A-centroids 12 bits START See above 27

OUTPUTS A 2-bit counter for A trig 2 bits AB.or.AC 2-bit counter for ABAC trig 2 bits AB.or.AC.or.BC 2-bit counter for ABACBC trig 2 bits ACENT[12..1] 12 bits of or d A-centroids 12 bits Table 12 - Summary of CF MTC10 FPGA Signals 28

Figure 5 A CENT Top Level Design 29

Figure 6 - A CENT Timing Diagram 30

Figure 7 - B CENT Top Level Design 31

Figure 8 B CENT Timing Diagram 32

Figure 9 - C CENT Top Level Design 33

Figure 10 - C CENT Timing Diagram 34

Figure 11 - TRIG1 Top Level Design 35

Figure 12 - TRIG1 Timing Diagram 36

Figure 13 - TRIG2 Top Level Design 37

Figure 14 - TRIG2 Timing Diagram 38

Figure 15 - TRIG3 Top Level Design 39

Figure 16 - TRIG3 Timing Diagram 40

Figure 17 - Octant Sum Top Level Design 41

Figure 18 - Octant Sum Timing Diagram 42

Figure 19 - Super Project CF MCT10 Top Level Design 43

Figure 20 - Super Project CF MTC10 Timing Diagram 44

8 References [1] D0 Note #2780, The D0 Muon System Upgrade, January 1996. [2] K. Johns, Level 1 Muon Trigger Technical Design Report, V1.0, June 1997. [3] K. Johns and J. Steinberg, Muon Trigger Card (MTCxx): Functional Description, V1.0, September 1997. [4] Altera Flex 10K Embedded Programmable Logic Family Data Sheet, V3, January 1998, p.117. 45