Unit: I Branch: EEE Semester: IV Page 1 of 6 Unit I Syllabus: BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS 9 Boolean algebra: De-Morgan s theorem, switching functions and simplification using K-maps & Quine McCluskey method, Design of adder, subtractor, comparators, code converters, encoders, decoders, multiplexers and demultiplexers. To study number systems, Boolean switching algebra, and principles, analysis and design of Combinational logic. Time Books Teaching 1. Introduction about Digital systems, various number systems and their conversion 2. Boolean algebra: De-Morgan s theorem 3. Simplification and Design problems using Boolean Algebra, Switching Functions 4. Canonical sum of product, product of sum, simplification SOP, POS, minterms and maxterms 5. Simplification using Karnaugh maps- 3-Variable 4- Variable w/examples 6. K maps w/examples, Don t Care terms, NAND/ NOR gate implementation using K-map 7. Simplification using Quine McCluskey method 8. Simplification using Quine McCluskey method 9. Design of adders and subtractors 10. Design of Binary comparators. 11. Code converters- BCD to Binary, BCD to excess-3 12. Design of encoders, decoders. 13. Implementation using Decoder, Priority Encoder 14. Design of multiplexers and demultiplexers. 15. Function implementation using multiplexers and demultiplexers 16. Problems
Unit: II Branch: EEE Semester: IV Page 2 of 6 Unit II Syllabus: SYNCHRONOUS SEQUENTIAL CIRCUITS 9 Flip flops - SR, D, JK and T. Analysis of synchronous sequential circuits; design of synchronous sequential circuits Counters, state diagram; state reduction; state assignment.. To study the design and analysis of various synchronous sequential circuits. Time Books Teaching 17. Introduction to Sequential Circuits: Latches and Flip flops 50 2,3,4 BB using NAND and NOR gates 18. Construction of SR and D Flip Flops- Operation and Truth 50 2,3,4 BB Table 19. Construction of JK and T- Flip flop- Operation and Truth 50 2,3,4 BB Table 20. Master Slave Edge Triggered JK Flip flops, Timing 50 2,3,4 BB diagram 21. Introduction to Counters- Ripple asynchronous counter 50 2,3,4 BB using T-Flip flop- Design and working 22. Design of Mod-10, Mod-12, BCD counter. Introduction to 50 2,3,4 BB synchronous counters 23. Design, analysis of synchronous counters. Introduction to 50 2,3,4 BB Registers SISO, SIPO, PISO, PIPO. 24. Mealy and Moore Models with examples. 50 2,3,4 BB 25. State machine State diagram, transition, Excitation table 50 2,3,4 BB of various flipflops, State Equations 26. Analysis of Synchronous sequential circuits. 50 2,3,4 BB 27. Design of Synchronous sequential circuits. 50 2,3,4 BB 28. State reduction and state assignment- Design Problems 50 2,3,4 BB 29. Design Problems 50 2,3,4 BB 30. CAT 1
Unit: III Branch: EEE Semester: IV Page 3 of 6 Unit Syllabus: ASYNCHRONOUS SEQUENTIAL CIRCUIT Analysis of asynchronous sequential machines, state assignment, asynchronous design problem. To study the design of various asynchronous sequential circuits. 31. 32. Introduction to asynchronous Sequential Circuits, Modes of asynchronous operation, with examples Analysis of ASM Stable and unstable states, Races and cycles. Time (Min) Books Referred Teaching Method 50 2,4 SM/PP 50 2,4 SM/PP 33. 34. Analysis procedure Flow Table, State variables, 50 2,4 SM/PP Race-free critical and non-critical racing Asynchronous circuits using Latches 50 2,4 SM/PP 35. Problem on Asynchronous Analysis 50 2,4 SM/PP Asynchronous Design Flow table, Implication table, 50 2,4 SM/PP 36. Merger graph, Compatibility states 37. State Reduction and flow tables 50 2,4 SM/PP 38. Race-free state assignment and Hazards 50 2,4 SM/PP 39. Asynchronous Design Problem 50 2,4 SM/PP 40. Asynchronous Design Problem & Summary 50 2,4 SM/PP
Unit: IV Branch: EEE Semester: IV Page 4 of 6 Unit Syllabus: PROGRAMMABLE LOGIC DEVICES, MEMORY AND LOGIC FAMILIES Memories: ROM, PROM, EPROM, PLA, PLD, FPGA, digital logic families: TTL, ECL,CMOS. To educate the students on various memory devices, FPGA and digital logic families. Time Books Teaching 41. Introduction to Memories ROM, PROM, EPROM 50 2,3,7 SM/PP 42. Internal Circuit of ROM and types of ROM, PLD. 50 2,3,7 SM/PP 43. Implementation of Combinational circuit using PLA, 50 2,3,7 SM/PP PAL and PROM 44. Implementation of Combinational circuit using PLA- 50 2,3,7 SM/PP Examples. FPGA working principle 45. Types of digital logic families, Characteristics of each 50 2,7 SM/PP family 46. Working of RTL, DTL and TTL circuits 50 2,7 SM/PP 47. Working of TTL circuits 50 2,7 SM/PP 48. ECL and CMOS. 50 2,7 SM/PP 49. CAT II
Unit: V Branch: EEE Semester: IV Page 5 of 6 Unit Syllabus: VHDL RTL Design combinational logic Types Operators Packages Sequential circuit Sub programs Test benches. (Examples: adders, counters, flipflops, FSM, Multiplexers / Demltiplexers). To introduce digital simulation techniques for development of application oriented logic circuit. Time Books Teaching 50. Introduction to RTL Design 50 2,4 SM/BB 51. Introduction to Combinational Logic Design 50 2,4 SM/BB 52. Types Operators 50 2,4 SM/BB 53. Packages 50 2,4 SM/BB 54. Sequential circuit Design 50 2,4 SM/BB 55. Sub programs 50 2,4 SM/BB 56. Test benches 50 2,4 SM/BB 57. Programming on Adders, Subtractors 50 2,4 SM/BB 58. Programming on Comparator, MUX and DeMUX. 50 2,4 SM/BB 59. Programming on FF,Counters 50 2,4 SM/BB 60. CAT II Course Delivery plan : Week 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 I II I II I II I II I II I II I II I II I II I II I II I II I II I II I II Units 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 C A T 1 3 3 3 3 3 4 4 4 4 4 C A T 2 5 5 5 5 5 5 C A T 3
TEXT BOOKS 1. Raj Kamal, Digital systems-principles and Design, Pearson education 2 nd edition, 2007 2. M. Morris Mano, Digital Design, Pearson Education, 2006. 3. John M.Yarbrough, Digital Logic, Application & Design, Thomson, 2002. REFERENCES 4. Charles H.Roth, Fundamentals Logic Design, Jaico Publishing, IV edition, 2002. 5. Floyd and Jain, Digital Fundamentals, 8th edition, Pearson Education, 2003. 6.John F.Wakerly, Digital Design Principles and Practice, 3rd edition, Pearson Education, 2002. 7. Tocci, Digital Systems: Principles and applications, 8th Edition Pearson Education Prepared by Approved by Signature Name Designation Dr.KR.SANTHA Dr.SUDHAKAR K BHARATAN Associate Processor/EE AP/EE Dr.KR.Santha HOD-EE Date 2.1.2014 2.1.2014 Reason for Revision : Usage of SMART board/ Power point.