ECE 545 igital System esig with VHL Lecture A igital Logic Reresher Part A Combiatioal Logic Buildig Blocks Cot. Problem 2 What is a size o ROM with a 4-bit address iput ad a 8-bit data output? What is a size o ROM with a m-bit address iput ad a -bit data output? 2 Read Oly Memory (ROM) Implemetig Arbitrary Combiatioal Logic Usig ROM X4 X3 X2 X X Y X5 X4 X3 X2 X Y m AR ROM OUT X AR OUT 5 ROM Y 3 4 Problem 2 Show how to implemet a 33 squarer, implemetig equatio y = 2, usig ROM (diagram + cotets o ROM). Problem 22 Show how to implemet Full Adder usig ROM (diagram + cotets o ROM) 5 6
Full-Adder cout s 2 FA y + y + ci = ( cout s )2 ci Problem 23 What is a uctio o a tri-state buer? y ci cout s y ci s cout 7 8 Tri-state Buer Four types o Tri-state Buers e e e (a) A tri-state buer e = (a) (b) e Z Z e = (b) Equivalet circuit e e (c) Truth table (c) (d) 9 uotiet ad remaider Give itegers a ad, > $! q, r Î Z such that q quotiet r remaider (o a divided by ) a = q + r ad r < q = a = a div r = a - q = a a = = a mod Rules o additio, subtractio ad multiplicatio modulo a + b mod = ((a mod ) + (b mod )) mod a - b mod = ((a mod ) - (b mod )) mod a b mod = ((a mod ) (b mod )) mod 2 2
Problem 24 Eplai how to perorm the ollowig operatios A. Z = X+Y mod 2 4 B. Z = X*Y mod 2 4 usig a 4-bit adder with carry i (ci) ad carry out (cout), ad a 44 multiplier, respectively, where X, Y, ad Z are 4-bit variables. 3 4 Z = X+Y mod 2 4 Z = X*Y mod 2 4 5 6 Problem 25 Eplai how to perorm the ollowig operatio usig simple arithmetic ad logic circuits: Y = (X*(2X + )) mod 2 4, where X ad Y are 4-bit variables. Y = (X*(2X + )) mod 2 4 7 8 3
Problem 26 What is a dierece betwee a adder, hal-adder, ad ull-adder? Sigle-Bit Adders Hal-adder Adds two biary (i.e. -bit) iputs A ad B Produces a sum ad carryout Problem: Caot use it aloe to build larger adders Full-adder Adds three biary (i.e. -bit) iputs A, B, ad carryi Like hal-adder, produces a sum ad carryout Allows buildig M-bit adders (M > ) Simple techique Coect Cout o oe adder to Ci o the et These are called ripple-carry adders 9 2 Hal-Adder Full-Adder c s 2 HA + y = ( c s )2 y cout s 2 FA y + y + ci = ( cout s )2 ci y c s y ci cout s ci y cout s 2 22 6-bit Usiged Adder 6 6 Multi-Bit Ripple-Carry Adder A 6-bit ripple-carry adder is composed o 6 (-bit) ull adders Iputs: 6-bit A, 6-bit B, -bit carry i (set to zero i the igure below) Outputs: 6-bit sum S, -bit carry out Other multi-bit adder structures ca be studied i ECE 645 Computer Arithmetic Cout X + S Y Ci 6 23 Called a ripple-carry adder because carry ripples rom oe ull-adder to the et. Critical path is 6 ull-adders. 24 4
5 Problem 27 Show how to implemet Full Adder usig 8-to- multipleers oly y cout s ci 25 26 Problem 27 Show how to implemet Full Adder usig two 4-to- multipleers ad iverters oly y cout s ci 27 28 Problem 28 Show how to implemet Full Adder usig two 2-to- multipleers ad a miimum umber o logic gates y cout s ci 29 3
Comparator Used two compare two M-bit umbers ad produce a lag (M >) Iputs: M-bit iput A, M-bit iput B Output: -bit output lag idicates coditio is met idicates coditio is ot met Ca compare: >, >=, <, <=, ==, etc. Problem 29 Show how to implemet 4-bit comparator A==B usig miimum umber o logic gates A B M M A > B? i A > B i A <= B 3 32 4-bit comparator (A == B) A B 4 4 A == B? i A == B i A!= B ECE 545 igital System esig with VHL Lecture B igital Logic Reresher Part B Sequetial Logic Buildig Blocks 33 34 Lecture Roadmap Sequetial Logic Sequetial Logic Buildig Blocks Flip-Flops, Latches Registers, Shit Registers Couters RAM Tetbook Reereces Sequetial Logic Review Stephe Brow ad Zvoko Vraesic, Fudametals o igital Logic with VHL esig, 2 d or 3 rd Editio Chapter 7 Flip-lops, Registers, Couters, ad a Simple Processors (7.3-7.4, 7.8-7. oly) OR your udergraduate digital logic tetbook (chapters o sequetial logic) 35 36 6
Problem What is a dierece betwee combiatioal logic ad sequetial logic? Sequetial Logic Buildig Blocks some slides modiied rom: Brow ad Vraesic, Fudametals o igital Logic with VHL esig, 2d Editio S. adamudi, Fudametals o Computer Orgaizatio ad esig 37 38 Itroductio to Sequetial Logic Output depeds o the curret iput ad the iteral state Past iputs eects the iteral state Sequetial circuits cosist typically o Storage elemets (lip-lop, latch, register, RAM, etc.) Combiatioal logic Itroductio (cot d) Mai compoets o a typical sychroous sequetial circuit (sychroous = uses a clock to keep circuits i lock step) INPUT PRESENT STATE S(t) COMBINATIONAL LOGIC STATE-HOLING STORAGE ELEMENTS (e.g. FLIP-FLOPS) OUTPUT NEXT STATE S(t+) CLOCK 39 4 Problem 2 What is a dierece betwee Latches ad Flip-lops? State-Holdig Memory Elemets Latch versus Flip Flop Latches are level-sesitive: wheever clock is high, latch is trasparet Flip-lops are edge-sesitive: data passes through (i.e. data is sampled) oly o a risig (or allig) edge o the clock Latches cheaper to implemet tha lip-lops Flip-lops are easier to desig with tha latches I this course, primarily use lip-lops 4 42 7
Latch vs. Flip-Flop latch Graphical symbol Truth table (t+) (t) Latch trasparet whe clock is high Timig diagram t t 2 t 3 t 4 Samples o risig edge o clock Time 43 44 lip-lop Graphical symbol Truth table Clk (t+) (t) (t) Timig diagram Problem 3 What is a dierece betwee: a. Reset active high vs. Reset active low b. Asychroous Reset vs. sychroous Reset? t t 2 t 3 t 4 Time 45 46 Flip-Flop with Asychroous Set ad Reset Flip-Flop with Sychroous Reset Set Reset Bubble o the symbol meas active-low Whe Set =, set to Whe Set =, do othig Whe Reset =, set to Whe Reset =, do othig Set ad Reset also kow as Preset ad Clear respectively I this circuit, Set ad Reset are asychroous chages immediately whe preset or clear are active, regardless o clock Reset Clear Reset (asychroous Reset) (sychroous Reset) Asychroous active-low Reset: immediately clears to Sychroous active-low Reset: clears to o risig-edge o clock 47 48 8
Problem 4 What is a register? Register (3) (3) (2) (2) 4 4 () () () () 49 I typical omeclature, a register is a ame or a collectio o lip-lops used to hold a bus All lip-lops o a register share the same clock ad cotrol sigals 5 Shit Register Si 3 2 Sout Problem 5 raw a symbol o a Clk Shit Register Clk Si Sout t t 2 t 3 t 4 t 5 t Si 3 2 Sout= a. 4-bit Shit Register with Eable, shitig to the right, with Serial Iput ad Serial Output oly a. 4-bit Shit Register with Eable, shitig to the right, with Parallel Load, ad Parallel Output t 6 t 7 5 52 4-bit Shit Registers: symbols a) Eable Si Sout Clk b) 4 Eable Load Si Clk 4 Problem 6 raw a block diagram o a a. 4-bit Shit Register with Eable, shitig to the right, with Serial Iput ad Serial Output oly a. 4-bit Shit Register with Eable, shitig to the right, with Parallel Load, ad Parallel Output 53 54 9
Shit Register with Serial Iput ad Serial Output Shit Register with Parallel Load ad Parallel Output Load Si (3) (2) () Sout=() (3) Si (2) () () Eable E E E E Eable (3) (2) () () 55 56 Sychroous Up Couter eable load 2 3 clk Eable (sychroous): whe high eables the couter, whe low couter holds its value Load (sychroous) : whe load =, load the desired value ito the couter Output carry: idicates whe the couter rolls over 3 dowto, 3 dowto is how to iterpret MSB to LSB carry 2 3 57 Problem 7 raw a block diagram o the digital circuit with the ollowig iterace ad uctioality: Iterace: i 8-bit data iput out 8-bit data output Addr 2-bit address o the locatio (register) where iput data is stored or output data is read rom RW cotrol sigal, =read, =write Clk clock 58 Problem 7 (cot.) Fuctioality: I RW = (write), the the output out is set to the high impedace state, ad at the et risig edge o the clock, data rom the iput i is stored i the iteral locatio give by the address Addr. I RW = (read), data rom the locatio give by the address Addr is traserred to the output out, ad the cotets o the iteral memory (registers) does ot chage. Problem 7 (cot.) Assume that the iteral memory is implemeted usig registers. Use oly medium scale compoets, such as registers, multipleers, ecoders, decoders, buers, etc. 59 6
Problem 8 What is a dierece i terms o the required iputs ad outputs betwee ROM ad RAM o the same size (e.g. 2 m )? 6 Radom Access Memory (RAM) More eiciet tha registers or storig large amouts o data Ca read ad write to RAM Addressable memory RAM dimesios are: (umber o words) (bits per word) Address is m bits, data is bits 2 m -bit RAM Eample: address is 5 bits, data is 8 bits 32 8 RAM Write Eable (WE) Whe set, writig takes place at the et risig edge o the clock m IN AR WE RAM OUT 62 Problem 9 raw a block diagram showig how to build 256 RAM out o our 64 RAMs. 63 64 Problem What is a dierece betwee a) RAM with asychroous read ad b) RAM with sychroous read? 65 66
Problem What is a value at the output o RAM with sychroous read durig a write operatio? Block RAM Waveorms REA_FIRST mode 67 68 Block RAM Waveorms WRITE_FIRST mode Block RAM Waveorms NO_CHANGE mode 69 7 Problem 2 What is a dierece betwee a sigle-port ad dual-port RAM? What operatios are allowed i the dual-port RAM? ual-port RAM Two sets o iput ports {INA, ARA, WEA} {INB, ARB, WEB} Two correspodig outputs OUTA OUTB Oe memory matri Possible operatios: Read rom two memory locatios Write to two dieret memory locatios Read rom a memory locatio ad write to a memory locatio (dieret or the same) m m INA ARA WEA INB ARB WEB RAM OUTA OUTB 7 72 2