Project Design. Eric Chang Mike Ilardi Jess Kaneshiro Jonathan Steiner

Similar documents
Overview. Teacher s Manual and reproductions of student worksheets to support the following lesson objective:

Experiment 7: Bit Error Rate (BER) Measurement in the Noisy Channel

Sequential Logic Notes

BER MEASUREMENT IN THE NOISY CHANNEL

Optimization of Multi-Channel BCH Error Decoding for Common Cases. Russell Dill Master's Thesis Defense April 20, 2015

Objectives. Combinational logics Sequential logics Finite state machine Arithmetic circuits Datapath

MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences

Graduate Institute of Electronics Engineering, NTU Digital Video Recorder

Solution to Digital Logic )What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it,

CSE140L: Components and Design Techniques for Digital Systems Lab. CPU design and PLDs. Tajana Simunic Rosing. Source: Vahid, Katz

Part 4: Introduction to Sequential Logic. Basic Sequential structure. Positive-edge-triggered D flip-flop. Flip-flops classified by inputs

Graphing Your Motion

TV Synchronism Generation with PIC Microcontroller

16-Bit DSP Interpolator IC For Enhanced Feedback in Motion Control Systems

Hugo Technology. An introduction into Rob Watts' technology

Press Publications CMC-99 CMC-141

2. Logic Elements and Logic Array Blocks in the Cyclone III Device Family

FPGA Laboratory Assignment 4. Due Date: 06/11/2012

Setting Up the Warp System File: Warp Theater Set-up.doc 25 MAY 04

Cyclone II EPC35. M4K = memory IOE = Input Output Elements PLL = Phase Locked Loop

ONE SENSOR MICROPHONE ARRAY APPLICATION IN SOURCE LOCALIZATION. Hsin-Chu, Taiwan

C8000. switch over & ducking

Department of Electrical & Electronic Engineering Imperial College of Science, Technology and Medicine. Project: Real-Time Speech Enhancement

UNIVERSITY OF TORONTO JOÃO MARCUS RAMOS BACALHAU GUSTAVO MAIA FERREIRA HEYANG WANG ECE532 FINAL DESIGN REPORT HOLE IN THE WALL

Logic Design II (17.342) Spring Lecture Outline

EECS150 - Digital Design Lecture 12 - Video Interfacing. Recap and Outline

Sound Creation Tool FWCTRL Operation Manual

AND-TFT-64PA-DHB 960 x 234 Pixels LCD Color Monitor

SREV1 Sampling Guide. An Introduction to Impulse-response Sampling with the SREV1 Sampling Reverberator

Power Supply and Watchdog Timer Monitoring Circuit ADM9690

Flip-Flops. Because of this the state of the latch may keep changing in circuits with feedback as long as the clock pulse remains active.

BEMC electronics operation

Full Disclosure Monitoring

Quick Start for TrueRTA (v3.5) on Windows XP (and earlier)

Flip Flop. S-R Flip Flop. Sequential Circuits. Block diagram. Prepared by:- Anwar Bari

Performing a Measurement/ Reading the Data

Microprocessor Design

cs281: Introduction to Computer Systems Lab07 - Sequential Circuits II: Ant Brain

Noise Detector ND-1 Operating Manual

GREAT 32 channel peak sensing ADC module: User Manual

Lab experience 1: Introduction to LabView

COMPOSITE VIDEO LUMINANCE METER MODEL VLM-40 LUMINANCE MODEL VLM-40 NTSC TECHNICAL INSTRUCTION MANUAL

R3B Si TRACKER CABLE TEST REPORT

802DN Series A DeviceNet Limit Switch Parameter List

TIME RESOLVED XAS DATA COLLECTION WITH AN XIA DXP-4T SPECTROMETER

Acoustic Measurements Using Common Computer Accessories: Do Try This at Home. Dale H. Litwhiler, Terrance D. Lovell

INTEGRATED CIRCUITS DATA SHEET. TDA4510 PAL decoder. Product specification File under Integrated Circuits, IC02

TSIU03, SYSTEM DESIGN. How to Describe a HW Circuit

Digital Electronics II 2016 Imperial College London Page 1 of 8

Advanced Techniques for Spurious Measurements with R&S FSW-K50 White Paper

Chapter 5 Flip-Flops and Related Devices

Digital Signal Processing Laboratory 7: IIR Notch Filters Using the TMS320C6711

Model 4455 ASI Serial Digital Protection Switch Data Pack

Solutions to Embedded System Design Challenges Part II

Report. Digital Systems Project. Final Project - Synthesizer

CONVOLUTIONAL CODING

Experiment # 4 Counters and Logic Analyzer

LOW POWER DIGITAL EQUALIZATION FOR HIGH SPEED SERDES. Masum Hossain University of Alberta

AES-402 Automatic Digital Audio Switcher/DA/Digital to Analog Converter

Oscilloscope Guide Tektronix TDS3034B & TDS3052B

LabView Exercises: Part II

Contents. xv xxi xxiii xxiv. 1 Introduction 1 References 4

Switching Solutions for Multi-Channel High Speed Serial Port Testing

2. AN INTROSPECTION OF THE MORPHING PROCESS

Agilent DSO5014A Oscilloscope Tutorial

CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam

EEM Digital Systems II

CS8803: Advanced Digital Design for Embedded Hardware

TROUBLESHOOTING DIGITALLY MODULATED SIGNALS, PART 2 By RON HRANAC

OPERATING GUIDE. HIGHlite 660 series. High Brightness Digital Video Projector 16:9 widescreen display. Rev A June A

Application Note AN-708 Vibration Measurements with the Vibration Synchronization Module

SC26 Magnetic Field Cancelling System

Application Note #63 Field Analyzers in EMC Radiated Immunity Testing

Reducing tilt errors in moiré linear encoders using phase-modulated grating


Model 5240 Digital to Analog Key Converter Data Pack

Micro/Junior/Pro PL7 Micro PLC Functions Upcounting. TLX DS 37 PL7 40E engv4

MBI5050 Application Note

The reduction in the number of flip-flops in a sequential circuit is referred to as the state-reduction problem.

DP1 DYNAMIC PROCESSOR MODULE OPERATING INSTRUCTIONS

Limitations of a Load Pull System

Quartzlock Model A7-MX Close-in Phase Noise Measurement & Ultra Low Noise Allan Variance, Phase/Frequency Comparison

IQDEC01. Composite Decoder, Synchronizer, Audio Embedder with Noise Reduction - 12 bit. Does this module suit your application?

One of the challenges in a broadcast facility is

Using Extra Loudspeakers and Sound Reinforcement

C8491 C8000 1/17. digital audio modular processing system. 3G/HD/SD-SDI DSP 4/8/16 audio channels. features. block diagram

Introduction To LabVIEW and the DSP Board

Mastering Phase Noise Measurements (Part 3)

Chapter 11 State Machine Design

Introduction to Digital Electronics

Chrontel CH7015 SDTV / HDTV Encoder

SpikePac User s Guide

BASE-LINE WANDER & LINE CODING

Digital Design, Kyung Hee Univ. Chapter 5. Synchronous Sequential Logic

Complete 10-Bit/12-Bit, 25 MHz CCD Signal Processor AD9943/AD9944

ORDERING Page 6 BASLER RELAY STANDARDS, DIMENSIONS, ACCESSORIES Request bulletin SDA

6.111 Final Project Proposal Kelly Snyder and Rebecca Greene. Abstract

CCE900-IP-TR. User s Guide

Introduction. NAND Gate Latch. Digital Logic Design 1 FLIP-FLOP. Digital Logic Design 1

ECE 4220 Real Time Embedded Systems Final Project Spectrum Analyzer

Transcription:

Project Design Eric Chang Mike Ilardi Jess Kaneshiro Jonathan Steiner

Introduction In developing the Passive Sonar, our group intendes to incorporate lessons from both Embedded Systems and E:4986, the latter of which three of our members are currently enrolled in. Our device works by triangulating the location of a sound source along a horizontal axis by calculating the difference between the arrival times in two spaced microphones. A marker projected onto a screen will represent calculated location of the sound source. Trigonometric calculations in the form of ROM-encoded lookup tables will be used to find the location based upon the difference in the arrival times of the peak of the sound wave for any given period of time. Due to complications involved in calculating the vertical position of a sound source, we will be only able to find the position along the horizontal axis.

Abstract Our basic setup is shown on Figure 1. Two microphones are spaced a distance x apart. A sound source is located on a plane a distance l perpendicular to the plane in which the microphones are situated. A projection screen is located equidistant between the microphones. d1 and d2 represent the distance from the sound source to the respective microphones. By means of the trigonometric calculations outlined on the attached diagram, we can triangulate the horizontal position of the sound source. Process Flow Figure 2 contains a block diagram outlining at an abstract level the logical flow of our Passive Sonar. Stage 1: Analog sound signals enter the left and right microphone inputs on the audio codec, labeled A on the block diagram. Serial digital audio samples corresponding to the left and right analog inputs feed out of two digital outputs on the codec and into separate 20-bit shift registers, labeled B and C on the block diagram. Configuration pins on the codec are connected to the microblaze processor to allow for easy configuration through a software interface. Stage 2: Data from the shift registers are read into the peak detectors, labeled F and G, once an entire 20 bit word has been loaded into the shift registers. The peak detectors operate by first comparing the sample with noise constant stored in the register labeled I on the diagram. Register I is configurable through the microblaze. If the sample is above the noise constant then the peak detector is activated for a constant period of time (to be determined by the length of a normal transient). All subsequent samples taken during this period of activation are compared against the previous greatest value and the time of occurrence based upon counter H s count are stored in internal registers. At the end of the transient sample period the time of the greatest value is output to the subtractor (D in diagram) to await the signal from the inactivated peak detector. While the subtractor is waiting, that peak detector is disabled, pending peak detection of the second signal. Stage 3: The inactivated peak detector (F or G) is now awaiting the signal to break the noise threshold. The second peak detector functions exactly like the first one, storing and tagging the maximum sample value. When the second peak detector reaches the end of the transient detection period the value is sent to the subtractor. Note: the peak detectors send an extra bit (notated +1 on our diagram) along with the time to tell the subtractor whether or not it is a new word. The subtractor will only output the difference when two new words have been received.

Stage 4: The subtractor (D) receives the first sample and holds it until it receives the second sample. The extra bit coming from the peak detector governs whether the subtractor is waiting or subtracting (to send a new difference). Stage 5: Our time difference is then sent to our lookup table (J). The lookup table will be filled with an array based on the trigonometry we did in Figure 1. The time difference will represent the index of the LUT which will output information to the microblaze (K) representing the horizontal position of the sound source. Stage 6: The microblaze has final control over the VGA framebuffer. It arbitrates between the output of diagnostic data obtained from the registers and the visualization of the sound source. In addition, the registers, including those in the codec, will be configurable through a software interface controlled by the microblaze. Stage 7: Video output from the framebuffer appears on a display.

Project design issues 1) We are placing the microphones a set distance apart from each other and placing that value into a register vs. making the distance variable. This is because leaving the distance as a variable would involve leaving all the trigonometry in terms of that variable. We would then need to build a multiplier in VHDL for the LUTs, which would unnecessarily complicate the project. 2) We briefly considered designating one mic as the dominant mic, meaning it would always receive the signal before the other mic. This would simplify the code and eliminate the need for some left/right variables, loops, if statements, et cetera. But a dominant mic would limit the range of direction that the sound could come from; it would have to come from closer to the dominant mic than the other mic. 3) Initially we had the system test for sound by comparing the signal against a noise floor, or threshold. Then whichever comparator that received the signal second would test it against the same floor. There was problem of finding the range to apply to the signal received by the second mic, as the same noise heard by the second mic will not be exactly the same as the noise heard by the first mic. 4) Now we are continuously sampling the signal once it passes a noise threshold for the largest amplitude within that sample. This peak detection will be much better able to accurately detect the delay between the left and right mics. 5) Much like the human hearing system, if the system receives a signal of constant amplitude, it will be confused because the system detects the sound by peaks in the sin wave. It will detect the initial attack and then the mics will pick up the peaks in the signal, but it will not be able to distinguish which period the peak is from. So the left and right mics will read the same signal, but at different periods, instead of the same signal s peak at one period. The system will actually be reading the phase difference of the shifted sin wave (the wave received by the second mic) as the delay. This phase difference will most likely be small enough that the vertical bar shined by the projector will stay near the center. 6) The system will work best with transience/pulses, i.e. cymbals or clapping. To detect a person speaking as he walks back and forth might require the person to enunciate in an unnatural manner. A discrete sound source will be simpler to work with than a continuous source. 7) Diagram is missing multiple resets, it will basically run through one iteration.