Enhanced JTAG to test interconnects in a SoC

Enhanced JTAG to test interconnects in a SoC by Dany Lebel and Sorin Alin Herta 1 Enhanced JTAG to test interconnects in a SoC Dany Lebel (1271766) and Sorin Alin Herta (1317418) ELE-6306, Test de systèmes électroniques Département de génie électrique, École Polytechnique, Montréal (Qc) ABSTRACT: With constant evolution of smaller and faster technologies and the constant growing number of interconnects due in part to the evolution of current System on Chip (SoC), the interconnect integrity has became a new challenge to face for the test engineers. It must be included early in the design process of a component. The purpose of this document is to present an enhanced architecture of the traditional 1149.1 JTAG to test interconnect integrity. Usual cells are modified to create: 1) a test pattern generator according to the MT fault model that accurately represents integrity testing and 2) an observation unit to propagate the result to the output of the JTAG chain. New instructions need to be added to control the new functionalities included in the enhanced JTAG presented. Integrity test time has shown great improvements by the new architecture proposed at a relatively low area overhead considering the testability added to the design under test. Index Terms: boundary scan, DUT, fault model, integrity testing, Joint Test Action Group (JTAG), MA, MT, SoC, I. INTRODUCTION With newer technologies, interconnects (especially in SoC) has shown signal integrity defaults. Integrity is not properly tested with the widely used stuck at fault model. In this paper will be presented MA and MT fault models which are better suited f or integrity testing. An evolution of the current JTAG 1149.1 [1] to test interconnects is presented as the main topic of this paper. This paper is a literature review on the topic mainly focused on ref. [2]. The rest of the paper is described as follow. Section II gives a brief overview of the integrity of an electric signal. Section III presents Maximum Aggressor (MA), Multiple Transition (MT) and exhaustive fault models. Then, section IV details the enhanced JTAG by describing the cells and instructions involved. Section V presents experimental results achieved from ref. [2]. Finally, section VI will briefly conclude this paper. II. INTEGRITY DEFINITION An interconnect problem is mainly shown as a lack of integrity of the signal. So, it becomes obvious a brief review of signal integrity is due. The integrity of a signal is represented with two elements. Firstly, the values at the receiving end of interconnect need to be exact compared to the expected value. Therefore, no significant noise was added to the signal while passing through interconnect. Secondly, the delay to obtain the expected result is acceptable, meaning that the environment did not cause an unacceptable delay on interconnect under test. The coupling capacity and the mutual inductance of surrounding signals affect the integrity of a signal by adding some noise and some extra delays to the interconnect tested. Thus, integrity problems are very likely to happen on interconnects used to connect SoC. In those areas, there is mostly a great amount of interconnect wires which are known to be significantly long. It is of great importance for a SoC design company to pay attention to the interconnect integrity since the effects of such problems are not obvious to detect with usual production tests. The integrity loss effects are usually a shortened life length and intermittent functionality errors. Those effects tend to be detected once the component is owned by the customer. Since an error detected at that phase is very costly for a company, testing the integrity of interconnects is an important step in delivering a quality and reliable product. Since the integrity error is expressed as the effect from surrounding signals, it becomes obvious that the usual stuck at fault model is not sufficient for this application. Fault models more adapted to the integrity of a signal are presented in section III. Integrity testing can be compared to analog testing in the sense that an acceptable delay for each specific interconnect has to be defined. This represents a non binary threshold for the fail decision. It indicates that the configuration of the SoC must be known and it becomes a white box test strategy. III. FAULT MODELS There are two models suited for integrity loss testing, the Multiple Aggressors (MA) and Multiple Transitions (MT) models. The simpler model named MA is usually used for crosstalk analysis. Fig.1 shows that the victim signal on line V can be affected by the signals transitions on aggressor line(s) (A signal) near the victim. Z is a coupling component used to represent the coupling effect between the victim and aggressor line(s). MA model is based on C coupling only. When mutual inductance appears, it has been shown that MA doesn t reflect the worst case [3]. Fig. 1: Signal Integrity fault model

Enhanced JTAG to test interconnects in a SoC by Dany Lebel and Sorin Alin Herta 2 In order to have a maximal ringing with the MA model, the victim line is set quiescent and all the aggressors make simultaneous transitions in the same direction. When it is desired to have a maximal delay in MA model, the victim line and aggressor line(s) make(s) an opposite transition. Fig.2 shows the test patterns for detecting faults according to MA model. One of the most important cases not covered by MA is when the aggressor lines on one side of the victim is changed in one direction and the other aggressors (on the other side of interconnect) are set with transitions in the opposite direction. This would be the worst case scenario [3]. middle and beside the six aggressors. The patterns chosen for MT model are: 1) 0110110 -> 1001001, 2) 0110101 -> 1001010. For MA model, the pattern is: 1110111 -> 0001000. Fig. 4: Integrity delay comparison with MA and MT models Fig. 2: MA fault model and test patterns Generating exhaustive and pseudorandom patterns used to cover exhausting testing shows that there are some cases where aggressors are in quiescent mode and in this situation, they do not maximally affect the victim line for noise and delay. Those tests can be put aside. Fig. 3 shows a more complete Multiple Transition (MT) fault model example with three interconnects. The middle signal is the victim, while the two surrounding ones are aggressors. This better fault model for integrity covers all transitions on victim and multiple transitions on aggressors. MT has a single victim and a limited number of aggressors. All cases tested on victims (2 quiescent and 2 transitions per victim as shown in fig. 4) and only a subset of possible transitions on the aggressors. Cases which are known not to be pathologic such as when aggressors are constant are leaved. The maximum delay is created with MT patterns having a transition time between 35 and 70 ps more than MA. When inductance is included, the MA model is not able to generate the maximum of noise/delay on the victim line with it s generated vector. When the victim is between two aggressors, there are four cases, two with victim line kept quiescent at 0 or 1 and two with transitions of victim line from 0 to 1 and from 1 to 0. Four cases on the victim are thus tested for each victim. Each case is tested for multiple aggressor transitions (2 m-1 ). The minus one comes from the fact that we do not cover the victim among the aggressors test pattern. The number of test patterns for a group of m interconnects is therefore Np=m*4*2 m-1, m being the number of interconnect to test. Each signal is tested as a victim. Based on this formula the time will increase exponentially with the number of interconnects. The number of surrounding aggressor lines used needs to be kept minimal to improve the test time. We define k as a local factor which determines how many aggressor(s) have an impact on a victim line based on a threshold established by the precision needed. Fig. 3 : MT fault model and test patterns There are some important differences between MT and MA models. MT is a complete model containing all worst cases for integrity, MA model being just a subset of those transitions from MT represented as the shaded cells in Fig. 3. Another important difference is double direction change of aggressors in MT versus single direction change in MA model. Because the quiescent cases of aggressors lines for which integrity loss will not be maximal do not need to be taken in consideration, the MT model is not an optimized model. Fig.4 shows a case in which the fault models are applied on a seven interconnect system that contains a victim line in the Fig. 5 : Simulation results for different number of aggressor lines (k) Fig. 5 shows a simulation in which the number of aggressor(s) considered will change from k=1 to k=5 to find how the victim line is impacted when kept quiescent at 0 while Vdd=1.8V. The peak noise difference which corresponds to two local factors k=3 and k=4 is: Vpeak(k=4) Vpeak(k=3)=0.048V. This difference is minimal for many applications. I this case the local factor k of 3 can be used. This value of k set to 3 is dependent of technology and application. The choice of local

Enhanced JTAG to test interconnects in a SoC by Dany Lebel and Sorin Alin Herta 3 factor k will be based on a tradeoff between longer simulation time and accuracy. IV. EXTENDED JTAG Some modifications to JTAG 1149.1 standard are proposed for interconnect testing [2], [5]. Two new modules to replace the usual BSC cell are presented. The first one is used as a test pattern generator and the second one, as an integrity observation (or decision we shall say). A. New JTAG cells 1) Generation cell (PGBSC): the first optimization presented is the creation of a new modified BSC cell that can generate the test vectors needed to cover our MT fault model. Having a module that generates all the vectors would just be the best for performance but might be costly as well. The approach presented in this document allows us to load only some seeds through the scan chain instead of all the vectors with an adaptation of the original BSC. Therefore, it helps to get closer to the test at clock speed ultimate target. Each seed is able to generate multiple test vectors. The number of seed to enter depends of k, the number of interconnects considered for the integrity of a tested victim. In Fig. 5 are presented a reorganization of the faults of Fig. 3 again for a three interconnects aggressor/victim (A/V) pattern. It produces a regular pattern on each line that can be regenerated in time with a proper seed. It must be noted that in the end of each line, the vector goes back to the original seed. Through each line, we can see that the victim line changes every two clocks and the aggressor line, at every clock. This is the base of the simplicity of the hardware implementation. To avoid reloading the seed often and since the sequence goes back to the original seed, it is a good approach to test one seed for all the A/V test patterns and then, start over with the next seed loaded until all the necessary seeds are tested. Fig. 5 : Reorganization of MT fault model for HW implementation In terms of hardware, to produce patterns that update every clock or every two clocks depending if the current cell is an aggressor or a victim means we have to divide the frequency of the original clock by two. The patterns of the clock signals are presented in Fig. 6. Fig. 6 : Clock used on interconnect depending on V/A The total number of seeds for a test situation of m interconnects will be Ns=m*2 m-1 =(2k+1)*2 2k in which 2 m-1 shows all the possible combinations of m-1 aggressor lines and k is the number of interconnects surrounding the victim considered. Each interconnect can act as a victim or an aggressor. One interconnect is tested as a victim now and then in the next test session can be tested as aggressor. The victim will propagate through interconnects for complete interconnect testing. The local factor k will decide how many interconnects test can we do in parallel. With a local factor k of 2, the victim selection pattern for a n-bit interconnect system is shown in Table I. The sequence sent to PGBSCs cells will start with a victim and then two 2 aggressors for the first set of interconnects and so on for the following interconnects. Intuitively, the number of victim lines tested in parallel can be found to be [n/(k+1)]. Table 1 :Victim selection pattern in an n-bit interconnect when k = 2 Victim location Victime sel data VAAVAA.VAA 100100.100 AVAAVAA VA 0100100.10 AAVAAVAA.V 00100100.1 Fig. 7 shows the hardware implementation of the new PGBSC cell. The shaded part represents the hardware added to the original design of the BSC. We can note it only needs one new input signal (SI). The seed is previously loaded with the scan chain in FF1 which is sent to FF2 before to begin the test. The A/V pattern is then inserted in the flip-flop FF1 by successive shifts form the test input TDI. Q1 which is the victim/aggressor (V/A) pattern is later shifted to the next PGBSC cell with the scan chain when a seed is completely finished for the current V/A pattern (4 clocks for MT model). Since the seed is given back at the end, we effectively do not need to reload it. When a seed is tested for the whole A/V pattern, the next seed needs to be charged again with the scan chain via FF1 which is then loaded in FF2. When we cover each of the lines for the MT model presented on Fig. 5, FF2 is inverted (Q2 inverted is sent back to D2) producing an opposite test vector. FF3 is a T flip-flop that can divide the clock frequency sent to FF2 by 2. The clock used is toggled with a multiplexer controlled by Q1 and SI. If not in test mode (SI = 0) or in test mode while Q1 would indicates an aggressor interconnect (Q1 = 0), the original clock is sent. If in test mode and the current

Enhanced JTAG to test interconnects in a SoC by Dany Lebel and Sorin Alin Herta 4 interconnect is set as a victim, the generated clock at half the original frequency is sent to built the fault model of Fig. 5. Fig. 9 : Propagation of the integrity value to TDO Fig. 7 : Hardware implementation of the PGBSC cell 2) Observation cell(obsc) : The second proposed cell is the one that detects the presence of an integrity problem and store the value in an output register. The value is held for the next test cycles until read and sent to the output test pin TDO. The value can be verified at a variable rate depending on test time suited and level of details regarding where is located the integrity problem (which test vector caused it?). The result capture and following shifts can be done: 1- Once all the vectors were tested for all the victims 2- After each seed for each victim/aggressor pattern 3- After each test vector is applied The first option is not costly but do not give a good level of details of the interconnect problem. The third one however is very costly but gives the exact information where the fail was found. The second option is a compromise between both. This choice can be based on some external factors like the level of confidence on the process used or the will to know the exact location of the fail for debug purposes. It also might be affected by the desired time before to observe the fail. This has an impact on the cost of the test in term of time under test. As can be seen on the hardware implementation of the OBSC cell in Fig. 8, there is only two new input signals needed with this new architecture (SI and CE). CE is used to activate/deactivate the ILS module which is the integrity sensor. SI however toggles between sending ILS s result to FF1 or sending the regular input. We can also note that shift DR has the priority on the SI pin when in shiftdr mode (scan chain shifted). Once the integrity value is loaded in FF1 by the activation of SI, the result is sent to the next OBSC cell to be propagated to TDO with shift instructions. Fig. 8 : Hardware implementation of the OBSC cell Fig. 9 shows the propagation of the result to TDO. The complete physical implementation of the Integrity Loss Sensor module is shown in Fig. 10. Essentially, the interconnect signal and its opposite value through an inverter are passed through transmission gates. The b signal generated controls the transmission gate so that its outputs are kept constants during the small interval for which b is zero. The rest of the time, the outputs are an exact replica of the input of the transmission gates (transparency mode). Once in the transparency mode, the opposite values between the two inputs of the next stage, the XNOR gate needs to be found to conclude in no integrity problem. If they are the same, the XNOR gate will detect it and send the result of 1 to the output flip-flop. Once the c signal is set to one, the output of the FF keeps track of it and keeps the value to one (we have integrity loss). This can be done with a reset flip-flop and the output of this ILS cell sent to its clock input. The flip-flop is being triggered on the rising edge of the clock. And reset would be generated by the TAP controller. This cell is in fact triggered by any unexpected delays of interconnect. Fig. 10 : Hardware details of the ILS module Some diagrams showing an example are presented on Fig. 11. On the first rising edge of the clock, at t equals 0, interconnect was fast enough but at t equal 3 ns, it is clear the interconnect reacts too slowly. The ILS would trigger the interval in which outputs of the transmission gates are the same right after b is set to 1. Acceptable delay as shown on the timing diagrams can be tuned by changing the gates delays. The acceptable Delay Region can be calculated through the following equation: ADR = t(xnor) + t(inv1) + t(nand) t(inv2)

Enhanced JTAG to test interconnects in a SoC by Dany Lebel and Sorin Alin Herta 5 The core before core i executes the BYPASS instruction to scan seeds from the system input. Broken lines in Fig.14 represent the seeds loading. At that time, the core i executes the PRELOAD instruction. The test patterns are then generated internally using the darker path in Fig.12. At the same time vectors are generated, the O-SITEST cell is activated to test for integrity with CE signal. Fig. 12 : Test data flow for the G-SITEST instruction Fig. 11 : Timing diagram of the OBSC cell Therefore, by scaling the two inverters inv1 and inv2, it is possible to tune the circuit for a specific delay. Increasing the delay of inv2 and decreasing the delay of inv1 both gives a smaller acceptable delay range and thus a better faster interconnect. This delay is sized with an odd number of inverters in series. The delay of the second inverter is usually kept easily tunable for adjustments to different interconnects and different process variation. Table 2 shows some tests that can affect the ADR. Table 2 : ADR for different inverter configurations T(INV1) [*10 t(not)] T(INV2) [*t(not)] ADR [ps] B. New Test Instructions 5 1 450 3 3 250 1 5 100 Two new instructions are defined: 1) G-SITEST to activate the new cell PGBSC to generate patterns for test and activate O-SITEST to check for integrity and 2) O-SITEST to read out the test integrity result. 1) G-SITEST Instruction: When it is used with the new enhanced boundary scan architecture, G-SITEST will generate test patterns. The PRELOAD instruction will load the seeds in BSC. Then will follow G-SITEST instruction which after being loaded in Update-IR TAP state will activate all the related signals. The signal SI=1 will activate PGBSC cells in integrity test mode as Victim or Aggressor depending of the pattern loaded in FF1 and the signal CE=1 will enable the ILS cells to capture signal integrity information. During the Shift- DR state, the victim-select data is shifted into FF1 of PGBSCs. Every Update-DR will generate pattern for MT model. To generate the three test patterns per victim needed (3 transitions to test 4 cases by seed), three Update-DR signals are generated. 2) O-SITEST Instruction: This instruction takes place after the loss information has been stored in ILS FF of OBSC cell. The role of O-SITEST is to capture and scan out the content of ILS FF. After the instruction is loaded in the Update-IR state, the control signals SI = 1 and CE = 0 (to deactivate ILS) are generated. While we run O-SITEST instruction, the ILS cell will not receive input data. Fig.13 shows the data flow in an OBSC cell (darker path again). All the cores after j might execute BYPASS instruction to scan out data to system output. Otherwise, if we want to run an integrity test on the next core as well, it would be in SHIFTDR mode. Specific conditions must be followed if we want to test more cores at the same time since the pattern generation affects the whole BSC chain. Fig.14 shows the algorithm for signal integrity test processing based on these two new instructions. Fig. 13 : Test data flow for the O-SITEST instruction Fig. 14 :Sequence of instruction for JTAG testing To scan the seed into BSCs, the PRELOAD instruction was used. When G-SITEST is loaded into the instruction register, the PGBSCs will generate patterns which are applied to the interconnects. At the receiving end of these interconnects, the ILS cells will detect any violation. The integrity loss data is recorded in ILS FF and must be read out by O-SITEST

Enhanced JTAG to test interconnects in a SoC by Dany Lebel and Sorin Alin Herta 6 instruction. This instruction deactivates the ILS cells because integrity test mode and integrity loss information propagation mode are not compatible. Before the scan-out phase is completed, new data will be scanned in if pattern generation is activated and may be applied to interconnects or cores in the Update-DR state. This can cause ILS to lose integrity-loss information sampled earlier. V. SIMULATION RESULTS The synthesis results of the described implementation obtained with design analyzer [4] is described in this section [2]. Use of the new enhanced cells (PGSBC and OBSC) compared to conventional BSC has shown the overhead area presented in Table 3. We can conclude that the enhanced cells PGBSC and OBSC are 38%-46% more costly in term of area than conventional BSC. This is not that expensive compared to the overall cost of boundary scan architecture. The control logic which is registered is known to use more area. The user also has the possibility of insert/change cells only on the interesting interconnects, thus the price in this case would be lower. The bidirectional cell which merges both PGSBC and OBSC in only one universal cell shows a smaller area overhead (28%) but the cells take much more area. It makes the cell more general at the cost of extra area. Having in mind the area overhead for test is usually kept minimal by the designers, this idea would be less interesting. Table 3 : Area cost analysis for enhanced BSC cells Test Architecture Cost [NAND] Sending Observing Bidirectional Conventional Cells 26 26 78 Enhanced Cells 36 38 100 Area Increase % 38.5 46.2 28.2 Table 4 shows the difference between the application of MT model in test using enhanced boundary scan and conventional boundary scan. We note that with increasing number of interconnects, the test is applied faster with our extended JTAG compared to the original 1149.1 JTAG. Table 4 : Application test time of MT model with original and new BSC cells Methods MT-Pattern Application Time [Cycle] (p=0) n=8 n=16 n=32 k=2 k=3 k=2 k=3 k=2 k=3 N clk_ebs 2560 17920 3840 25088 6400 39424 N clk_bs 19200 150528 32000 250880 57600 451584 Time Reduction % 86.1% 88.5% 88.3% 90.3% 88.9% 91.8% Table 5 compares how fast the three observation methods presented in section IV are. Table 5 : Observation time of MT model with the three methods Observation Test Time [Cycle] (q=0) Methods n=8 n=16 n=32 k=2 k=3 k=2 k=3 k=2 k=3 Method 1 8 8 16 16 32 32 Method 2 640 3584 1280 7168 2560 14336 Method 3 2560 14336 5120 28672 10240 57344 The method choice depends on the application. Method one is amazingly fast because it is in fact the time taken to go through the output chain only one time. Method three is however extremely expensive as we expected. It costs 320 times more than method 1 when k equals 2 and 1792 times when k equals 3. In the end, method 2 can be used as a tradeoff between the time of test and accuracy. Table 6 shows the maximum noise voltage and skew differences between MA and MT models for different local factor k. We observe an improvement in terms of integrity delay tested of up to 9.6% with MT over MA when k is 4. Also, the results are better when k equals 3 or 4. Table 6 : MT and MA comparison with different k Observation Test Time [Cycle] (q=0) k MT MA Vnoise[V] Delay[ps] Vnoise[V] Delay[ps] k=2 0.351 470.5 0.348 468.5 k=3 0.408 472.3 0.404 450.7 k=4 0.420 483.4 0.411 440.9 Overall, the new enhanced JTAG presented shows huge improvement in term of time of test at a reasonable area cost. The new model used is also more suited for integrity tests. VI. CONCLUSION The proposed MT fault model is a superset of MA model and is much more capable of testing the capacitive and inductive couplings among interconnects based on JTAG boundary-scan architecture than MA model which is only based on capacitive couplings. Hardware modifications proposed compared with the standard JTAG are: 1) new cells used for patterns generation named PGBSC, 2) modified BSC named OBSC used to observe the integrity at the receiving side of the interconnects, and 3) modifications of the TAP controller to handle two new instructions, G-SITEST and O-SITEST. This new architecture detects worst case of delay and noise integrity violations. Practically, these new cells can be used only for those long interconnects susceptible to signal integrity failures. With more A/V interconnects simultaneously involved in our test procedure, more efficient results would be obtained with our enhanced JTAG. The advantage of this proposed architecture is that it provides area cost-effective solution for optimal interconnect test using the popular JTAG standard. The performance results in terms of processing time and quality of interconnect test show a net improvement which can easily be translated to a cost effective solution for a SoC. REFERENCES [1] Joint Test Action Group (JTAG) 1149.1 documentation Available: http://www.jtag.com/ [online] [2] Mohammad H Tehranipour, Nisar Ahmed and Mehrdad Nourani, Test SoC Interconnects for signal Integrity using extended JTAG, IEEE, 2004. [3] S. Naffziger, Design methodologies for interconnects in GHz+ ICs, presented at the Int. Solid Stat Conf., 1999 [4] Synopsys design compiler description Available: http://www.synopsys.com/products/logic/design_compiler.html [online] [5] N. Ahmed, M. H. Tehranipour and M. Nourani, Extending JTAG for testing signal integrity in SoCs, 2003