Lecture : Adder Design Mark McDermott Electrical and omputer Engineering The University of Texas at Austin /9/8 EE46 lass Notes
Single-it Addition Half Adder Full Adder A A S = AÅÅ out out S out = MAJ( A,, ) S A out S A G P K out S Page 2
Full Adder Design I rute force implementation from equations S = AÅÅ out = MAJ( A,, ) A A A A A A MAJ S out S A A A out A A A Page 3
Full Adder Design II Factor S in terms of out S = A + (A + + )(~out) ritical path is usually to out in ripple adder MINORITY A out S S out Page 4
Layout lever layout circumvents usual line of diffusion Use wide transistors on critical path Eliminate output inverters Page 5
Full Adder Design III omplementary Pass Transistor Logic (PL) Slightly faster, but more area Requires true and complement signals There is some signal degradation through the pass transistors. ross coupled PMOS devices are used to restore logic levels. A S out A A S out A Page 6
Ripple arry Adder Simplest design: cascade full adders ritical path goes from in to out Design full adder to have fast carry delay A 4 4 A 3 3 A 2 2 A out 3 2 S 4 S 3 S 2 S in Page 7
Use Inversions to speed up arry Path ritical path passes through majority gate uilt from minority + inverter Eliminate inverter and use inverting full adder A 4 4 A 3 3 A 2 2 A out in 3 2 S 4 S 3 S 2 S Page 8
arry Propagate Adders N-bit adder called PA Each sum bit depends on all previous carries How do we compute all these carries quickly? A N... N... out out out + in + + in in carries A 4... 4... S 4... S N... Page 9
arry Propagate, Generate, Kill (PGK) For a full adder, define what happens to carries Generate: out = independent of G = A Propagate: out = P = A Å Kill: out = independent of K = ~A ~ (i.e., ~K = A + ) A G P K out S Page
Propagate / Generate (PG) Equations often factored into P and G Propagate and generate for groups spanning i:j G i: j = G i:k + P i:k i G k : j P i: j = P i:k i P k : j ase case G i:i G i = A i i i P i:i P i = A i i ::ing G: º G = in P: º P = Sum: Si = Pi Å Gi - : Page
Ripple arry Revisited in PG Framework G i: = G i + P i i G i : A 4 4 A 3 3 A 2 2 A in G 4 P 4 G 3 P 3 G 2 P 2 G P G P G 3: G 2: G : G : 3 2 4 out S 4 S 3 S 2 S Page 2
PG Diagram Notation lack cell Gray cell uffer i:k k-:j i:k k-:j i:j i:j i:j i:j G i:k P i:k G k-:j G i:j G i:k P i:k G i:j G k-:j G i:j G i:j P k-:j P i:j P i:j P i:j Page 3
Ripple arry PG Diagram t = t + ( N - ) t + t ripple pg AO xor A 4 4 A 3 3 A 2 2 A in G 4 P 4 G 3 P 3 G 2 P 2 G P G P G 3: G 2: G : G : 3 2 4 out S 4 S 3 S 2 S Page 4
arry-skip Adder Ripple carry is slow through all N stages arry-skip allows carry to skip over groups of n bits Decision based on n-bit propagate signal A 6:3 6:3 A 2:9 2:9 A 8:5 8:5 A 4: 4: P 6:3 P 2:9 P 8:5 P 4: 2 8 4 out + + + + in S 6:3 S 2:9 S 8:5 S 4: Page 5
Manchester arry-skip Adder Uses dynamic logic and n-channel pass gates an skip across 4 bits /9/8 EE46 lass Notes Page 6
arry-skip PG Diagram For k n-bit groups (N = nk) t ( ) skip = tpg + éë2 n- + ( k - ) ùûtao + t Page 7 xor
Variable Group Size Delay grows as O(sqrt(N)) Page 8
arry-lookahead Adder arry-lookahead adder computes G i: for many bits in parallel Uses higher-valency cells with more than two inputs Page 9
Higher-Valency ells i:k k-:l l-:m m-:j i:j G i:k P i:k G k-:l P k-:l G l-:m P l-:m G m-:j P m-:j G i:j P i:j Page 2
LA PG diagram using higher valency cells Page 2
arry-select Adder Trick for critical paths dependent on late input X Precompute two possible outputs for X =, Select proper output when X arrives arry-select adder precomputes n-bit sums For both possible carries into n-bit group A 6:3 6:3 A 2:9 2:9 A 8:5 8:5 A 4: 4: + + + out + 2 + 8 + 4 + in S 6:3 S 2:9 S 8:5 S 4: Page 22
arry-increment Adder Factor initial PG and final XOR out of carry-select t ( ) increment = tpg + éë n- + ( k - ) ùûtao + t Page 23 xor
Variable Group Size uffer noncritical signals Page 24
Tree Adder If look-ahead is good, look-ahead across lookahead! Recursive lookahead gives O(log N) delay Many variations on tree adders Three metrics to worry about: Wiring tracks Levels of logic Fanout Page 25
rent-kung 5 4 3 2 9 8 7 6 5 4 3 2 5:4 3:2 : 9:8 7:6 5:4 3:2 : 5:2 :8 7:4 3: 5:8 7: : 3: 9: 5: 5:4:3: 2: : : 9: 8: 7: 6: 5: 4: 3: 2: : : Page 26
Sklansky 5 4 3 2 9 8 7 6 5 4 3 2 5:4 3:2 : 9:8 7:6 5:4 3:2 : 5:2 4:2 :8 :8 7:4 6:4 3: 2: 5:8 4:8 3:8 2:8 5: 4: 3: 2: : : 9: 8: 7: 6: 5: 4: 3: 2: : : Page 27
Kogge-Stone 5 4 3 2 9 8 7 6 5 4 3 2 5:4 4:3 3:2 2: : :9 9:8 8:7 7:6 6:5 5:4 4:3 3:2 2: : 5:2 4: 3: 2:9 :8 :7 9:6 8:5 7:4 6:3 5:2 4: 3: 2: 5:8 4:7 3:6 2:5 :4 :3 9:2 8: 7: 6: 5: 4: 5: 4: 3: 2: : : 9: 8: 7: 6: 5: 4: 3: 2: : : Page 28
Tree Adder Taxonomy Ideal N-bit tree adder would have L = log N logic levels Fanout never exceeds 2 No more than one wiring track between levels We describe adders with 3-D taxonomy (l, f, t) Logic levels: L + l Fanout: 2 f + Wiring tracks: 2 t Known tree adders sit on plane defined by l + f + t = L- Page 29
asic Tree Adder Taxonomy l (Logic Levels) 3 (7) f (Fanout) Sklansky 2 (6) rent-kung 3 (9) 2 (5) (5) (3) (2) (4) () (2) 2 (4) 3 (8) Kogge-Stone t (Wire Tracks) /9/8 EE46 lass Notes Page 3
Han-arlson 5 4 3 2 9 8 7 6 5 4 3 2 5:4 3:2 : 9:8 7:6 5:4 3:2 : 5:2 3: :8 9:6 7:4 5:2 3: 5:8 3:6 :4 9:2 7: 5: 5: 4: 3: 2: : : 9: 8: 7: 6: 5: 4: 3: 2: : : Page 3
Knowles 5 4 3 2 9 8 7 6 5 4 3 2 5:4 4:3 3:2 2: : :9 9:8 8:7 7:6 6:5 5:4 4:3 3:2 2: : 5:2 4: 3: 2:9 :8 :7 9:6 8:5 7:4 6:3 5:2 4: 3: 2: 5:8 4:7 3:6 2:5 :4 :3 9:2 8: 7: 6: 5: 4: 5: 4: 3: 2: : : 9: 8: 7: 6: 5: 4: 3: 2: : : Page 32
Ladner-Fischer 5 4 3 2 9 8 7 6 5 4 3 2 5:4 3:2 : 9:8 7:6 5:4 3:2 : 5:2 :8 7:4 3: 5:8 3:8 7: 5: 5:8 3: : 9: 5: 4: 3:2: : : 9: 8: 7: 6: 5: 4: 3: 2: : : Page 33
Revised Tree Adder Taxonomy /9/8 EE46 lass Notes Page 34
Tree Adder Taxonomy Overview (b) Sklansky (f) Ladner-Fischer 5 4 3 2 9 8 7 6 5 4 3 2 5 4 3 2 9 8 7 6 5 4 3 2 5:4 3:2 : 9:8 7:6 5:4 3:2 : 5:4 3:2 : 9:8 7:6 5:4 3:2 : 5:2 :8 7:4 3: 5:2 4:2 :8 :8 7:4 6:4 3: 2: 5:8 3:8 7: 5: 5:8 4:8 3:8 2:8 5:8 3: : 9: 5:4:3: 2::: 9: 8: 7: 6: 5: 4: 3: 2: : : f (Fanout) Sklansky Ladner- Fischer Ladner- Fischer 2 (6) rent- Kung l (Logic Levels) 3 (7) (a) rent-kung 5 4 5: 4: 3: 2: : : 9: 8: 7: 6: 5: 4: 3: 2: : : 3 2 9 8 7 6 5 4 3 2 (e) Knowles [2,,,] 5 4 3 2 9 8 7 6 5 4 3 2 3 (9) 2 (5) (3) (2) (4) () (5) Han- arlson 5:4 5:2 5:8 3:2 : :8 9:8 7:6 7:4 7: 5:4 3:2 3: : 5:4 4:3 3:2 2: : :9 5:2 4: 3: 2:9 :8 :7 9:8 9:6 8:7 8:5 7:6 7:4 6:5 6:3 5:4 5:2 4:3 4: 3:2 3: 2: 2: : Knowles [4,2,,] New (,,) : 3: 9: 5: 5:8 4:7 3:6 2:5 :4 :3 9:2 8: 7: 6: 5: 4: (2) 5:4:3:2::: 9: 8: 7: 6: 5: 4: 3: 2: : : Knowles [2,,,] 2 (4) Han- arlson (d) Han-arlson 5:4:3:2::: 9: 8: 7: 6: 5: 4: 3: 2: : : (c) Kogge-Stone 5 4 3 2 9 8 7 6 5 4 3 2 5 4 3 2 9 8 7 6 5 4 3 2 Kogge- Stone 3 (8) 5:4 3:2 : 9:8 7:6 5:4 3:2 : 5:4 4:3 3:2 2: : :9 9:8 8:7 7:6 6:5 5:4 4:3 3:2 2: : 5:2 3: :8 9:6 7:4 5:2 3: 5:2 4: 3: 2:9 :8 :7 9:6 8:5 7:4 6:3 5:2 4: 3: 2: t (Wire Tracks) 5:8 3:6 :4 9:2 7: 5: 5:8 4:7 3:6 2:5 :4 :3 9:2 8: 7: 6: 5: 4: 5:4:3:2::: 9: 8: 7: 6: 5: 4: 3: 2: : : 5:4:3:2::: 9: 8: 7: 6: 5: 4: 3: 2: : : Page 35
Area vs. delay of synthesized adders /9/8 EE46 lass Notes Page 36
Summary Adder architectures offer area / power / delay tradeoffs. hoose the best one for your application. /9/8 EE46 lass Notes Page 37