XRM-VIDEO-IO Video Adapter Module User Guide
Copyright 2006-2008 Alpha Data Parallel Systems Ltd. All rights reserved. This publication is protected by Copyright Law, with all rights reserved. No part of this publication may be reproduced, in any shape or form, without prior written consent from Alpha Data Parallel Systems Limited Alpha Data 4 West Silvermills Lane Edinburgh EH3 5BD UK Phone: +44 (0) 131 558 2600 Fax: +44 (0) 131 558 2700 Email: support@alphadata.co.uk Alpha Data 2570 North First Street, Suite 440 San Jose, CA 95131 USA Phone: (408) 467 5076 Fax: (866) 820 9956 Email: support@alpha-data.com EMI This equipment generates, uses and can radiate electromagnetic energy. It may cause or be susceptible to electromagnetic interference if not installed and used with adequate EMI protection for specific applications.
Table of Contents 1. Introduction...1 2. Installation...2 2.1. Handling instructions...2 2.2. Voltage Settings...2 3. Specification...3 3.1. Inputs...3 3.2. Outputs...3 3.3. Clocks...3 4. Related Documents...4 5. Design Examples...5 6. Pinout...6 6.1. XRC2, XRCPro, XPI, XRC4SX and XR4LX...6 6.2. XRC4FX, XRC5LX, XRC5T1, XRC5T2...7 6.3. Signal Description...8 6.3.1. ADC Signals...8 6.3.2. DAC Signals...8 7. Board Layout...9
Photograph 1 - XRM-VIDEO-IO
1. Introduction The XRM-VIDEO-IO is a front panel adapter card primarily designed for use with Alpha Data s ADM-XRC5, ADM-XRC4, ADM-XP, ADM-XRCII and ADP- XPI FPGA based cards. This adapter provides users with an easy method of applying Alpha Data s range of FPGA cards to tasks involving compute-intensive processing of multi-standard composite and component video signals. In addition, analogue video in a variety of formats can be generated to provide monitoring of the processed data or a separate data stream via a suitable display. Connection for both composite and component analogue video input signals is provided via either an S-video connector or via a pair of 75 ohm MCX connectors. The connector(s) used and the signal format can be controlled by the user. Analogue data output is provided via a standard SVGA-style connector.
2. Installation The XRM- XRM-VIDEO-IO is designed to plug in to the front panel connector (SAMTEC QSH series) on the FPGA base card. The retaining screws should be tightened to secure the XRM-CCIR. Note: This operation should not be performed while the FPGA card is powered up. 2.1. Handling instructions Observe precautions for preventing damage to components by electrostatic discharge. Personnel handling the board should take SSD precautions. Avoid flexing the board. 2.2. Voltage Settings This board is a 3V3 only module; users should ensure that the VIO setting on the FPGA card is set to suit this value to ensure no damage can occur.
3. Specification 3.1. Inputs Four separate inputs are provided which can be configured as S-video (Y/C) pairs or as separate composite video (CVBS, PAL or NTSC) inputs which are multiplexed to a pair of ADCs. Resolution: Input Voltage: Impedance : Connector: Coupling: 9 bits (both channels) 1 volt peak-to-peak nominal 75 ohm nominal a)standard S-Video 4 way (main inputs) b)2x 75 ohm MCX (auxiliary inputs) AC coupled. 3.2. Outputs Analogue outputs : 3 (nominal Red,Green,Blue) Resolution : 10 bits Impedance : 75R nominal. Level : 700mV peak to peak, nominal 1 Digital outputs 2 2 Vertical sync : 5V TTL Horizontal sync: 5V TTL Connector: Standard 15-way SVGA D-type. 3.3. Clocks ADC Reference Clock : 24.576 MHz crystal oscillator. DAC Reference Clock: 25.175 MHz crystal oscillator or user generated ( via FPGA) 1 When externally terminated with 75 ohm. 2 Factory-configurable for 3V3 if required.
4. Related Documents ADM-XRC5 User Manual ADM-XRC4 User Manual ADM-XP User Manual ADM-XRC-II User Manual ADP-XPI User Manual SAA7113H Manual (ADC) ADV7123 manual (DAC)
5. Design Examples Example UCF, HDL files and Application software are available from Alpha Data for users of this card.
6. Pinout 6.1. XRC2, XRCPro, XPI, XRC4SX and XR4LX Pin No. UCF Name XRC2 XRC2Pro XPI V4SX V4LX 1 adc_ckenab C2 D10 D10 H28 H28 17 dac_psave_l F8 G9 G9 C33 C33 18 dac_blank_l G11 E13 E13 K28 K28 19 dac_anasync_l F9 H9 H9 C34 C34 20 dac_ckenab G10 F13 F13 K29 K29 21 dac_vsync B6 J12 J12 G33 G33 23 dac_hsync B7 H12 H12 G32 G32 38 adc_llc H16 F21 F21 D34 D34 61 dac_green(0) A11 D20 D20 H34 H34 62 dac_red(0) C11 H20 H20 K33 K33 63 dac_green(1) A12 C20 C20 H33 H33 64 dac_red(1) C12 J20 J20 K32 K32 65 dac_green(2) B11 K17 K17 P27 P27 66 dac_red(2) B13 F15 F15 K34 K34 67 dac_green(3) B12 L17 L17 N27 N27 68 dac_red(3) B14 E15 E15 J34 J34 69 dac_green(4) D12 J17 J17 N30 N30 70 dac_red(4) G12 C15 C15 AF30 V30 71 dac_green(5) D13 H17 H17 N29 N29 72 dac_red(5) G13 C14 C14 AF29 W30 73 dac_green(6) E13 H18 H18 AK32 Y33 74 dac_red(6) J14 L16 L16 AA28 T23 75 dac_green(7) E14 G18 G18 AK31 Y32 76 dac_red(7) J15 M16 M16 AA29 U23 77 dac_green(8) K13 E17 E17 W24 R26 78 dac_red(8) C13 K16 K16 AA30 T25 79 dac_green(9) K14 E18 E18 Y24 T26 80 dac_red(9) C14 J16 J16 AB30 T24 81 dac_blue(4) K16 K19 K19 AE34 R29 82 dac_blue(5) H14 H16 H16 AC28 N32 83 dac_blue(3) K15 J19 J19 AE33 P29 84 dac_blue(6) H15 G16 G16 AB28 P32 85 dac_blue(2) G16 H19 H19 AC30 P31 86 dac_blue(7) F16 M17 M17 AD32 T31 87 dac_blue(1) G17 G19 G19 AC29 P30 88 dac_blue(8) F17 M18 M18 AE32 R31 89 adc_ck E16 K21 K21 AD34 1 P34 2 90 dac_blue(9) C16 C19 C19 AA24 V34 91 dac_ck E17 J21 J21 AC33/AC34 3 R33/R34 4 92 adc_data(0) D17 D19 D19 AA23 V33 93 dac_blue(0) F13 E19 E19 AF34 T34 94 adc_sda D18 E28 E28 AD29 U27 95 adc_data(7) G15 F19 F19 AF33 T33 96 adc_scl C18 F28 F28 AE29 U26 97 adc_data(6) J18 G22 G22 AL24 AF29 99 adc_data(5) K18 F22 F22 AL25 AF30 100 adc_ce G19 C28 C28 AF31 U30 101 adc_data(4) F18 H27 H27 AH34 U33 102 adc_rtc0 E18 J22 J22 AM21 AA25 103 adc_data(3) F19 G27 G27 AJ34 U32 104 adc_rts0 E19 K22 K22 AM22 AA26 105 adc_data(2) G20 J27 J27 AC27 U25 106 adc_rts1 F22 L27 L27 H32 H32 107 adc_data(1) A28 K27 K27 AD27 V25 1 adc_ck uses low capacitance clock input 2 adc_ck uses low capacitance clock input 3 AC34 as clock input, AC33 as clock output 4 R34 as clock input, R33 as clock output
6.2. XRC4FX, XRC5LX, XRC5T1, XRC5T2 Pin No. UCF Name XRC4FX XRC5LX XRC5T1 XRC5T2 1 adc_ckenab C27 AL6 AP14 Y34 17 dac_psave_l G30 AP7 AE8 G38 18 dac_blank_l J26 AN10 AK11 N39 19 dac_anasync_l F30 AP6 AD9 G39 20 dac_ckenab K26 AM11 AJ11 M39 21 dac_vsync C30 AM17 AK9 E40 23 dac_hsync D30 AN17 AK8 E39 38 adc_llc C25 AP9 AD10 H40 61 dac_green(0) E24 AB10 AB5 N41 62 dac_red(0) C32 AB7 AD7 AA37 63 dac_green(1) D24 AB11 AA5 M42 64 dac_red(1) C33 AB8 AC7 Y37 65 dac_green(2) C23 AJ6 AD5 U41 66 dac_red(2) J32 AD7 Y7 M41 67 dac_green(3) C24 AJ7 AD4 T42 68 dac_red(3) K32 AE7 AA6 L42 69 dac_green(4) C34 AH7 AE6 R40 70 dac_red(4) F35 AC9 Y6 J41 71 dac_green(5) D34 AG7 AD6 P41 72 dac_red(5) G35 AD9 W6 H41 73 dac_green(6) D37 AH8 AF6 Y40 74 dac_red(6) F34 AC10 W7 V40 75 dac_green(7) E37 AG8 AE7 W40 76 dac_red(7) E34 AD10 V7 W41 77 dac_green(8) G36 AE9 Y11 U42 78 dac_red(8) D36 AG10 W9 K42 79 dac_green(9) F36 AF9 W11 V41 80 dac_red(9) E36 AF10 W10 J42 81 dac_blue(4) K34 AK8 AJ6 Y42 82 dac_blue(5) J37 AG11 V8 AA40 83 dac_blue(3) L34 AK9 AJ7 W42 84 dac_blue(6) J36 AF11 U8 AA39 85 dac_blue(2) M31 AH10 AK6 AA41 86 dac_blue(7) M32 AE11 V9 P40 87 dac_blue(1) N30 AJ10 AK7 AA42 88 dac_blue(8) N32 AD11 V10 N40 89 adc_ck E32 1 AE8 AG5 Y39 90 dac_blue(9) L26 AH9 AH7 T40 91 dac_ck D32/M27 2 AF8 AF5 Y38 92 adc_data(0) N35 W7 D11 AF40 93 dac_blue(0) D27 AN13 AF9 T39 94 adc_sda N34 AE4 M8 AL42 95 adc_data(7) G25 AC8 Y8 L40 96 adc_scl M36 AC3 L4 AE37 97 adc_data(6) T35/U36 AA4 K8 AE40 99 adc_data(5) T34/T36 AB5 K9 AD40 100 adc_ce H37 W9 F9 AB41 101 adc_data(4) M33 W11 E8 AC39 102 adc_rtc0 V37/V35 AG1 T8 AV40 103 adc_data(3) N33 Y11 E9 AC40 104 adc_rts0 U37/U35 AG2 U7 AU39 105 adc_data(2) J27 AH2 R11 AK38 106 adc_rts1 AC25 AF18 H20 L30 107 adc_data(1) K27 AE18 H19 K30 1 adc_clk uses low capacitance clock input 2 M27 as clock input., D32 as clock output
6.3. Signal Description 6.3.1. ADC Signals adc_data adc_ckenab adc_ck adc_sda adc_scl adc_llc adc_rtc0 adc_rts<1:0> adc_ce -data output, format configured via I2C bus. -active-high enable for adc oscillator ( 24.576 MHz) -copy of 24.576MHz oscillator for FPGA use -serial data for I2C interface -serial clock for I2C interface -line locked system clock (27 MHz) -real-time control output from video processor -real-time signal output,configured via I2C bus. -video processor chip enable ( low activates sleep mode) 6.3.2. DAC Signals dac_red -10-bit pixel data for RED gun dac_green -10-bit pixel data for GREEN gun dac_blue -10-bit pixel data for BLUE gun dac_psave_l -DAC power save control pin dac_blank_l -composite blank control to DAC dac_anasync -composite sync control to DAC dac_ckenab -active high enable to clock oscillator(25.175 MHz); low allows FPGA generated clock to be used for the DAC. dac_vsync -vertical sync signal for SVGA connector dac_hsync -horizontal sync signal for SVGA connector dac_clk -FPGA copy of oscillator clock (25.175 MHz) or clock output to DAC
7. Board Layout ADM-XRCII/XP/XRC4 connector 1 1 1 J3 SVGA Out J4 SVideo/ 2xCVBS in J2 Chroma2/ CVBS in J1 Luma2/ CVBS in
RevisionHistory Date Revision Comment Nov06 - Initialdraft Jan08 Added pinouts for 4FX,5T1,5T2. Added signal descriptions