RX40_V1_0 Measurement Report F.Faccio

RX40_V1_0 Measurement Report F.Faccio This document follows the previous report An 80Mbit/s Optical Receiver for the CMS digital optical link, dating back to January 2000 and concerning the first prototype of the optical receiver (version RX40_v0_0). The test results of the first prototype, including extensive BER and irradiation tests, have been widely reported in published documents. After the test of that prototype, and after a further discussion of the system context where it has to operate, the new version RX40_v1_0 of the circuit has been designed and manufactured in the same quarter micron technology. I. Modified specifications and circuit architecture The new optical receiver chip has been modified in the following points: - The detection of the reset requires now 20 consecutive 0 to be transmitted (500ns) in the data line. - The output of the receiver is disabled during reset, which happens also in the absence of signal at the receiver input. - The DC baseline current the circuit is capable of dealing with has been increased to 500µΑ. - The number of channels has been decreased to 2 per chip, each having a separate reset signal output. - A couple of pads have been added to test the functionality of the chip without bonding the channels to the photodiodes. The purpose is to enable bad-die detection at the wafer test level. The chip has a size of 2x2 mm 2. A list of the main specifications is reported in the following table: Min Typ Max Unit Note DC input current 500 µa Baseline DC current AC input current 10 (after rad) 500 µa Bandwidth 80 MHz Low cut-off frequency 1-2 MHz Jitter 0.5 ns Output voltage level LVDS Supply voltage 2.5 V Sensitivity -20 dbm Bit error rate 10-12 Reset output Coupling with p-i-n DC diode Diode bias voltage 1.8 V Low for >5µs for a transmission of 20 consecutive 0 To match these specifications, the following architecture has been chosen (the PIN diode is DC coupled to the input of the amplifier and is not integrated in the chip): PIN diode No_signal_out B.F. Reset block Switch box reset in preamplifier L.A. L.A. L.A. L.A. sf LVDS Tx out RX40_v1_0 measurement report, November 2000 1

. Compared to the previous version, and to cope with the modified specifications, a few characteristics have been changed in the architecture: - The current in the input branch of the preamplifier has been increased to enable the circuit to cope with higher DC baseline currents. - Correspondingly, the size of sink transistor in the preamplifier (to sink the DC baseline current to ground), has been increased. Also the transresistance transistor has been resized to cope with the new specifications. - In the preamplifier, a comparator with hysteresis has been added to monitor the value of the transresistance. In this way, above a given value of the transresistance the circuit considers that no signal is present at the input of the preamplifier. This cut has been chosen to correspond a modulation (AC) an optical power of about 7-8 µw. Whenever the signal amplitude is below this level, the flag No_signal_out is enabled (low). - The block detecting the transmission of a reset signal has been completely changed, and moved to sense the output of the third Limiting Amplifier. The new block enables the reset signal (low) when the input signal is low (no light) for more than about 250 ns (which corresponds to about 10 clock cycles). The duration of the reset is determined by an rc circuit, and it is designed to be about 8 µs. - The No_signal_out output from the preamplifier and the reset output from the reset block are fed to a logic AND. When either signal is enabled (low), the reset output from the circuit is also enabled (low), and controls the switch block at the input of the fourth Limiting Amplifier, forcing the circuit output to a constant level. The receiver circuit is directly bonded to the Fermionics photodiode, as shown in Figure 1. Figure 1: Image of the receiver ASIC alone, and bonded in the test board to the Fermionics diode. II. Measurements The measurements have been performed using the setup shown in Figure 2. Either the BER tester or the HP8110A generate the pseudo-random pattern that is fed to the receiver. The output of the receiver is converted from LVDS to ECL in the test board, then the signal is fed to the BER tester, where appropriate ECL termination is provided. All the following results, unless otherwise specified, refer to measurements performed on chip n.1, channel 1 (mounted on board n.1). RX40_v1_0 measurement report, November 2000 2

Optical attenuator Single-mode optical fiber PIN diode Optical receiver circuit 1310nm laser transmitter Optical power-meter Output signal Bit Error Rate tester Input signal HP 8110A Pulse generator Lecroy 9310 300MHz digital oscilloscope Figure 2: Setup used for the characterisation of the optical receiver. II.1 General characteristics The main measured characteristics of the optical receiver, for a power supply voltage of 2.5 V, are summarised in Table 1. Some of these characteristics will be detailed in the following paragraphs. Characteristic Input AC modulation range capability Input DC baseline power capability Power consumption LVDS output @ 2.5 V Bandwidth Jitter (peak-peak) for 0 DC baseline current and minimum signal Jitter (peak-peak) for 500 µw DC baseline and minimum signal Reset detection Table 1: Main characteristics measured on the optical receiver at V dd = 2.5 V. Measured performance -20.1 dbm (9.7 µw) < P opt < 3 dbm (2 mw) > 500 µw 28.6 ma (72 mw, or 36 mw per channel) Min 1.25 V; Max 1.51 V ( 260 mv) Higher than 80 MHz (reception OK @ 175 Mbit/s) 0.7 ns 1.5 ns Transmission of 10 consecutive 0 @ 40 Mbit/s (250 ns) Reset duration 9.7 µs Power supply range 1.85 V < V dd < 3 V RX40_v1_0 measurement report, November 2000 3

An example eye diagram measured at the LVDS output of the circuit, at a bit rate of 80 Mbit/s and for two different optical powers, is shown in Figure 3. Figure 3: Example eye diagram taken at a bit rate of 80 Mbit/s, with no DC baseline current, for two different AC optical powers (left: -19.6 db or 11 µw; right: -10.6 dbm or 88 µw). X-axis: 2 ns/div. Y-axis: 50 mv/div. II.2 DC baseline The circuit shows the capability to function correctly up to the required level of 500 µa of DC baseline current. In these conditions, however, the noise is increased due to the contribution of the sink transistor noise directly at the preamplifier input. The noise increase is observable in the eye diagram in Figure 4. Figure 4: Eye diagram at the LVDS output of the circuit. The signal modulation amplitude is about 18 µw, with a DC baseline of about 500 µw. X-axis: 2 ns/div. Y-axis: 50 mv/div. II.3 Bandwidth To measure whether the bandwidth is higher than 80 MHz, we used the BER tester up to its maximum bit rate capability of 175 Mbit/s. The receiver worked correctly in that conditions, with a BER of the order of 5.7 10-12 for an AC optical power of -18.6 dbm (13.8 µw). An eye diagram taken at the LVDS output of the circuit at that bit rate is shown in Figure 5. Figure 5: Eye diagram measured at a bit rate of 175 Mbit/s, with an AC optical power of 18.6 dbm. II.4 Reset output (no signal and reset detection) The reset signal output (CMOS logic) has been monitored in the presence and absence of input signal to the receiver. As wished, the reset is low (active) in the absence of signal, and correspondingly the receiver channel output is not valid (stable with one LVDS out high and the other low). In the presence of valid signal, instead, the reset signal output is high. The optical power necessary to activate the receiver is about -20.1 dbm (or 9.7 µw). RX40_v1_0 measurement report, November 2000 4

When a sequence of at least 10 consecutive 0 is transmitted along the data line (at 40 Mbit/s, corresponding to 250 ns with no AC input signal), the reset output is enabled for a time duration of about 9.7 µs. A sequence of pictures of the reset output taken with the digital scope is shown in Figure 6. In A, the transmission of 9 consecutive 0 at the right half oscilloscope screen is not detected as a reset: the reset output at the bottom remains high. In B, the transmission of 10 consecutive 0 is instead detected as reset, and correspondingly the reset output is enabled (low). This signal stays enabled for about 9.7 µs, as seen in C. Simultaneously, the circuit output is disabled and forced to a stable level. When the reset is finally released, data transmission along the channel is re-established, as shown in D. The reset release is not synchronised to the data transmission, therefore the first bit transmission might be shorter than 25 ns. It is therefore important, after a reset, to transmit an idle to re-synchronise transmitter and receiver. A) C) B) D) Figure 6: Sequences of the reset output signal. In each figure, the top signal is the receiver channel output (converted into ECL logic on the test board), and the bottom signal is the reset output. The time scale in A, B and D is 100 ns/div, whilst in C it is 2 µs/div. II.5 Power supply voltage range Measurement have confirmed that the receiver works correctly down to a power supply voltage of 1.85 V and up to 3 V, without any appreciable change in its current consumption. The performance changes with respect to the measurements at 2.5 V are summarised in Table 2. Table 2: Main characteristics measured at different power supply voltages (nominal ± 20%) Characteristic V dd = 2 V V dd = 3 V Min detectable AC signal -19.9 dbm (10.2 µw) -19.9 dbm (10.2 µw) Current consumption 28.1 ma (56.2 mw) 28.4 ma (85.2 mw) LVDS output Min 790 mv, Max 1.06 V Min 1.77 V, Max 2.07 V Reset detection 9 consecutive 0 @ 40 Mbit/s 13 consecutive 0 @ 40 Mbit/s Reset duration 7.5 µs 11.5 µs RX40_v1_0 measurement report, November 2000 5

II.6 Bit Error Rate measurement Contrary to the previous version of the receiver ASIC, the present version does not allow for measuring the full BER curve starting from very low optical power (-30 dbm or less). The present version senses the input optical power and enables the output only for powers above about 20.5 dbm. Therefore, BER measurements are possible only for optical powers higher than this level, for which the BER is already extremely low (as measured for the previous ASIC version, and published in several papers). Some of the BER measurements performed on the ASIC are summarised in Table 3. Channel 1 in chip n.3 is bonded to an irradiated photodiode. It should be noted that the conversion from LVDS to ECL levels is performed on the test board, and that the BER tester outputs and inputs ECL levels. Therefore, it is never possible to distinguish whether the measured errors occur in the receiver chip or in the LVDS-ECL converter block on the test board. In addition, it should be added that the measurements have been performed in a noisy environment (in particular, the mains are far from being clean in this laboratory). It was in fact possible to observe clear bursts of consecutive errors after hours of error-free data transmission. AC optical power (modulation) Chip n.1, channel 1 DC baseline optical power Table 3: Summary of the BER measurements. V dd Bit rate N. of errors Measure time -19.6 dbm (10.9 µw) 0 2.5 V 80 Mbit/s 5 2 d 15 h 2.7 10-13 -18.2 dbm (15 µw) 500 µw 2.5 V 80 Mbit/s 17 1 d 20 h 1.3 10-12 -18.9 dbm (12.9 µw) 0 2 V 80 Mbit/s 0 5 < 4 10-11 -19.6 dbm (11 µw) 0 3 V 80 Mbit/s 0 25 < 8 10-12 Chip n.2, channel 1-18.7 dbm (13.5 µw) 0 2.5 V 80 Mbit/s 0 14 h 12 < 2 10-13 Chip n.3, channel 1-10.6 dbm (87 µw) 467 µw 2.5 V 80 Mbit/s 2 10d 21h 2.7 10-14 Chip n.3, channel 1 with ch.2 working ($) -10.6 dbm (87 µw) 467 µw 2.5 V 80 Mbit/s 17 14 d 3 h 1.7 10-13 Chip n.3, channel 2 with ch.1 working ($) -19.7 dbm (10.7 µw) 42 µw 2.5 V 80 Mbit/s 4 19 h 5 7.3 10-13 Chip n.3, channel 1 with clock on ch. 2 (*) -14 dbm (39.8 µw) 470 µw 2.5 V 80 Mbit/s 0 2 d 15 h < 5 10-14 -14 dbm (39.8 µw) 470 µw 2.5 V 175 Mbit/s 0 37 < 3 10-12 ($) Data transmitted on one channel, with an uncorrelated signal on the other channel (39 MHz, -14 dbm modulation, 470 µw DC baseline in the first measurement, and 12.2 dbm modulation, 240 µw DC baseline in the second and longest measurement). (*) Data was transmitted on channel 1, and clock on channel 2. The clock signal characteristics were: AC optical power 10 dbm (100 µw); DC baseline 370 µw. BER RX40_v1_0 measurement report, November 2000 6

II.7 Measurements on other chips All of the above results, except for BER tests, refer to one only IC (chip n.1). Two other chips were measured, and very similar performance was observed. For the sake of completeness, the results of these measurements are summarised in Table 1. In chip n.3, both channels were bonded to a photodiode (channel 1 to a photodiode irradiated with neutrons). Measurements were taken at V dd =2.5 V unless otherwise specified. Table 4: Summary of the measurements on chip n.2 and n.3. The power consumption always refers to the full chip (2 channels). Characteristic Chip n.2, channel 1 Chip n.3, channel 1 Chip n.3, channel 2 Input AC modulation range capability Input DC baseline power capability -20.2 dbm < P opt -19.2 dbm < P opt < 2.35 dbm or higher -19.9 dbm < P opt < 2.35 dbm or higher > 500 µw > 500 µw Power consumption 70.5 mw (28.2 ma) 75.2 mw (30.1 ma) Å LVDS output @ 2.5 V 1.33 V -> 1.62 V 1.28 V -> 1.56 V 1.31 V -> 1.59 V Bandwidth Reset detection 10 consecutive 0 10 consecutive 0 10 consecutive 0 Reset duration 9.8 µs 9.3 µs 9 µs Min. supply voltage 1.8 V 1.9 V 1.9 V LVDS output @ 2V 0.75 V -> 1.07 V 0.8 V -> 1.08 V 0.81 V -> 1.09 V Power cons. @ 2 V 56 mw (28 ma) 58.4 mw (29.2 ma) Å LVDS output @ 3V 1.8 V -> 2.09 V 1.78 V -> 2.08 V 1.81 V -> 2.1 V Power cons. @ 3 V 85.2 mw (28.4 ma) 92.4 mw (30.8 ma) Å II.8 Injection of test signals A new feature of the present version of the receiver chip is the possibility to exercise the two channels without having to bond them to a photodiode. This allows to verifying the functionality of the two channels of each receiver chip at the wafer level, hence to detect bad-dies before having them mounted on the hybrids. Two pads have been added to the chip layout, one for the injection of an AC signal and the other for a DC baseline. The amplitude of these signals is about 320 µa for both, the current being generated internally. To exercise the channel inputs in that way, it is sufficient to apply a voltage signal to the two test pads. The effectiveness of this test feature has been verified by bonding two chips to a DIL package that was placed in a small board mounted on purpose. In that way, it was easily and quickly possible to check the correct functionality of the two chips (LVDS output, DC baseline capability up to 320 µa, reset output, power consumption, sufficient bandwidth). The same test can be easily run systematically on chips on wafers with the help of a dedicated probe card. RX40_v1_0 measurement report, November 2000 7