Dynamic Power Reduction in Sequential Circuit Using Clock Gating

Dynamic Power Reduction in Sequential Circuit Using Clock Gating S. Stella Sangeetha 1, G. Ewance Lidiya 2 PG Scholar, VLSI Design, Dr.Sivanthi Aditanar College of Engineering 1 Assistant Professor/ECE, Dr.Sivanthi Aditanar college of Engineering 2 ABSTACT--The popularity of portable electronic products in low power system has attracted more attention in recent years. Dynamic power consumption remains to be the biggest contributor to the total power consumption of a hardware design. One of the major sources for dynamic power consumption is the system s clock signal, which is responsible for thirty to seventy percentage of the total dynamic power consumption. Clock gating is a predominant technique used to reduce the dynamic power. Clock gating technique is used to reduce unwanted switching of clock signals. In the proposed system clock gating technique is applied to one bit counter, two bit counter, three bit counter and it is compared to counter without clock gating. The power consumption of counter with clock gating is low compared to counter without clock gating. The advanced clock gating techniques are used for further power reduction, among which Look-Ahead Clock Gating (LACG) is efficient to reduce power consumption. LACG computes the clock enabling signals of each flip-flop one cycle ahead of time based on the present cycle data of those flip-flops on which it depends. The proposed design aims at designing a counter with LACG technique for power reduction in sequential circuits. Keywords_ LACG (Look Ahead Clock Gating), Dynamic power Consumption, Clock Gating. I. INTRODUCTION One of the major aspects of digital system is analysis and design of sequential circuits. Sequential circuits require outputs to be generated that are not only dependent on the present input conditions but also depend upon the past history of these inputs. These past history are provided by feedback from the output back to the input. Sequential circuit contains memory elements that are connected to the combinational circuit as the feedback path. The information stored in the memory elements at any given time defines the present state of the sequential circuit. The present state and the external inputs determine the outputs and the next state of the sequential circuit. Flip flop is the basic building block of a shift register. Flip flops are of different types. In electronic application, D Flip flop is the simplest type of flip flop widely used. A register has group of flip flops and helps to store one bit information. Binary information in a register gets shifted upon the activation of the clock signal in the shift register. In Parallel Out shift register, the data bits are given simultaneously and the outputs are taken in parallel. In this shift register no delay exists between the data bits to be entered and the output to be taken [17]. The major dynamic power consumption in consumer electronic products is due to the system s clock signal, in which there will be 30%-70% of the total dynamic power consumption. Clock gating technique with activity driven clock tree to reduce the dynamic power consumption. Further modification has been made with linear feedback shift register to obtain the power savings of about 10% [10]. Here dynamic power management strategy is implemented in order to reduce the power dissipation. The maximum power savings of 28% has been achieved with counter and implied overhead gets reduced [4]. Several techniques to reduce the dynamic power are developed, of which clock gating is predominant. Ordinarily, when a logic unit is clocked, its underlying sequential elements receive the clock signal, regardless of whether or not they will toggle in the next cycle. With clock gating, the clock signals ANDed with explicitly predefined enable signals. Clock gating is employed at all levels like system architecture, block design, logic design, and gate. This technique is often used to save power by effectively shutting down portions of a digital circuit when they are not in use, but comes at a cost of increased complexity in timing analysis. 78 S. Stella Sangeetha, G. Ewance Lidiya

Fig.1.Enabling of the clock signal transition look ahead D flip flop. Counters have modes. The mod of the counter represents the number of states of the cycles through it, before setting the counter to its initial state. For example, a binary mod 8 counter has 8 countable states. They are from 000 to 111. So the mod 8 counter counts from 0 to 7. The clock signal driving a flip flop is disabled when the flip flops state is not subject to change in the next clock cycle. In order to reduce the hardware overheads, several flip flops to be driven by the same clock signal. A XOR gate compares its output Q at the present cycle with the present data input D that is supposed to appear at the output in the next cycle. The clk_en output of the XOR indicates whether or not a clock signal will be required in next cycle. The clock driver used in figure 1(a) is then replaced by a 2-way AND gate where the clock signal is enabled. The symbol used in figure 1(b) to represents the sequential elements that incorporate generation of clk_en. The clock can be controlled in each flip-flop by a dedicated gater using the flip-flop's clk_enable signal. Deactivating the clock signal leads to reduced power consumptions of both its internal nodes and clock lines, but the overhead involved limits its use in low data switching situations. The main purpose of the project is to reduce the dynamic power in counter using clock gating and it is compared to counter without clock gating. II. 3 BIT SYNCHRONUS COUNTER Generally counter bits are evaluated at every clock cycle and captured by associated flip flops at every triggering edge of the clock. Because the switching activity of counter bits in a binary counter is decreased by half as the significance of each bit increase, this type of operation apparently causes a lot of redundant transition, particularly for counter bits having higher significance. Figure (2) denote the three bit synchronous counter here D flip flop were used to generate the binary sequence from 000 to 111 because it will count up to seven bit for every clock signal. But the clock signal flows continuously in the D flip flop independent of the data transition, the increase in the load capacitance results in increase in the power consumption relatively more in D flip flop compare to the data Fig.2.Three bit Synchronous counter A binary mod 4 counter has 4 count states, from 000 to 011. So the mod 4 counter counts from 0 to 4. This means, in general a mod N counter can contain n number of flip flops, where 2n = N. The design procedure for synchronous counters is same as those Sequential circuits. Synchronous counter have a regular pattern and can be constructed with complementing flip flops and gates. Like shift registers and other combinational circuits, there is another important element in digital electronics which we use most. They are counters. Counters are used not only for counting but also for measuring frequency and time; increment memory addresses. Counters are specially designed synchronous sequential circuits, in which, the state of the counter is equal to the count held in the circuit by the flip flops. Counters calculate or note down the number that how many times an event occurred. Counters are the crucial hard ware components, and are defined as the digital circuit which is used to count the number of pulses. Counters are well known to us as Timers. Counter circuits are the best example for the flip flop applications. Counters are designed by grouping of flip flops and applying a single clock signal to them. In simple words, the counters are those, which have the group of storage elements like flip flops to hold the count. III. CLOCK GATING TECHNIQUE A promising technique to reduce the power consumption of the clock signal is called clock gating, it depends on deactivating the clock signal on portions of the circuit that are inactive for certain 79 S. Stella Sangeetha, G. Ewance Lidiya

periods of time. Ordinarily, when a logic unit is clocked, its underlying sequential elements receive the clock signal, regardless of whether or not they will toggle in the next cycle. With clock gating, the clock signals ANDed with explicitly predefined enable signals. The comparison between input D and output Q is done by an XOR gate which feeds the AND gate to produce the required gated clock (GC) signal for the latch. When both D and Q are the same, the gated clock signal will remain low and will not consume power for switching. In the D FF the output reflects the input. If the D FFs input does not change, then the clock should be gated for that instant of time. If the input of D FF change from 0 to 1(state transition), then the clock should be allowed for that instant of time. thus can effectively be defined and capture the periods where functional blocks and modules do not need to be clocked. Those are later being automatically synthesized into clock enabling signals at the gate level. In many cases, clock enabling signals are manually added for every FF as a part of a design methodology. Still, when modules at a high and gate level are clocked, the state transitions of their underlying FFs depend on the data being processed. It is important to note that the entire dynamic power consumed by a system stems from the periods where modules clock signals are enabled Gated positive latch is shown in the Figure 4.The comparison between input D and output Q is done by an XOR gate which feeds the AND gate to produce the required gated clock signal (Clkg) for the latch. When both D and Q are the same, the gated clock signal will remain low and will not consume power for switching. When they differ, the gated clock signal will copy the original clock and may make a necessary transition to change the state of the latch. The same technique can be used for gated negative latch by using XNOR gate and OR gate [10]. Fig.3. Clock gating technique If the state transition exists then the output of Y will be 1 otherwise the output will be 0, then the value of clock signal will be 1. If the output of Y is 1 and the clock signal is allowed, the output of AND gate is 1 i.e. the clock is allowed. If the output of Y is 0 and the clock is allowed, then the output of AND gate is 0. Then the power consumption is low because the unnecessary clocks get reduced. For stable inputs, the clocks are not allowed. For state transitions of input, the clocks get allowed. The clock signals driving a given FF is disabled (gated) once the FFs state is not subject to a change in the next clock cycle. There are four clock gating methods are available. A) Synthesis Based Clock Gating Synthesis based clock gating is the most widely used method by EDA tools. The utilization of the clock pulses, measured by data to clock toggling ratio, left after the employment of synthesis based gating may still be very low. Clock enabling signals are very well understood at the system level and 80 S. Stella Sangeetha, G. Ewance Lidiya Fig.4. Synthesis based clock gating The main advantage of this method is the gated flip-flop is implemented by cascading two clockgated latches in a master-slave configuration and this design overcomes the timing constraints. The disadvantage of this method is the design needs two gating overhead circuits for each flip-flop. This double overhead limits the use of flip-flop on data signals with low switching activity. B) Auto Gated Flip Flop The FF s master latch becomes transparent on the falling edge of the clock, where its output must stabilize no later than a setup time prior to the arrival of the clock s rising edge, when the master latch becomes opaque and the XOR gate indicates whether or not the slave latch should change its

state. If it does not, its clock pulse is stopped and otherwise it is passed. A significant power reduction was reported for register based small circuits, such as counters, where the input of each FF depends on the output of its predecessor in the register. AGFF can also be used for general logic; the diagram is given in figure [5]. Clk signal is given as the input to the master D latch and one input of the AND gate. The gated clock signal clk_g is given to the slave latch. A significant power reduction was reported for register based small circuits, such as counters, where the input of each FF depends on the output of its predecessor in the register. AGFF has two major drawbacks. Firstly, only the slave latches are gated, leaving half of the clock load not gated. Secondly, serious timing constraints are imposed on those FFs residing on critical paths, which avoid their gating. AGFF can also be used for general logic. Auto-Gated Flip-Flip (AGFF) method is very simple to implement and can be used for general logic by allotting a full clock cycle for the computation of the enabling signals and their propagation [1]. Fig.5. Auto gated flip flop C) Data Driven Clock Gating A Flip-Flop finds out that its clock can be disabled in the next cycle by XORing its output with the present data input that will appear at its output in the next cycle. The outputs of k XOR gates are ORed to generate a joint gating signal for k FFs, which is then latched to avoid glitches. The diagram of data driven clock gating is shown in figure [6]. The combination of a latch with AND gate is commonly used by commercial tools and is called integrated clock gate (ICG). Such data-driven gating is used for a digital filter in an ultralowpower design. A single ICG is amortized over k FFs. There is a clear tradeoff between the number of saved (disabled) clock pulses and the hardware overhead. With an increase ink, the hardware overhead decreases but so does the probability of disabling, obtained by ORing the k enable signals [12]. Fig.6. Data driven clock gating Data-driven gating aims to disable large amount of redundant clock pulses. To reduce the hardware overhead, flip-flops are grouped so that they share a common clock enabling signal. Data-driven gating suffers from a very short time-window where the gating circuitry can properly work. The cumulative delay of the XOR, OR, latch and the AND gate must not exceed the setup time of the FF. Such constraints may exclude 5%-10% of the FFs from being gated due to their presence on timing critical paths. Another difficulty of data-driven gating is its design methodology. To maximize the power savings, the FFs should be grouped such that their toggling is highly correlated. This requires running extensive simulations characterizing the typical applications expected by the end-user. D) Look Ahead Clock Gating Look Ahead Clock Gating computes the clock enabling signals of each FF one cycle ahead of time, based on the present cycle data of those FFs on which it depends. Similarly to data-driven gating, it is capable of stop-ping the majority of redundant clock pulses. It has however a big advantage of avoiding the tight timing constraints of AGFF and data driven, by allotting a full clock cycle for the enabling signals to be computed and propagate to their gates [1]. LACG takes AGFF a leap forward, addressing three goals; stopping the clock pulse also in the master latch, making it applicable for large and general designs and avoiding the tight timing constraints. LACG is based on using the XOR 81 S. Stella Sangeetha, G. Ewance Lidiya

output in to generate clock enabling signals of other FFs in the system, whose data depend on that FF. Furthermore, unlike data driven gating whose optimization requires the knowledge of FF s data toggling vectors, LACG is independent of those [16]. The embedding of LACG logic in the RTL functional code is uniquely defined and easily derived from the underlying logic, independently of the target application. This simplification is advantageous as it significantly simplifies the gating implementation. The diagram of look ahead clock gating shown in figure [7]. Look ahead clock gating has been shown to be very useful in reducing the clock switching power. Similar to data driven gating, it is capable of stopping the majority of redundant clock pulses. design. The software used for this work is Xilinx 14.5. Verilog language is preferred than VHDL because this technique can reduce cost and time easy to troubleshoot, and high references availability. Single bit is given as the input in the D Flip flop i.e. D is assigned as the input and the input sample is given as 0. Because D Flip flop output reflects the input. Single D flip flop with clock gating is shown in figure (8). If the D Flip flop inputs 0 do not change, then the clock should be gated for that instant of time. If the D Flip flop input change from 0 to 1(state transition), then the clock should be allowed for that instant of time. If the state transitions exits then the output of a will be 1 otherwise the output will be 0. The clk will be 1. If the output of a is 1 and when the clk is allowed, the output of AND gate is 1 i.e. the clock is allowed. If the output a is 0 and then clock is allowed, the output of AND gate is 0. Then the power dissipation is low because the unnecessary clocks get reduced. Synthesis and simulation waveform of counter is obtained by using modelsim software. Fig.7. Look ahead clock gating It has however a big advantage of avoiding the tight timing constraints of AGFF and data driven, by allotting a full clock cycle for the enabling signals to be computed and propagate to their gates. IV. RESULT AND DISCUSSION In this proposed system clock gating method is applied for 3 bit counter and its compared to counter without clock gating is analyzed by using Xilinx and modelsim. Verilog is used as the hardware description language because of the flexibility to exchange among environments. The code is pure verilog that could easily be implemented on other devices, without changing the 82 S. Stella Sangeetha, G. Ewance Lidiya.. Fig.8. Single D flip flop with clock gating Three bit counter having clk and reset as input and counter is a output of counter. Here clk is positive edge clock and give reset input then counter output is produced. Three bit counter without clock gating output is given in figure [9]. In order to reduce the hardware overheads, several flip flops to be driven by the same clock signal. Three bit counter with clock gating have four input namely d1, d2, d3, clk and reset. First time run by reset is 0 and next time assign reset is 1. Then counter will be start to count.

Fig.11. Output of counter without clock gating Fig.9. Output of three bit counter without clock gating Fig.12. Output of counter with clock gating Fig.10. Output of three bit counter with clock gating Three bit counter with clock gating output shown in figure (10), the clock signals ANDed with explicitly predefined enable signals. Clock gating is employed at all levels like system architecture, block design, logic design, and gates. This technique is often used to save power by effectively shutting down portions of a digital circuit when they are not in use, but comes at a cost of increased complexity in timing analysis. The clock signal driving a flip flop is disabled when the flip flops state is not subject to change in the next clock cycle. The dynamic power is calculated by using Xilinx 14.5. The proposed system produces the less amount of dynamic power in counter circuit. Here Table1denote the comparison of counter with clock gating and counter without clock gating. Counter with clock gating technique will produce less power consumption. Table.1. Comparison of counter with and without clock gating Counter Dynamic power without clock gating (w) Dynamic power with clock gating (w) One bit 0.127 0.28 Two bit 0.122 0.30 Three bit 0.142 0.96 Here the table shown the maximum amount of power would be reduced by using clock gating 83 S. Stella Sangeetha, G. Ewance Lidiya

technique. In this project totally 70% of power would be reduced. V. CONCLUSION Achieves power savings on an average of 70.44% compared to the ordinary counter and counter with clock gating. The future work aims at to apply various clock gating techniques are applied for further power reduction in counter. Then noise will be reduced by using variable frequency clock generator. VI. REFERENCE [1] Arye Albahari and Shmuel Wimer, Look-Ahead Clock Gating Based on Auto Gated Flip-Flops, IEEE Transactions on Circuits and Systems-I: Regular Papers, Vol. 61, pp.1465-1472 No. 5, May 2014. [2] Benini.L, Bogliolo.A, and De Micheli.G, A survey on design techniques for system-level dynamic power management, IEEE Trans.Very Large Scale Integr. (VLSI) Syst., vol. 8, no. 3, pp. 299 316, Jun 2000. [3] Changjun.K, Chunhong.C, and Majid.S, Activitysensitive clock tree construction for low power, in Proc. Int. Symp. Low Power Electron. Design, 2002. [4] Chen.C, Farrahi.A, Srivastava.A, Tellez s, and Sarrafzadeh.M, Activity-driven clock design, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.20, no. 6, pp.705-714, Jun. 2001. [5] Cai.Y, Hong. X, Hu. J, Shen. W, and, Activity and register placement aware gated clock network design, in Proc. Int. Symp. Phys. Design, pp.182-189, 2008. [6] Chang.Y.-T, Chen.S.F, Hsu.C.-C, Lin.M.P.-H, and Tsai.Y.-W, Post-placement power optimization with multi-bit flip-flops, in Proc. IEEE/ACM Int. Conf. Computer Aided Design, pp.218-223, Nov. 2010. [7] Spy Glass Power [Online]. Available: http://www.atrenta.com/solutions/spyglassfamily/sp yglass-power.htm [8] Chang.C.-L, Cheng.L.S.-F,Jiang.I.H.-R,Tsai.E.Y.-W, and, Yang.Y.-M, INTEGRA: Fast multi-bit flipflop clustering for clock power saving based on interval graphs, in Proc. Int. Symp. Phys. Design, pp. 115-121, 2011. [9] Donno.M, Macii.E, and Mazzoni.L, Power-aware clock tree planning, in Proc. Int. Symp. Phys. Design, pp 138-147, 2004. [10] Hosny.M.S and Yuejian.W, Low power clocking strategies in deep submicron technologies, in Proc. IEEE Intll. Conf. Integr. Circuit Design Technology, pp.143-146, Jun, 2008. [11] Harry Veendrick, Deep Submicron CMOS ICs, From Basics to ASICs, kluwer academic publishers, 2000. [12] Israel Koren, and Shmuel Wimer Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, No. 4, pp.771-778, April 2014. [13] Jiang Hu, Weixiang Shen, Xianlong Hong and YiciCai, An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.18, No.12, pp.1639-1648,december 2010. [14] Koren.I, and Wimer.S, The Optimal fan-out of clock network for power minimization by adaptive gating, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 10, pp. 1772-1780, Oct. 2012. [15] Massoud Pedram, Qing Wu, and Xunwei Wu. Clock-Gating and its Application to Low Power Design of Sequential Circuits, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 47, No. 103, March 2000. [16] Nogawa.M and Ohtomo.Y, A Data-.Transition Look-Ahead Circuit for Statistical Reduction in Power Consumption, IEEE Journal of Solid-State Circuits, Vol.33, Issue 5, May 2000. [17] Oklobdzija.V.G, Digital System Clocking, High- Performance and Low-Power Aspects, New York, NY, USA: Wiley, 2003. [18] Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, second edition, IEEE 1364-2001, 2003. [19] Tierno.J et al., A DPLL-based per core variable frequency clock generator for an eight-core POWER7 microprocessor, in Proc. Symp. VLSI Circuits, Jun. 2010. 84 S. Stella Sangeetha, G. Ewance Lidiya