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October 010 74UP1G7 TinyLogic Low Power Universal onfigurable Two- Input Logic Gate Features 0.8 to 3.6 Supply Operation 3.6 Over-oltage Tolerant I/Os at from 0.8 to 3.6 High Speed tpd -.9ns: Typical at 3.3 Power-Off High-Impedance Inputs and Outputs Low Static Power onsumption - I =0.9µ Maximum Low Dynamic Power onsumption - PD=.9pF Typical at 3.3 Ultra-Small MicroPak Packages Ordering Information Description The 74UP1G7 is a universal configurable -input logic gate that provides a high performance and low power solution ideal for battery-powered portable applications. This product is designed for a wide low voltage operating range (0.8 to 3.6) and guarantees very low static and dynamic power consumption across the entire voltage range. ll inputs are implemented with hysteresis to allow for slower transition input signals and better switching noise immunity. The 74UP1G7 provides for multiple functions as determined by various configurations of the three inputs. The potential logic functions provided are ND, NND, OR, NOR, and XNOR, inverter and buffer. Refer to Figures to 8. Part Number Top Mark Package Packing Method 74UP1G7L6X 6-Lead Micropak, 1.0mm Wide 74UP1G7FHX 6-Lead, MicroPak, 1x1mm ody,.3mm Pitch 000 Units on Tape & Reel 000 Units on Tape & Reel 74UP1G7 TinyLogic Low Power Universal onfigurable Two-Input Logic Gate 008 Fairchild Semiconductor orporation www.fairchildsemi.com 74UP1G7 Rev. 1.0.4
Pin onfigurations Pin Definitions GND 1 3 6 4 Figure 1. MicroPak (Top Through iew) Pin # Name Description 1 Data Input GND Ground 3 Data Input 4 Output Supply oltage 6 Data Input 74UP1G7 TinyLogic Low Power Universal onfigurable Two-Input Logic Gate 008 Fairchild Semiconductor orporation www.fairchildsemi.com 74UP1G7 Rev. 1.0.4
Function Table Inputs 74UP1G7 =Output L L L H L L H L L H L H L H H L H L L L H L H L H H L H H H H H H = HIGH Logic Level L = LOW Logic Level Function Selection Table -Input Logic Function onnection onfiguration -Input ND Figure -Input ND with oth Inputs Inverted Figure -Input NND with Inverted Input Figure 3, Figure 4 -Input OR with Inverted Input Figure 3, Figure 4 -Input NOR Figure -Input NOR with oth Inputs Inverted Figure -Input XNOR Figure 6 Inverter Figure 7 uffer Figure 8 74UP1G7 TinyLogic Low Power Universal onfigurable Two-Input Logic Gate 008 Fairchild Semiconductor orporation www.fairchildsemi.com 74UP1G7 Rev. 1.0.4 3
74UP1G7 Logic onfigurations Figure through Figure 8 show the logical functions that can be implemented using the 74UP1G7. The diagrams show the DeMorgan s equivalent logic duals for a given two-input function. The logical 1 3 Figure. 6 4 -Input ND Gate or -Input NOR with oth Inputs Inverted 1 3 Figure 4. 6 4 -Input NND with Inverted Input or -Input OR Gate with Inverted Input 1 3 6 4 implementation is next to the board-level physical implementation of how the pins of the function should be connected. 1 3 Figure 3. Figure. 6 4 -Input NND with Inverted Input or -Input OR Gate with Inverted Input 1 3 6 4 -Input NOR Gate or -Input ND Gate with oth Inputs Inverted 1 3 6 4 74UP1G7 TinyLogic Low Power Universal onfigurable Two-Input Logic Gate Figure 6. -Input XNOR Gate Figure 7. Inverter 1 3 6 4 Figure 8. Non-Inverter uffer 008 Fairchild Semiconductor orporation www.fairchildsemi.com 74UP1G7 Rev. 1.0.4 4
bsolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit Supply oltage -0. 4.6 IN D Input oltage -0. 4.6 OUT D Output oltage HIGH or LOW State (1) -0. + 0. =0-0. 4.6 I IK D Input Diode urrent IN < 0-0 m I OK D Output Diode urrent OUT < 0-0 OUT > +0 I OH / I OL D Output Source / Sink urrent ±0 m I or I GND D or Ground urrent per Supply Pin ±0 m T STG Storage Temperature Range -6 +10 T J Junction Temperature Under ias +10 T L Junction Lead Temperature, Soldering 10s +60 P D ESD Power Dissipation at +8 MicroPak-6 130 MicroPak-6 10 Human ody Model, JEDE:JESD-114 000+ harged Device Model, JEDE:JESD-101 000 Note: 1. I O absolute maximum rating must be observed. Recommended Operating onditions () The Recommended Operating onditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to bsolute Maximum Ratings. Symbol Parameter onditions Min. Max. Unit Supply oltage 0.8 3.6 IN Input oltage 0 3.6 OUT I OH/I OL Output oltage Output urrent =0 0 3.6 HIGH or LOW State 0 =3.0 to 3.6 ±4.0 =.3 to.7 ±3.1 =1.6 to 1.9 ±1.9 =1.4 to 1.6 ±1.7 =1.1 to 1.3 ±1.1 m mw =0.8 ±0.0 µ T Operating Temperature, Free ir -40 +8 θ J Thermal Resistance MicroPak-6 00 MicroPak-6 60 Note:. Unused inputs must be held HIGH or LOW. They may not float. m /W 74UP1G7 TinyLogic Low Power Universal onfigurable Two-Input Logic Gate 008 Fairchild Semiconductor orporation www.fairchildsemi.com 74UP1G7 Rev. 1.0.4
D Electrical haracteristics Symbol Parameter onditions P N H OH OL I IN I OFF ΔI OFF I ΔI Positive Threshold oltage Negative Threshold oltage Hysteresis oltage HIGH Level Output oltage LOW Level Output oltage Input Leakage urrent Power Off Leakage urrent dditional Power Off Leakage urrent Quiescent Supply urrent Increase in I per Input T =+ T =-40 to +8 Min. Max. Min. Max. 0.80 0.30 0.60 0.30 0.60 1.10 0.3 0.90 0.3 0.90 1.40 0.74 1.11 0.74 1.11 1.6 0.91 1.9 0.91 1.9.30 1.37 1.77 1.37 1.77 3.00 1.88.9 1.88.9 0.80 0.10 0.60 0.10 0.60 1.10 0.6 0.6 0.6 0.6 1.40 0.39 0.7 0.39 0.7 1.6 0.47 0.84 0.47 0.84.30 0.69 1.04 0.69 1.04 3.00 0.88 1.4 0.88 1.4 0.80 0.07 0.0 0.07 0.0 1.10 0.08 0.46 0.08 0.46 1.40 0.18 0.6 0.18 0.6 1.6 0.7 0.66 0.7 0.66.30 0.3 0.9 0.3 0.9 3.00 0.79 1.31 0.79 1.31 0.80 3.60 I OH=-0µ -0.1-0.1 1.10 1.30 I OH=-1.1m 0.7 x 0.70 x 1.40 1.60 I OH=-1.7m 1.11 1.03 1.6 1.9 I OH=-1.9m 1.3 1.30.30.70 3.00 3.60 I OH=-.3m.0 1.97 I OH=-3.1m 1.90 1.8 I OH=-.7m.7.67 I OH=-4.0m.60. 0.80 3.60 I OL=0µ 0.10 0.10 1.10 1.30 I OL=1.1m 0.30 x 0.30 x 1.40 1.60 I OL=1.7m 0.31 0.37 1.6 1.9 I OL=1.9m 0.31 0.3.30.70.70 3.60 I OL=.3m 0.31 0.33 I OL=3.1m 0.44 0.4 I OL=.7m 0.31 0.33 I OL=4.0m 0.44 0.4 Units 0 to 3.6 0 IN 3.6 ±0.1 ±0. µ 0 0 ( IN, O) 3.6 0. 0.6 µ 0 to 0. 0.8 to 3.6 IN or O=0 to 3.6 0. 0.6 µ IN - or GND 0. 0.9 IN 3.6 ±0.9 3.3 IN= -0.6 40.0 0.0 µ µ 74UP1G7 TinyLogic Low Power Universal onfigurable Two-Input Logic Gate 008 Fairchild Semiconductor orporation www.fairchildsemi.com 74UP1G7 Rev. 1.0.4 6
Electrical haracteristics Symbol Parameter onditions t PHL, t PLH IN OUT PD Propagation Delay Input apacitance Output apacitance Power Dissipation apacitance 0.80 T =+ Min. Typ. Max Min. Max..1 1.10 1.30. 6. 1.6. 13.0 1.40 1.60. 4.6 7.6. 8. 1.6 1.9 L=pF, R L=1MΩ.0 3.9 6..0 6.8.30.70 1.7 3.1 4. 1.7.1 3.00 3.60 1.3.9 3.9 1.3 4.1 0.80 7.1 1.10 1.30 3. 7.6 14.4.8 14.9 1.40 1.60 L=10pF,.6.3 8.7.8 9.3 1.6 1.9 R L=1MΩ. 4.6 7.0. 7.8.30.70 1.9 3.7. 1.9.9 3.00 3.60 1.3.8 4.6 1.3 4.9 0.80 3.6 1.10 1.30 3.4 8.3 1.7 3.1 16.7 1.40 1.60 L=1pF,.8.8 9.4 3.1 10.4 1.6 1.9 R L=1MΩ..1 7.9. 8.7.30.70.1 4.0 6.1.1 6.9 3.00 3.60 1.3 3..0 1.3. 0.80.4 1.10 1.30 3.4 8.6 18. 3.4 19.0 1.40 1.60 L=30pF, 3.1. 10. 3.1 11.0 1.6 1.9 R L=1MΩ.1 4. 8.7.1 9..30.70 1. 3.4 6.9 1. 7.4 3.00 3.60 1.1.9.9 1.1 6.3 T =-40 to +8 Units Figure 0 0.8 pf 0 1.7 pf 0.80 1.8 1.10 1.30 1.8 1.40 1.60 IN=0 or, 1.8 1.6 1.9 f=10mhz 1.9.30.70.1 3.00 3.60.9 ns pf Figure 9 Figure 10 74UP1G7 TinyLogic Low Power Universal onfigurable Two-Input Logic Gate 008 Fairchild Semiconductor orporation www.fairchildsemi.com 74UP1G7 Rev. 1.0.4 7
Loadings and Waveforms Symbol Figure 9. Test ircuit Figure 10. Waveforms 3.3 ± 0.3. ± 0. 1.8 ± 0.1 1. ± 0.10 1. ± 0.10 0.8 mi / / / / / / mo / / / / / / 74UP1G7 TinyLogic Low Power Universal onfigurable Two-Input Logic Gate 008 Fairchild Semiconductor orporation www.fairchildsemi.com 74UP1G7 Rev. 1.0.4 8
Physical Dimensions X Notes: 0.0 PIN 1 IDENTIFIER 0.0 DETIL (0.0) 6X 0.MX 1.4 (0.4) TOP IEW 1.0 0. OTTOM IEW X 0.0 1.00 0.0 0.00 0. 0.1 1. ONFORMS TO JEDE STNDRD M0- RITION UD. DIMENSIONS RE IN MILLIMETERS 3. DRWING ONFORMS TO SME 14.M-1994 4. FILENME ND REISION: M06RE4. PIN ONE IDENTIFIER IS X LENGTH OF N OTHER LINE IN THE MRK ODE LOUT. Figure 11. 6-Lead, MicroPak, 1.0mm Wide 6X 0.3 0. 0.40 0.30 0.0 (0.49) X (0.) 1X PIN 1 0.10 0.0 X X (0.13) 4X 0.07 X 4 HMFER (1) (0.30) 6X REOMMENED LND PTTERN 0.10 0.00 6X 0.40 0.30 (0.7) 0.4 0.3 DETIL PIN 1 TERMINL Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. 74UP1G7 TinyLogic Low Power Universal onfigurable Two-Input Logic Gate lways visit Fairchild Semiconductor s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specifications Please visit Fairchild Semiconductor s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf. Package Designator Tape Section avity Number avity Status over Type Status L6X Leader (Start End) 1 (Typical) Empty Sealed arrier 000 Filled Sealed Trailer (Hub End) 7 (Typical) Empty Sealed 008 Fairchild Semiconductor orporation www.fairchildsemi.com 74UP1G7 Rev. 1.0.4 9
Physical Dimensions X X 0.3 0. NOTES: 0.0 PIN 1 MIN 0uM (0.08) 4X DETIL 0.3 1.00 TOP IEW SIDE IEW 1 3 6 4 OTTOM IEW 1.00. OMPLIES TO JEDE MO- STNDRD. DIMENSIONS RE IN MILLIMETERS.. DIMENSIONS ND TOLERNES PER SME 14.M, 1994 D. LNDPTTERN REOMMENDTION IS SED ON FS DESIGN. E. DRWING FILENME ND REISION: MGF06RE3 Figure 1. 0.MX 0.60 0.09 0.19 (0.08) 4X X 0.0 6X 0.0 0.10.0 X 0.40 1X 0.4 X 0. 1X 0.7 0.07X4 HMFER (0.0) 6X 0.89 0.3 6X 0.19 0.0 6X 0.66 REOMMENDED LND PTTERN FOR SPE ONSTRINED P 0.90 0.3 0.73 LTERNTIE LND PTTERN FOR UNIERSL PPLITION 0.40 0.30 DETIL PIN 1 LED SLE: X 6-Lead, MicroPak, 1x1mm ody,.3mm Pitch Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. 74UP1G7 TinyLogic Low Power Universal onfigurable Two-Input Logic Gate lways visit Fairchild Semiconductor s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specifications Please visit Fairchild Semiconductor s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/packaging/micropk_6l_tr.pdf. Package Designator Tape Section avity Number avity Status over Type Status Leader (Start End) 1 (Typical) Empty Sealed FHX arrier 000 Filled Sealed Trailer (Hub End) 7 (Typical) Empty Sealed 008 Fairchild Semiconductor orporation www.fairchildsemi.com 74UP1G7 Rev. 1.0.4 10
008 Fairchild Semiconductor orporation www.fairchildsemi.com 74UP1G7 Rev. 1.0.4 11 74UP1G7 TinyLogic Low Power Universal onfigurable Two-Input Logic Gate
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