MT884 8 x 2 Analog Switch Array Features Internal control latches and address decoder Short set-up and hold times Wide operating voltage: 4.5 to 3.2 2pp analog signal capability R ON 65Ω max. @ DD =2, 25 C R ON Ω @ DD =2, 25 C Full CMOS switch for low distortion Minimum feedthrough and crosstalk Separate analog and digital reference supplies Low power consumption technology Applications Key systems PBX systems Mobile radio Test equipment /instrumentation Analog/digital multiplexers Audio/ideo switching MT884AE MT884AP Description ISSUE 3 March 997 Ordering Information 4 Pin Plastic DIP 44 Pin PLCC -4 to 85 C The Mitel MT884 is fabricated in MITEL s ISO- CMOS technology providing low power dissipation and high reliability. The device contains a 8 x 2 array of crosspoint switches along with a 7 to 96 line decoder and latch circuits. Any one of the 96 switches can be addressed by selecting the appropriate seven address bits. The selected switch can be turned on or off by applying a logical one or zero to the DATA input. SS is the ground reference of the digital inputs. The range of the analog signal is from DD to EE. Chip Select (CS) allows the crosspoint array to be cascaded for matrix expansion. CS STROBE DATA RESET DD EE SS AX AX AX2 AX3 AY AY AY2 7 to 96 Decoder 96 Latches 96 8 x 2 Switch Array Xi I/O (i=-) Yi I/O (i=-7) Figure - Functional Block Diagram 3-33
MT884 Y3 AY2 RESET AX3 AX X6 X7 X8 X9 X X Y7 SS Y6 STROBE Y5 SS Pin Description 4 2 39 3 38 4 37 5 36 6 35 7 34 8 33 9 32 3 3 2 29 3 28 4 27 5 26 6 25 7 24 8 23 9 22 2 2 DD Y2 DATA Y CS Y X X X2 X3 X4 X5 AY AY AX2 AX Y4 AX X6 X7 X8 X9 X X Y7 SS 4 PIN PLASTIC DIP 44 PIN PLCC Figure 2 - Pin Connections AX3 RESET AY2 Y3 DD Y2 DATA Y CS 6 5 4 3 2 44434244 7 39 8 38 9 37 36 35 2 34 3 33 4 32 5 3 6 3 7 29 8 9 2 2 22 23 24 25 26 27 28 Y6 STROBE Y5 EE Y4 AX AX2 AY AY Y X X X2 X3 X4 X5 PDIP Pin # PLCC Name Description Y3 Y3 Analog (Input/Output): this is connected to the Y3 column of the switch 2 2 AY2 Y2 Address Line (Input). 3 3 RESET Master RESET (Input): this is used to turn off all switches regardless of the condition of CS. Active High. 4,5 4,7 AX3,AX X3 and X Address Lines (Inputs). 6,7 5,6,8 No Connection. 8-3 9-4 X6-X X6-X Analog (Inputs/Outputs): these are connected to the X6-X rows of the switch 4 5,8 No Connection 5 6 Y7 Y7 Analog (Input/Output): this is connected to the Y7 column of the switch 6 7 SS Digital Ground Reference. 7 9 Y6 Y6 Analog (Input/Output): this is connected to the Y6 column of the switch 8 2 STROBE STROBE (Input): enables function selected by address and data. Address must be stable before STROBE goes high and DATA must be stable on the falling edge of the STROBE. Active High. 9 2 Y5 Y5 Analog (Input/Output): this is connected to the Y5 column of the switch 2 22 EE Negative Power Supply. 2 23 Y4 Y4 Analog (Input/Output): this is connected to the Y4 column of the switch 22, 23 24,25 AX,AX2 X and X2 Address Lines (Inputs). 24, 25 26,27 AY,AY Y and Y Address Lines (Inputs). 26, 27 28-3 No Connection. 28-33 32-37 X5-X X5-X Analog (Inputs/Outputs): these are connected to the X5-X rows of the switch 34 38 No Connection. 35 39 Y Y Analog (Input/Output): this is connected to the Y column of the switch 3-34
MT884 Pin Description PDIP Pin # PLCC Name Description 36 4 CS Chip Select (Input): this is used to select the device. Active High. 37 4 Y Y Analog (Input/Output): this is connected to the Y column of the switch 38 42 DATA DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off the selected switch. Active High. 39 43 Y2 Y2 Analog (Input/Output): this is connected to the Y2 column of the switch 4 44 DD Positive Power Supply. Functional Description The MT884 is an analog switch matrix with an array size of 8 x 2. The switch array is arranged such that there are 8 columns by 2 rows. The columns are referred to as the Y inputs/outputs and the rows are the X inputs/outputs. The crosspoint analog switch array will interconnect any X I/O with any Y I/O when turned on and provide a high degree of isolation when turned off. The control memory consists of a 96 bit write only RAM in which the bits are selected by the address inputs (AY-AY2, AX-AX3). Data is presented to the memory on the DATA input. Data is asynchronously written into memory whenever both the CS (Chip Select) and STROBE inputs are high and are latched on the falling edge of STROBE. A logical written into a memory cell turns the corresponding crosspoint switch on and a logical turns the crosspoint off. Only the crosspoint switches corresponding to the addressed memory location are altered when data is written into memory. The remaining switches retain their previous states. Any combination of X and Y inputs/outputs can be interconnected by establishing appropriate patterns in the control memory. A logical on the RESET input will asynchronously return all memory locations to logical turning off all crosspoint switches regardless of whether CS is high or low. Two voltage reference pins ( SS and EE ) are provided for the MT884 to enable switching of negative analog signals. The range for digital signals is from DD to SS while the range for analog signals is from DD to EE. SS and EE pins can be tied together if a single voltage reference is needed. Address Decode The seven address inputs along with the STROBE and CS (Chip Select) are logically ANDed to form an enable signal for the resettable transparent latches. The DATA input is buffered and is used as the input to all latches. To write to a location, RESET must be low and CS must go high while the address and data are set up. Then the STROBE input is set high and then low causing the data to be latched. The data can be changed while STROBE is high, however, the corresponding switch will turn on and off in accordance with the DATA input. DATA must be stable on the falling edge of STROBE in order for correct data to be written to the latch. 3-35
MT884 Absolute Maximum Ratings*- oltages are with respect to EE unless otherwise stated. Parameter Symbol Min Max Units Supply oltage DD -.3 SS -.3 * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. 6. DD +.3 2 Analog Input oltage INA -.3 DD +.3 3 Digital Input oltage IN SS -.3 DD +.3 4 Current on any I/O Pin I ±5 ma 5 Storage Temperature T S -65 +5 C 6 Package Power Dissipation PLASTIC DIP P D.6 W Recommended Operating Conditions - oltages are with respect to EE unless otherwise stated. Characteristics Sym Min Typ Max Units Test Conditions Operating Temperature T O -4 25 85 C 2 Supply oltage DD SS 4.5 EE 3.2 DD -4.5 3 Analog Input oltage INA EE DD 4 Digital Input oltage IN SS DD DC Electrical Characteristics - oltages are with respect to EE = SS =, DD =2 unless otherwise stated. Characteristics Sym Min Typ Max Units Test Conditions Quiescent Supply Current I DD µa All digital inputs at IN = SS or DD.4.5 ma All digital inputs at IN =2.4 + SS ; SS =7. 5 5 ma All digital inputs at IN =3.4 2 Off-state Leakage Current (See G.9 in Appendix) I OFF ± ±5 na I Xi - Yj I = DD - EE See Appendix, Fig. A. 3 Input Logic level IL.8+ SS SS =7.5; EE = 4 Input Logic level IH 2.+ SS SS =6.5; EE = 5 Input Logic level IH 3.3 6 Input Leakage (digital pins) I LEAK. µa All digital inputs at IN = SS or DD DC Electrical Characteristics are over recommended temperature range. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. DC Electrical Characteristics- Switch Resistance - DC is the external DC offset applied at the analog I/O pins. Characteristics Sym 25 C 7 C 85 C Units Test Conditions On-state DD =2 Resistance DD = DD = 5 (See G., G.2, G.3 in Appendix) 2 Difference in on-state resistance between two switches (See G.4 in Appendix) R ON 45 55 2 Typ Max Typ Max Typ Max 65 75 85 75 85 25 8 9 225 Ω Ω Ω SS = EE =, DC = DD /2, I Xi - Yj I =.4 See Appendix, Fig. A.2 R ON 5 Ω DD =2, SS = EE =, DC = DD /2, I Xi - Yj I =.4 See Appendix, Fig. A.2 3-36
MT884 AC Electrical Characteristics - Crosspoint Performance-oltages are with respect to DD =5, SS =, EE =-7, unless otherwise stated. Characteristics Sym Min Typ Max Units Test Conditions Switch I/O Capacitance C S 2 pf f= MHz 2 Feedthrough Capacitance C F.2 pf f= MHz 3 Frequency Response Channel ON 2LOG( OUT / Xi )=-3dB 4 Total Harmonic Distortion (See G.5, G.6 in Appendix) 5 Feedthrough Channel OFF Feed.=2LOG ( OUT / Xi ) (See G.8 in Appendix) 6 Crosstalk between any two channels for switches Xi-Yi and Xj-Yj. Xtalk=2LOG ( Yj / Xi ). (See G.7 in Appendix). 7 Propagation delay through switch F 3dB 45 MHz Switch is ON ; INA = 2pp sinewave; R L = kω See Appendix, Fig. A.3 THD. % Switch is ON ; INA = 2pp sinewave f= khz; R L =kω FDT -95 db All Switches OFF ; INA = 2pp sinewave f= khz; R L = kω. See Appendix, Fig. A.4 X talk -45 db INA =2pp sinewave f= MHz; R L = 75Ω. -9 db INA =2pp sinewave f= khz; R L = 6Ω. -85 db INA =2pp sinewave f= khz; R L = kω. -8 db INA =2pp sinewave f= khz; R L = kω. Refer to Appendix, Fig. A.5 for test circuit. t PS 3 ns R L =kω; C L =5pF Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Crosstalk measurements are for Plastic DIPS only, crosstalk values for PLCC packages are approximately 5dB better. AC Electrical Characteristics - Control and I/O Timings- oltages are with respect to DD =5, SS =, EE =-7, unless otherwise stated. Characteristics Sym Min Typ Max Units Test Conditions Control Input crosstalk to switch (for CS, DATA, STROBE, Address) CX talk 3 mpp IN =3 square wave; R IN =kω, R L =kω. See Appendix, Fig. A.6 2 Digital Input Capacitance C DI pf f=mhz 3 Switching Frequency F O 2 MHz 4 Setup Time DATA to STROBE t DS ns R L = kω, C L =5pF ➀ 5 Hold Time DATA to STROBE t DH ns R L = kω, C L =5pF ➀ 6 Setup Time Address to STROBE t AS ns R L = kω, C L =5pF ➀ 7 Hold Time Address to STROBE t AH ns R L = kω, C L =5pF ➀ 8 Setup Time CS to STROBE t CSS ns R L = kω, C L =5pF ➀ 9 Hold Time CS to STROBE t CSH ns R L = kω, C L =5pF ➀ STROBE Pulse Width t SPW 2 ns R L = kω, C L =5pF ➀ RESET Pulse Width t RPW 4 ns R L = kω, C L =5pF ➀ 2 STROBE to Switch Status Delay t S 4 ns R L = kω, C L =5pF ➀ 3 DATA to Switch Status Delay t D 5 ns R L = kω, C L =5pF ➀ 4 RESET to Switch Status Delay t R 35 ns R L = kω, C L =5pF ➀ Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details. Digital Input rise time (tr) and fall time (tf) = 5ns. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. ➀ Refer to Appendix, Fig. A.7 for test circuit. 3-37
MT884 t CSS t CSH CS 5% 5% t RPW RESET t SPW 5% 5% STROBE 5% 5% 5% t AS ADDRESS 5% 5% t AH DATA 5% 5% t DS t DH SWITCH* ON OFF t D t S t R t R Figure 3 - Control Memory Timing Diagram * See Appendix, Fig. A.7 for switching waveform ➀ AX AX AX2 AX3 AY AY AY2 Connection Table. Address Decode Truth Table This address has no effect on device status. X-Y X-Y X2-Y X3-Y X4-Y X5-Y No Connection No Connection X6-Y X7-Y X8-Y X9-Y X-Y X-Y No Connection ➀ No Connection ➀ X-Y X-Y X-Y2 X-Y2 X-Y3 X-Y3 X-Y4 X-Y4 X-Y5 X-Y5 X-Y6 X-Y6 X-Y7 X-Y7 3-38