REVISION ISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Jul.25.2004 Rev. 2.0 Revised ISB(max) : 0.5mA => 1.25mA May.11.2006 Rev. 2.1 Revised Package Outline Dimension(TSOP-II) Apr.12.2007 Rev. 2.2 Deleted Spec. Added S Spec. Revised Test Condition of ICC/ISB1/IDR Revised VTERM to VT1 and VT2 Nov.8.2007 Rev. 2.3 Revised IDR Mar.21.2008 Mar.30.2009 Rev. 2.4 Added ISB1/IDR values when TA = 25 and TA = 40 Revised FEATURES & ORDERING INFORMATION ead free and green package available to Green package available Added packing type in ORDERING INFORMATION Deleted TSODER in ABSOUTE MAXIMUN RATINGS Rev. 2.5 Revised PACKAGE OUTINE DIMENSION in page 10 May.6.2010 Rev. 2.6 Revised ORDERING INFORMATION in page 11 Aug.30.2010 Rev. 2.7 Revised Notes of READ CYCE of TIMING WAVEFORMS in page 5 Jan.7.2016 Rev. 2.8 Corrected ORDERING INFORMATION Typo. May.20.2016 Rev. 2.9 Deleted WRITE CYCE Notes : 1. WE#,, B#, UB# must be high during all address transitions. in page 7 Jun.29.2016 Revised twp(min) in AC EECTRICA CARACTERISTICS Sep.11.2017 0
FEATURES Fast access time : 45/55/70ns ow power consumption: Operating current : 40/30/20mA (TYP.) Standby current : 2 A (TYP.) -version 1 A (TYP.) S-version Single 2.7V ~ 3.6V power supply All inputs and outputs TT compatible Fully static operation Tri-state output Data byte control : B# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15) Data retention voltage : 1.5V (MIN.) Green package available Package : 44-pin 400mil TSOP II 48-ball 6mm x 8mm TFBGA GENERA DESCRIPTION The is a 4,194,304-bit low power CMOS static random access memory organized as 262,144 words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. The operates from a single power supply of 2.7V ~ 3.6V and all inputs and outputs are fully TT compatible PRODUCT FAMIY Product Operating Power Dissipation VCC Range Speed Family Temperature Standby(ISB1,TYP.) Operating(ICC,TYP.) 0 ~ 70 2.7 ~ 3.6V 45/55/70ns 2µA()/1µA(S) 40/30/20mA (E) -20 ~ 80 2.7 ~ 3.6V 45/55/70ns 2µA()/1µA(S) 40/30/20mA (I) -40 ~ 85 2.7 ~ 3.6V 45/55/70ns 2µA()/1µA(S) 40/30/20mA FUNCTIONA BOCK DIAGRAM PIN DESCRIPTION SYMBO DESCRIPTION Vcc Vss A0 - A17 Address Inputs DQ0 DQ15 Data Inputs/Outputs A0-A17 DECODER 256Kx16 MEMORY ARRAY WE# Chip Enable Input Write Enable Input OE# Output Enable Input B# ower Byte Control UB# Upper Byte Control VCC Power Supply DQ0-DQ7 ower Byte DQ8-DQ15 Upper Byte I/O DATA CIRCUIT COUMN I/O VSS Ground WE# OE# B# UB# CONTRO CIRCUIT 1
PIN CONFIGURATION A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 DQ3 Vcc Vss DQ4 DQ5 DQ6 DQ7 WE# A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 XXXXXXXX XXXXXXXX 22 23 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 A5 A6 A7 OE# UB# B# DQ15 DQ14 DQ13 DQ12 Vss Vcc DQ11 DQ10 DQ9 DQ8 NC A8 A9 A10 A11 A12 TSOP II A B# OE# A0 A1 A2 NC B DQ8 UB# A3 A4 DQ0 C D E F DQ9 DQ10 A5 Vss DQ11 A17 Vcc DQ12 NC DQ14 DQ13 A14 A6 A7 A16 A15 DQ1 DQ3 DQ4 DQ5 DQ2 Vcc Vss DQ6 XXXXXXXX XXXXXXXX G DQ15 NC A12 A13 WE# DQ7 NC A8 A9 A10 A11 NC 1 2 3 4 5 6 TFBGA(See through with Top View) TFBGA(Top View) 2
ABSOUTE MAXIMUN RATINGS* PARAMETER SYMBO RATING UNIT Voltage on VCC relative to VSS VT1-0.5 to 4.6 V Voltage on any other pin relative to VSS VT2-0.5 to VCC+0.5 V 0 to 70(C grade) Operating Temperature TA -20 to 80(E grade) -40 to 85(I grade) Storage Temperature TSTG -65 to 150 Power Dissipation PD 1 W DC Output Current IOUT 50 ma *Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUT TABE MODE OE# WE# B# UB# X Standby X X Output Disable Read X Write X X Note: = VI, = VI, X = Don't care. X X X X X X I/O OPERATION DQ0 - DQ7 DQ8 - DQ15 igh-z igh-z igh-z igh-z igh-z igh-z igh-z igh-z DOUT igh-z igh-z DOUT DOUT DIN igh-z DIN DOUT igh-z DIN DIN SUPPY CURRENT ISB,ISB1 ICC,ICC1 ICC,ICC1 ICC,ICC1 3
DC EECTRICA CARACTERISTICS PARAMETER SYMBO TEST CONDITION MIN. TYP. *4 MAX. UNIT Supply Voltage VCC 2.7 3.0 3.6 V Input igh Voltage VI *1 2.2 - VCC+0.3 V Input ow Voltage VI *2-0.2-0.6 V Input eakage Current II VCC VIN VSS - 1-1 µa Output eakage VCC VOUT VSS, IO Current Output Disabled - 1-1 µa Output igh Voltage VO IO = -1mA 2.2 2.7 - V Output ow Voltage VO IO = 2mA - - 0.4 V Average Operating Power supply Current Standby Power Supply Current ICC ICC1 Cycle time = MIN. = VI, II/O = 0mA Other pins at VI or VI Cycle time = 1µs = 0.2V, II/O = 0mA Other pins at 0.2V or VCC - 0.2V - 45-40 50 ma - 55-30 40 ma - 70-20 30 ma - 4 5 ma ISB = VI, other pins at VI or VI - 0.3 1.25 ma - 2 15 µa E/I - 2 20 µa ISB1 VCC - 0.2V Others at 0.2V or VCC - 0.2V S *5 SE *5 SI *5 25-1 3 µa 40-1 3 µa S - 1 10 µa SE/SI - 1 12 µa Notes: 1. VI(max) = VCC + 3.0V for pulse width less than 10ns. 2. VI(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(TYP.) and TA = 25 5. This parameter is measured at V CC = 3.0V 4
CAPACITANCE (T A = 25, f = 1.0Mz) PARAMETER SYMBO MIN. MAX. UNIT Input Capacitance CIN - 6 pf Input/ Output Capacitance CI/O - 8 pf Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse evels 0.2V to VCC - 0.2V Input Rise and Fall Times 3ns Input and Output Timing Reference evels 1.5V Output oad C = 30pF + 1TT, IO/IO = -1mA/2mA AC EECTRICA CARACTERISTICS (1) READ CYCE PARAMETER SYM. -45-55 -70 MIN. MAX. MIN. MAX. MIN. MAX. UNIT Read Cycle Time trc 45-55 - 70 - ns Address Access Time taa - 45-55 - 70 ns Chip Enable Access Time tace - 45-55 - 70 ns Output Enable Access Time toe - 25-30 - 35 ns Chip Enable to Output in ow-z tcz* 10-10 - 10 - ns Output Enable to Output in ow-z toz* 5-5 - 5 - ns Chip Disable to Output in igh-z tcz* - 15-20 - 25 ns Output Disable to Output in igh-z toz* - 15-20 - 25 ns Output old from Address Change to 10-10 - 10 - ns B#, UB# Access Time tba - 45-55 - 70 ns B#, UB# to igh-z Output tbz* - 20-25 - 30 ns B#, UB# to ow-z Output tbz* 10-10 - 10 - ns (2) WRITE CYCE PARAMETER SYM. -45-55 -70 MIN. MAX. MIN. MAX. MIN. MAX. UNIT Write Cycle Time twc 45-55 - 70 - ns Address Valid to End of Write taw 40-50 - 60 - ns Chip Enable to End of Write tcw 40-50 - 60 - ns Address Set-up Time tas 0-0 - 0 - ns Write Pulse Width twp 30-35 - 45 - ns Write Recovery Time twr 0-0 - 0 - ns Data to Write Time Overlap tdw 20-25 - 30 - ns Data old from End of Write Time td 0-0 - 0 - ns Output Active from End of Write tow* 5-5 - 5 - ns Write to Output in igh-z twz* - 15-20 - 25 ns B#, UB# Valid to End of Write tbw 35-45 - 60 - ns *These parameters are guaranteed by device characterization, but not production tested. 5
TIMING WAVEFORMS READ CYCE 1 (Address Controlled) (1,2) Address trc taa to Dout Previous Data Valid Data Valid READ CYCE 2 ( and OE# Controlled) (1,3,4,5) Address trc taa B#,UB# tace OE# tba tbz tcz toz toe *6 to toz tbz tcz Dout igh-z Data Valid igh-z Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, = low, B# or UB# = low. 3.Address must be valid prior to or coincident with = low, B# or UB# = low transition; otherwise taa is the limiting parameter. 4.tCZ, tbz, toz, tcz, tbz and toz are specified with C = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tcz is less than tcz, tbz is less than tbz, toz is less than toz. 6. = low, B# or UB# = low transition must be at least 25ns prior to OE# = low transition; otherwise tba is the limiting parameter. 6
WRITE CYCE 1 (WE# Controlled) (1,2,4,5) twc Address taw tcw tbw B#,UB# tas twp twr WE# twz tow Dout (4) igh-z (4) tdw td Din Data Valid WRITE CYCE 2 ( Controlled) (1,4,5) twc Address taw tas twr B#,UB# tbw tcw twp WE# Dout twz (4) igh-z tdw td Din Data Valid 7
WRITE CYCE 3 (B#,UB# Controlled) (1,4,5) twc Address taw twr B#,UB# tas tcw tbw twp WE# Dout (4) twz igh-z tdw td Din Data Valid Notes : 1.A write occurs during the overlap of a low, low WE#, B# or UB# = low. 2.During a WE# controlled write cycle with OE# low, twp must be greater than twz + tdw to allow the drivers to turn off and data to be placed on the bus. 3.During this period, I/O pins are in the output state, and input signals must not be applied. 4.If the, B#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 5.tOW and twz are specified with C = 5pF. Transition is measured ±500mV from steady state. 8
DATA RETENTION CARACTERISTICS PARAMETER SYMBO TEST CONDITION MIN. TYP. MAX. UNIT VCC for Data Retention VDR VCC - 0.2V 1.5-3.6 V - 1.0 12 µa E/I - 1.0 16 µa Data Retention Current IDR VCC = 1.5V S 25-0.5 2.5 µa VCC - 0.2V SE Others at 0.2V or VCC-0.2V SI 40-0.5 2.5 µa S - 0.5 8 µa SE/SI - 0.5 10 µa Chip Disable to Data Retention Time tcdr See Data Retention Waveforms (below) 0 - - ns Recovery Time tr trc* - - ns trc* = Read Cycle Time DATA RETENTION WAVEFORM ow VCC Data Retention Waveform (1) ( controlled) VDR 1.5V Vcc Vcc(min.) Vcc(min.) tcdr tr VI Vcc-0.2V VI ow VCC Data Retention Waveform (2) (B#, UB# controlled) VDR 1.5V Vcc Vcc(min.) Vcc(min.) tcdr tr B#,UB# VI B#,UB# Vcc-0.2V VI 9
PACKAGE OUTINE DIMENSION 44-pin 400 mil TSOP Ⅱ Package Outline Dimension SYMBOS DIMENSIONS IN MIMETERS DIMENSIONS IN MIS MIN. NOM. MAX. MIN. NOM. MAX. A - - 1.20 - - 47.2 A1 0.05 0.10 0.15 2.0 3.9 5.9 A2 0.95 1.00 1.05 37.4 39.4 41.3 b 0.30-0.45 11.8-17.7 c 0.12-0.21 4.7-8.3 D 18.212 18.415 18.618 717 725 733 E 11.506 11.760 12.014 453 463 473 E1 9.957 10.160 10.363 392 400 408 e - 0.800 - - 31.5-0.40 0.50 0.60 15.7 19.7 23.6 ZD - 0.805 - - 31.7 - y - - 0.076 - - 3 Θ 0 o 3 o 6 o 0 o 3 o 6 o 10
48-ball 6mm 8mm TFBGA Package Outline Dimension 11
ORDERING INFORMATION Package Type 44-pin (400mil) TSOP II Access Time (Speed)(ns) Power Type 45 Special Ultra ow Power Ultra ow Power 55 Special Ultra ow Power Ultra ow Power 70 Special Ultra ow Power Ultra ow Power Temperature Range( ) Packing Type yontek Item No. 0 ~70 Tray M-45S Tape Reel M-45ST -20 ~80 Tray M-45SE Tape Reel M-45SET -40 ~85 Tray M-45SI Tape Reel M-45SIT 0 ~70 Tray M-45 Tape Reel M-45T -20 ~80 Tray M-45E Tape Reel M-45ET -40 ~85 Tray M-45I Tape Reel M-45IT 0 ~70 Tray M-55S Tape Reel M-55ST -20 ~80 Tray M-55SE Tape Reel M-55SET -40 ~85 Tray M-55SI Tape Reel M-55SIT 0 ~70 Tray M-55 Tape Reel M-55T -20 ~80 Tray M-55E Tape Reel M-55ET -40 ~85 Tray M-55I Tape Reel M-55IT 0 ~70 Tray M-70S Tape Reel M-70ST -20 ~80 Tray M-70SE Tape Reel M-70SET -40 ~85 Tray M-70SI Tape Reel M-70SIT 0 ~70 Tray M-70 Tape Reel M-70T -20 ~80 Tray M-70E Tape Reel M-70ET -40 ~85 Tray M-70I Tape Reel M-70IT 12
ORDERING INFORMATION Package Type 48-ball (6mm x 8mm) TFBGA Access Time (Speed)(ns) Power Type 45 Special Ultra ow Power Ultra ow Power 55 Special Ultra ow Power Ultra ow Power 70 Special Ultra ow Power Ultra ow Power Temperature Range( ) Packing Type yontek Item No. 0 ~70 Tray G-45S Tape Reel G-45ST -20 ~80 Tray G-45SE Tape Reel G-45SET -40 ~85 Tray G-45SI Tape Reel G-45SIT 0 ~70 Tray G-45 Tape Reel G-45T -20 ~80 Tray G-45E Tape Reel G-45ET -40 ~85 Tray G-45I Tape Reel G-45IT 0 ~70 Tray G-55S Tape Reel G-55ST -20 ~80 Tray G-55SE Tape Reel G-55SET -40 ~85 Tray G-55SI Tape Reel G-55SIT 0 ~70 Tray G-55 Tape Reel G-55T -20 ~80 Tray G-55E Tape Reel G-55ET -40 ~85 Tray G-55I Tape Reel G-55IT 0 ~70 Tray G-70S Tape Reel G-70ST -20 ~80 Tray G-70SE Tape Reel G-70SET -40 ~85 Tray G-70SI Tape Reel G-70SIT 0 ~70 Tray G-70 Tape Reel G-70T -20 ~80 Tray G-70E Tape Reel G-70ET -40 ~85 Tray G-70I Tape Reel G-70IT 13
TIS PAGE IS EFT BANK INTENTIONAY. 14