Week 5 Dr. David Ward Hybrid Embedded Systems

Week 5 Dr. David Ward Hybrid Embedded Systems

Today s Agenda Discuss Homework and Labs HW #2 due September 24 (this Friday by midnight) Don t start Lab # 5 until next week Work on HW #2 in today s lab Project Proposal VGA Basics Verilog example Chapter 7.7 textbook SOPC Builder ftp://ftp.altera.com/up/pub/university_program_ip_cores/v GA.pdf

Proposal Each student should submit a one- or two-page written project proposal. You should crystallize the details of your project You should focus your energies on producing a high quality project The proposal should include enough detail to convince the reader that you've found a good project You understand the complexity of your project You should map out a plan for how to implement it and complete it on schedule You should have an idea about which experiments you might run to test the success of your implementation Please do not be vague in your written proposal After submitting your project proposal, schedule a half-hour meeting with instructor. If needed, we will make any adjustments in the scope or detail of your project

Proposal Outline Example Goal What am I going to do? Who would benefit? What will you build? What will you demonstrate? Resources What equipment/hardware and software will you require? Where and how will you get such resources Problem Statement Why is it hard? How hard is it? Previous Work What have others tried? Approach What approach am I going to try? Why do you think it will work well? What parts do you expect to be difficult, and which will be easy? Methodology What steps (task list) are required? Which of these steps is particularly hard? What to do if the hard steps don't work out? Metrics How will I measure success? Timeline Give a timeline e indicating what each group member will accomplish each week until the project is completed (from task list) I would recommend that you have a working prototype ready to demonstrate midway (week 11-12)

Chapter 7.7 7 (Textbook)

Horizontal Synchronization

Vertical Synchronization

Character Display Hardware MonitorSynch characterpointer CharacterMatrix MaxtrixSlice characterpixel

MonitorSynch 800 cycles to complete Horizontal Synch

CharacterPointer Selects a 8x8 character (4800 total)

MatrixSlice Character range 32-95 Flat memory 512 bytes needed to store characters

CharacterPixel

TestBench w/ DualPort RAM Can display current content while writing new data

Altera University IP Core

VGA Core Block Diagram

Altera VGA Core Drives Di the signals for VGADiitlt Digital-to-Analog l Converter (DAC) Horizontal and Vertical synchronization signals 640x480 @ refresh of 60 frames/sec 25Mhz input clock Slave ports run at 50Mhz Pixel Character Supports pixel or character input Pixel l SRAM Avalon_pixel_slave Character On-chip memory Avalon_character_slave Flat contiguous memory space (simple memory interface) Can be used with other SOPC components using SOPC Builder

Pixel Mode User can provide the color of each pixel lto the Avalon Interface Avalon_pixel_slave Uses SRAM as pixel buffer Suitable for animation or image display Color C l Setting RGB color model 16 bit color mode Red and blue have 5-bit color spaces Green G has 6-bit color space 8-bit color mode for grayscale Resolution Supports 640x480 => 307,200 pixels Support t mega pixel for lower resolution 80 x 60. Each mega pixel is 8 x 8 pixel group 320 x 240. Each mega pixel is 2 x 2 pixel group

Character Mode Operates O t on characters Characters are sent to VGA Core Avalon_char_slave Handles conversion of characters to pixel Initializes I or reset tvga core to space No display Clear screen by writing 1 to highest memory location Color Setting 9-bit color mode. Each color has a 3-bit color space 8-bit color mode. 4-bit color mode 1-bit color mode. Characters are drawn in white with transparent tbackground

Character Size

Address Format

Data Format (Pixel Slave)

Data Format (Character)

SOPC Builder Instantiation

VGA Functions

RGB Color Table