NOTE: Explanation Refer Class Notes Digital Circuits(15EECC203) INTRODUCTION TO SEQUENTIAL CIRCUITS by Nagaraj Vannal, Asst.Professor, School of Electronics Engineering, K.L.E. Technological University, Hubballi. nagaraj_vannal@bvb.edu
INTRODUCTION TO SEQUENTIAL CIRCUITS (Planned Hours:10hours) Lesson Schedule: 1. Basic Bistable Element, Latches, A SR Latch 2. Application of SR Latch, A Switch Debouncer 3. The SR Latch, The gated SR Latch, The gated D Latch 4. The Master-Slave Flip-Flops (Pulse-Triggered Flip-Flops) 5. The Master-Slave SR Flip-Flops 6. The Master-Slave JK Flip-Flop, 7. Edge Triggered Flip-Flop, 8. The Positive Edge-Triggered D Flip-Flop, 9. Negative-Edge Triggered D Flip-Flop, 10. Characteristic Equations
The discussion so far... Logical operations which respond to combinations of inputs to produce an output. Call these combinational logic circuits. For example, can add two numbers. But: No way of remembering or storing information after inputs have been removed. To handle this, we need sequential logic capable of storing intermediate (and final) results.
Sequential Circuits Inputs.. Combinational Logic Gates.. Outputs Clock Memory Elements (Flip-Flops) Clock a periodic external event (input) Clock
The Basic Bistable Element A flip-flop is a bi-stable device: a circuit having 2 stable conditions (0 or 1) A stable value can be stored at inverter outputs 0 1 1 0 State 1 State 2
SR Latch An SR (or set-reset) latch consists of S (set) input: set the circuit R (reset) input: reset the circuit Q and Q output: output of the SR latch in normal and complement form
An application of the SR latch Digital Circuits(15EECC203) (a) Effects of contact bounce. (b) A switch debouncer.
S R Latch Digital Circuits(15EECC203)
S-R Latch with control input or Gated SR Latch Occasionally, desirable to avoid latch changes C = 0 disables all latch state changes Control signal enables data change when C = 1 Right side of circuit same as ordinary S-R latch
NOR S-R Latch with Control Input Latch is level-sensitive, in regards to C Only stores data if C = 0 Digital Circuits(15EECC203) R Q C Latch operation enabled by C S Input sampling enabled by gates Nagaraj Vannal, Asst. Professor, Dept. of IT, BVBCET Hubli Q Outputs change when C is low: RESET and SET Otherwise: HOLD 10
Gated D Latch Digital Circuits(15EECC203) Q 0 indicates the previous state (the previously stored value) D X Q C S Y R Q D C Q Q 0 1 0 1 1 1 1 0 X 0 Q 0 Q 0 X Y C Q Q 0 0 1 Q 0 Q 0 Store 0 1 1 0 1 Reset 1 0 1 1 0 Set 1 1 1 1 1 Disallowed X X 0 Q 0 Q 0 Store
Summary Digital Circuits(15EECC203) Latches are based on combinational gates (e.g. NAND, NOR) Latches store data even after data input has been removed S-R latches operate like cross-coupled inverters with control inputs (S = set, R = reset) With additional gates, an S-R latch can be converted to a D latch (D stands for data) D latch is simple to understand conceptually When C = 1, data input D stored in latch and output as Q When C = 0, data input D ignored and previous latch value output at Q Next time: more storage elements!
Timing Consideration When using a real flip-flop, the following information is needed to be considered: propagation delay (t plh, t phl ) - time needed for an input signal to produce an output signal minimum pulse width (t w(min) ) - minimum amount of time a signal must be applied setup and hold time (t su, t h ) - minimum time the input signal must be held fixed before and after the latching action
Propagation delays in an SR latch Nagaraj Vannal, Asst. Professor, Dept. of IT, BVBCET Hubli 14
Timing diagram for an SR latch Digital Circuits(15EECC203)
Minimum pulse width constraint This is the minimum amount of time a signal must be applied in order to produce a desired result. Failure to satisfy this constraint may not cause the intended change or possibly have the latch enter metastable state.
Timing diagram for a gated D latch The minimum time the D signal must be held fixed before the latching action is called the setup time. While the minimum time the D signal must be held fixed after the latching action is called Hold time.
Unpredictable response in a gated D latch Failure to the satisfy setup time and hold time constraints can result in unpredictable output behavior, including metastablility. Unpredictable behavior occurs when latching is attempted at time t12 since the signal on the D line changed at time t11, which is assumed to have occurred within the setup time of the gated D latch Nagaraj Vannal, Asst. Professor, Dept. of IT, BVBCET Hubli 18
J K Flip-Flop J K CLK Q Q 0 0 0 No Change 0 1 0 Clear 1 0 1 Set 1 1 Toggle Q 0 : Rising Edge of Clock Q: Complement of Q
J K Flip-Flop: Example Timing SET TOGGLE TOGGLE CLEAR NO CHANGE SET NO CHANGE Q J K CLK
T Flip-Flop
D Flip-Flop D Q D CLK Q Q 0 0 1 CLK Q 1 1 0 : Rising Edge of Clock
D Flip-Flop: Example Timing Q=D=1 Q=D=0 Q=D=0 No Change Q=D=1 Q=D=1 No Change Q=D=0 Q=D=0 No Change Q D CLK
Master-slave JK flip-flop
Timing diagram for master-slave JK flip-flop
Master-slave SR flip-flop
Timing diagram for a master-slave SR flip-flop Nagaraj Vannal, Asst. Professor, Dept. of IT, BVBCET Hubli 27
Flip-Flop Vs. Latch The primary difference between a D flip-flop and D latch is the EN/CLOCK input. The flip-flop s CLOCK input is edge sensitive, meaning the flip-flop s output changes on the edge (rising or falling) of the CLOCK input. The latch s EN input is level sensitive, meaning the latch s output changes on the level (high or low) of the EN input.
Clock Edges Digital Circuits(15EECC203) Positive Edge Transition 1 0 1 0 Negative Edge Transition
POS & NEG Edge Triggered D Positive Edge Trigger Digital Circuits(15EECC203) D Q D CLK Q Q 0 0 1 CLK Q 1 1 0 : Rising Edge of Clock Negative Edge Trigger D CLK Q Q D Q 0 0 1 CLK Q 1 1 0 : Falling Edge of Clock
POS & NEG Edge Triggered J/K J CLK K J CLK K Positive Edge Trigger Q Q Negative Edge Trigger Q Q J K CLK 0 0 0 1 0 1 0 1 1 1 : Rising Edge of Clock J K CLK 0 0 Q Q 0 Q 0 0 1 0 1 0 1 1 1 : Rising Edge of Clock Nagaraj Vannal, Asst. Professor, Dept. of IT, BVBCET Hubli Q Q 0 Q 0 31
Positive-edge-triggered D flip-flop
Timing diagram for a positive-edgetriggered D flip-flop
do not require the presence of a control signal preset (PR) - set the flip-flop clear (CLR) - reset the flip-flop Asynchronous Inputs useful to bring a flip-flop to a desired initial state Set the FF to 1/0 states at any time. Digital Circuits(15EECC203)
Asynchronous Inputs
Positive-edge-triggered D flipflop with asynchronous inputs
Positive-edge-triggered JK flip-flop
Clocked J-K Flip Flop Two data inputs, J and K J -> set, K -> reset, if J=K=1 then toggle output Digital Circuits(15EECC203) Characteristic Table
Positive-edgetriggered T flip-flop Digital Circuits(15EECC203)
Characteristic Equations algebraic descriptions of the next-state table of a flip-flop constructing from the Karnaugh map for Q t+1 in terms of the present state and input
Characteristic Equations Derivation Refer class Notes
Flip Flop Conversion For the conversion of one flip flop to another, a combinational circuit has to be designed first. If a JK Flip Flop is required, the inputs are given to the combinational circuit and the output of the combinational circuit is connected to the inputs of the actual flip flop. Thus, the output of the actual flip flop is the output of the required flip flop.
SR Flip Flop to JK Flip Flop
JK Flip Flop to SR Flip Flop
SR Flip Flop to D Flip Flop
D Flip Flop to SR Flip Flop
JK Flip Flop to T Flip Flop
JK Flip Flop to D Flip Flop
D Flip Flop to JK Flip Flop
555 Timer (Refer the Other PPT) Metastability Other important topics Race around condition https://www.youtube.com/watch?v=trpgho7mpnw 1 s and 0 s catching Drawing the output waveforms for given input and so on.
References http://www.play-hookey.com/digital/ http://web.cecs.pdx.edu/~mcnames/ece171/ http://www.allaboutcircuits.com Class Notes Lab Experiments
DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR