Zen and the Art of On-Wafer Probing A Personal Perspective

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Transcription:

Zen and the Art of On-Wafer Probing A Personal Perspective Rob Sloan School E&EE, University of Manchester - after Robert Pirsig

Device or Circuit Measurement at Microwave/ Millimetre-wave/ THz frequencies On-wafer Probes, typically GSG, connected to SMUs and VNAs

Device Modelling From Physical layers Engineering layers

Solid-state Power vs. frequency 20 db of gain at 670 GHz Fabricated by Northrop Grumman under DARPA THz Electronics Program* Several high frequency processes and research programmes, dot7, DARPA THz Transistor, Teledyne, HRL, NGST, Infineon. Designing into these processes requires good models got from good device measurements.

On-Wafer Probing - Calibration In measuring a device we need to calibrate the network analyser. This removes the systematic errors associated with cables and the receiver. Usual on-wafer model is based upon a 16-term error model which can be simplified if the two leakage terms are is zeroed and the source switch is behind the reflectometers usually down to an 8-term error model (or 7 normalised). Errors Corrected: Ports match Coupler directivity Tracking Leakage a 0 a 0 a 1 b 0 a 3 e 10 e 00 e 20 e 13 e 11 e 30 e 03 e 01 b 0 b 1 a 3 e 23 a 2 e 21 e 12 b 1 a 2 S 12 DUT 16-Term Error Model 1 S 11 S 22 S 21 a 1 b 2 e 00, e 33 Directivity e 11, e 22 Port Match e 10, e 01, e 32, e 23 Tracking e 30, e 03 Primary Leakage All others are lower level leakage paths e 33 e 31 e 02 e 22 e 32 b 3 b 3 b 2 One of the 16 error terms can be normalized to yield 15 error terms 1. JV Butler, DK Rytting, MF Iskander, RD Pollard and MV Bosche, 16-Term Error Model and Calibration Procedure for On-Wafer Network Analysis Measurements, IEEE Trans. on Microwave Theory & Tech. VOL. 39, NO. 12. 1991, pp. 2211 2217.

Summary of Calibration Methods for on-wafer probing Based on the 8-term error model; seven or more known conditions must be measured for calibration. Z 0 must be known. SOLT (Standard Cal for VNAs) LRM Known Thru (T) [4 Terms] Known Thru (T) or Line (L) [4 Terms] 3 known Reflects (R) (Open, Short & Load) on Port 1 [3 Terms] Unknown but equal (symmetry) Reflect (R) on Port-1 & Port-2 [1 Term] 3 known Reflects (R) (Open, Short & Load) on Port 2 [3 Terms] Known Match (Load) (M) on Port-1 & Port-2 [2 Terms] LRRM & elrrm * Known Thru (T) or Line (L) [4 Terms] 2 Unknown but equal (symmetry) Reflects (RR open & short) on Port-1 & Port-2 [2 Terms] Known Match (Load) (M) on Port-1 [1 Term] TRL & mtrl Known Thru (T) [4 Terms] Unknown but equal (symmetry) Reflect (R) on Port-1 & Port-2 [1 Term] Known (S 11 and S 22 ) Line or multiple Lines (L) [2 Terms] * - usually through Cascade Microtech s WinCAL

On-Wafer Probing - Calibration In measuring a transistor calibrating the VNA removes the systematic errors associated with cables and the test setup and supposedly the leakage.

On-Wafer Probes Probes GGB Picoprobe, Cascade Microtech plus loads of others, down to 50µm pin/contact spacing and to greater than 1THz Can be GSG but also almost any other combination, eg. balanced GSG ground signal ground, 3 pins Coax connector eg, 1mm. RF plus DC feed via VNA and Bias-T

Choice of reference plane for RFOW Probing? Probe tip vs. On-wafer at the DUT 100µm Probe pitch On Wafer calibration Probe tip calibration

Probe Tip Cal Using ISS Impedance Standard Substrate Example here is often used for LRRM - the industry standard. Owned by Cascade Microtech and is often used in conjunction with their software WinCAL. Menu driven. Uses a standard SOLT set of standards for probe tip calibration.

Calibration Checklist for Probe Tip Cal Using ISS Impedance Standard Substrate Switch phone off. It s really important not to do anything else when doing RFOW cal and measurement. Probes are expensive and not easily repaired. And an wafer may be a lot more! Visually check and clean probes Mount probes on prober if necessary. Planarise, 3 even scratches GSG (contact substrate for planarity) or on wafer area. Planarity 3 even scratches Then set the probe skate.

Probe tip Cal on ISS: LRRM Line, 2x Reflect, Match Set the skate using the alignment marks from X to Y. This distance depends upon the probes used. Open standard is taken as the two probes lifted off the ISS tile > 250um and spaced sufficiently far apart >1mm Thru or Line Standard, 1ps [L] Short Standard 1 Reflect [R] Match Standard [M] 1 Reflect [R]

So what s it got to do with Zen & the Art? It s about QUALITY in this case Whether it s maintaining a motorbike or making a measurement right attitude yields quality. In our case a good calibration. That gets good measurements and then good device models. Virtuous Circle for MMIC Design Good calibration Good working circuits On-wafer Probing Good device/ circuit measurements Good Modelling & design

However for Millimetre-wave DUTs there s more work to do. So if you want to measure a transistor/diode right up to the DUT there are 2 ways: 1. ISS Cal and then de-embed back to the device ǂ. The problem with this are the parasitics. The error associated with de-embedding far outweighs the device parasitics that you re trying to measure. Probe tip cal plane De-embed De-embed ǂ H Cho and, DE Burk, A three-step method for the de-embedding of high-frequency S-parameter measurements, IEEE Trans. on Electron Devices. Vol. 38, No. 6. 1991, pp. 1371 1375.

On-wafer Calibration Standards 2. Use on-wafer cal standards. LRRM or multiline TRL. Brings the cal plane up to the device and eliminates the need to de-embed the structures connecting to the device. On-wafer cal plane

On-wafer Calibration Standards LRRM is a popular choice since the standards are compact and take up little valuable wafer space. Multiline TRL is a better cal standard for millimeter-wave frequencies and there is free software available from NIST to do mtrl. However mtrl requires longer lengths of line, which is more wafer space! For more information see Prescription for THz Transistor Characterisation, Dylan Williams, NIST, Boulder, Colorado. Guidelines on Cal standard spacing between circuits should be >5x the substrate thickness. CPW circuits screen better than microstrip but bring with them a whole bunch of modal issues. Also spacing between standards depends upon the probe used check with the manufacturer. Angle of probe and use of absorber

On-wafer Cal Standards - Thru On a 50µm GaAs phemt process using ADS & simulated using Momentum. Pp10 WIN Semiconductor. Then check using LRRM cal on ISS.

On-wafer Cal Standards - Open 50µm GaAs phemt process pp10 WIN Semiconductor. Checked using LRRM cal on ISS tile.

On-wafer Cal Standards - Short 50µm GaAs phemt process pp10 WIN Semiconductor. Checked using LRRM cal on ISS tile. Pull in of higher frequency resonance

On-wafer Cal Standards - Load 50µm GaAs phemt process pp10 WIN Semiconductor. Checked using LRRM cal on ISS tile. Notice this is not a particularly good load above ~ 60GHz, via inductance is becoming a feature. There are tricks that can be employed to improve the appearance of a good load.

Finally the On-wafer Cal can be done and DUT can be measured Calibrate then check by re-measuring the standards. LRRM is self consistent so that the shorts do not have to sit at zero Ohms and can on occasion appear to give gain especially at frequencies above 80GHz! Note these small devices have huge gain at low frequencies so in measuring smallsignal we mustn t drive the device too hard. RF signal level for modelling transistors is about -40dBm (VNA -30dBm plus cable/probe losses) or around 2mV RMS or pk-pk ~6mV. Usually small signal 1 is V T /10. 1. ICCAP Manual, Franz Sischka, October 2010

Future of On-Wafer Cal LRRM and MTRL are the way forward. I can see a frequency partition calibration DC -80GHz LRRM and >80GHz mtrl. This requires an extra set of loads to be designed on wafer but saves the space of the lines needed for low frequency cal. Example of Multiline TRL Kit: M Ferndahl, K Andersson & C Fager, Mulit-line TRL Calibration Compared to a General De-embedding Method, 73 rd ARFTG, 2009

Good calibration good models complex circuit design For TWA accurate models allow for designs to be optimised and kept stable. 10 stages of cascode.

Conclusions There s a lot of work to do mm-wave devices are here and need exploiting! Devices exist capable of working >400GHz. The applications will follow and devices and pull outs need measuring and characterising. Co-workers: Dr Chris Duff, Miss Priya Shinghal, Mr Geoffrey Barigye (UoM) And Finally,

Conclusions The zen master and the university professor vs. Zen and the student In the beginner s mind there are many possibilities, but in the expert s there are few. Shunryu Suzuki, Zen Mind, Beginner s Mind