A/D and D/A convertor 0(4) 24 ma DC, 6 bits ZAT-DV The board contains independent isolated input A/D convertors for measurement of DC current signals 0(4) ma from technological convertors and sensors and four independent isolated output D/A convertors 0 24 ma. The unit of the set ZAT-DV is used in system ZAT-00 MP in connection with modules ZAT of series MD, VD, VH, VP and VZ. System interface is formed by VME bus (J) with VME interface A24 (A6):D6. The board is intended for system VME 6HE, connection of associated equipment is through connector on the front panel of the board, see Fig.. ERR RUN J4 FUNCTION DESCRIPTION The board processes input and output analog current signals. Input signal is converted into digital form with 24-bit resolution from which 6 bits ( bits are sign) are used for next processing. Output analog signal is unipolar with resolution 6 bits. Digital data are transferred to control board through VME bus. The board does not use interruption system of VME bus. After passage through input filter, analog signal of each input is converted into digital data by separate sigma/delta convertor. After the conversion the signals are led through galvanic separation by means of optrons into internal bus and subsequently processed by micro-controller SAB0C66 with cycle frequency MHz. Micro-controller controls processing of analog signals, their digital filtering and storing of measured values together with time data of resolution ms into dual-port memory (memory for analog archive). Output analog signals are generated by 6-bit sigma/delta convertor D/A. Access into archive and communication with the board concerning the side of VME bus is controlled by VLSI circuit ALTERA. could be calibrated by means of calibration program in specialized workplace. Resulting calibration constants are saved in Flash board memory. J Fig. : Front board panel ZAT-00 MP _KL-00-REV0-4--AN-VIT.
MAP OF MEMORY Detailed description of the map of memory is included in document map of memory. BIR Board Identification Register board identification no. AA2H NAR Address Register BASE ADR of the board in access A2 (i.e. address A2-A). OIW Output Input Width length of input and output field 00E0h DRW Length of diagnosing and DPRAM field - 00h SAW Length of control and status register 0000h CR Control Register SR Status Register Base address of A6 access is set through switch SW by bocks of 64 byte. Block addres of A24 access is set by SW driver at board initialization through write into NAR register. DESCRIPTION OF INDIVIDUAL CIRCUITS Heart of connection is created by 6-bit microcontroller SAB0C66 with cycle frequency MHz, which controls all the functions of the board. On the board there is implemented a possibility of interactive software debugging by means of instrument SODOB 66. After feeding connection or activating of signal RESET of VME bus, supervisory circuit MAX696 performs RESET of micro-controller SAB0C66. After reset micro-controller performs test of entire hardware of the board and test of firmware integrity. If input conditions are fulfilled, red LED (ERR) on the front board panel lights off. Yellow LED (RUN) lights after proper initialization of the board and after its accepting by program of control board (CPU). During proper board operation it lights permanently. Into sensing resistors of analog inputs of the board there is led current signal 0 ma (0 ma). Each measuring channel is equipped with analog low filter with protection circuit against pulse overvoltage. The protection limits input of frequencies higher than 2 khz into convertor. Analog current signal is sensed in a precise board resistor 00 Ω by separate sigma/delta A/D convertor with digital filter with network frequency 0 or 60 Hz. Itself convertor has resolution 24 bits, from which FW of microcontroller selects valid part for transfer into system and storing in archive. Self-calibration of A/D convertor is done in each conversion cycle. Conversion time of convertor is 6 ms, where 40 ms are reserved for sampling of input signal. This feature enables to reach high suppression of interference in network frequencies. Measurement in all the input channels is synchronous and cyclic one. Single channels could be set by means of SW to amplification (range I) or 4 (range II). Overreaching of input voltage limits and fatal error of input module are indicated in diagnostics reports for each channel. Adjusting of output values of D/A convertors is asynchronous by activity of A/D convertors (change of analog value starts immediately after setting of new digital value with stabilizing time see Technical parameters). Output circuits are immune against shortcircuit of output. Local archive is created by buffer in which 4 last measurements with time mark are started. Concerning design point of view, analog circuits of each input and output forms separate enclosed module CA00 for A/D conversion, for D/A conversion, on which there are placed protection circuits, itself A/D (D/A) convertor, reference source circuits for galvanic isolation and DC/DC convertor for circuit feeding. EARS 4 EARS 4 2 2 6 6 4 4 Ain Ain 6 Ain 6 9 Ain 9 Ain6 Ain6 Ain 2 Ain 2 9 Ain4 9 22 Ain4 22 0 Ain 0 2 Ain 2 Ain2 24 Ain2 24 2 Ain 2 Ain CONNECTOR J CONNECTOR J4 EARS EARS Aout4 Aout4 Aout Aout Aout2 Aout2 Aout Aout ZAT-00 MP 2 _KL-00-REV0-4-2-AN-VIT.
Input of each module is connected through capacitance 0 nf to EARS bus. This bus is connected through capacitance 0,2 µf to board chassis (panel). For test purposes, EARS bus is led in connectors J and J4. These pins are not connected in a standard ZAT cabling. TECHNICAL PARAMETERS: Table (the values are valid at ambient of temperature ±2 C, unless is fixed otherwise) Parameter Conditions Min. Type Max. Units Feeding voltage (VME) Consumption V 2 V 2 V 2 2 660 000 40 40 Board power 4 W Dielectrical strength Input / system Dielectrical strength Input / input Insulation resistance against board panel Input range I Input range II Range overrun Range overrun Input accuracy after calibration Input accuracy without calibration V ma min. 000 V DC min. V DC SW parametrized MΩ 0 24 0 at measurement range 0, % without failure of input circuits ma ±0 ma for one year 0,0 0,0 % 0,06 0, % Integral non-linearity of input 0 ma, 0 ma 0,00 % Additional input errors (data error caused by change of) ambient temperature feeding voltage ±2 V 0,00 0,002 0,00 Input resistance 6 Ω % per K % per V Suppression 0 Hz 00 0 db Conversion time of A/D 6 ms Output range 0 24 ma Output voltage 22 2 V Resistance of output loop 0 00 Ω Overrun of range into negative input currents (max. 0 % of range, e.g. 2 ma at range 0 ma) are used especially for reversing of input polarity indication and in this case high linearity is not guaranteed. ZAT-00 MP _KL-00-REV0-4--AN-VIT.
Output accuracy 0,2 % Integral non-linearity of output 0,002 0,02 % Additional output errors (data error caused by change of) ambient temperature feeding voltage ±2 V 0,002 0,00 0,00 % per K % per V Conversion time of D/A, ms Stabilization time of D/A output to 0, % 2, ms Operational temperature range 60 C Weight 0, kg Dimension 6HE, 4TE Table 2 Table of input values of Input value Output value Range overload 0.. ma 0.. ma > I HLI =, * I RNG FFF /HEX/,000 ma 6,0 ma I MAX =,2 * I RNG AE /HEX/ 0 24,000 ma 6,000 ma I RNG 6666 /HEX/ 0,000 ma,000 ma 0 0000 /HEX/ 0 0,000 ma 0,000 ma LSB FFFF /HEX/ 0 ~ 0,0006mA ~ 0,0009mA I MIN = 0, * I RNG FC /HEX/ 0 2,000 ma 0,00 ma < I LLI = 0,6 * I RNG F000 /HEX/, ma 0, ma Table accuracy is guaranteed in range of values 0. I RNG (see Technical parameters).. Linearity of input is guaranteed in range of values I MIN. I MAX (see Technical parameters). The values I HLI and I LLI are limit ones, when range overload of convertor is not yet reported. Table Table of output values of Input value Output current 0000 /HEX/ 0,000 ma 000 /HEX/ ~ 0,00066 ma FFFF /HEX/ 24,000 ma ZAT-00 MP 4 _KL-00-REV0-4-4-AN-VIT.
BLOCK DIAGRAM OF CONNECTION FOR BOARD V ±2 V VME BUS J U ZÁL PROG. PLD VME PLD ALTERA CONTROL SRAM PROG. CPU BSL RESET and WD CIRCUITS CPU SAB 0C66 DATA ADR FLASH XTAL MHz - BUS BUS 2 4 OPTOISOLATORS INSULATING BARRIER INPUT CA00 INPUT 2 INPUT INPUT 4 x INPUT INPUT 6 INPUT INPUT CA00 2 INPUT 24 0 2 9 22 2 6 9 INPUT 2 2 4 6 4 24 2 22 2 9 6 4 24 2 22 2 9 6 4 2 0 9 4 2 6 2 0 9 4 2 6 J CANNON M J4 CANNON M ZAT-00 MP _KL-00-REV0-4--AN-VIT.