HT32 Series EBI /N: AN0470E Overview The parallel bus interface used for the HT32 microcontroller family, named EBI or the External Bus Interface, allows access to external asynchronous parallel bus devices such as SRAM, Flash Memory, LC modules, etc. It can send these external signals to the internal address bus in the Cortex -M core using corresponding memory mapping. The HT32 Series EBI supports both data and address line multiplexing, thus effectively reducing the pin count required for external device connection. The bus read/write timing can be adjusted according to the external device timing requirements. Bus Control Signal The following table shows all the control signals, address and data line signals of the HT32 series external bus interface. It should be noted that some signals are only supported in the larger package types. For the smaller package types it may only support a reduced number of signals. Signal Input/output escription A[xx:0] Output Address bus A[xx:0] Input/output Address/data bus Output Chip select Output Output enable Output Write enable ALE Output Address latch enable BL[1:0] Output Bit group channel ARY Input Asynchronous ready Table 1. EBI Bus Control Signals Note that the BL[1:0] bit field is only used for some 16-bit data width SRAMs and the ARY bit is only applied for some NOR Flash memory types. EBI Operating Mode The EBI supports both multiplexed and non-multiplexed addressing modes. The nonmultiplexed address mode has a higher and faster work efficiency but also requires larger pin counts. The multiplexed addressing mode is slower and requires an additional address latch but has lower pin counts. AN0470E 1 / 10 November 14, 2017
Non-multiplexed Mode 8A8: This mode supports 8-bit address and 8-bit data. The signal high byte in the EBI_A signal line is address while the lower byte is data. 16: In the non-multiplexed mode, the 16-bit signal in the EBI_A signal line is data. The address is contained in the EBI_A signal line. Multiplexed Mode 8A24ALE: This mode allows a 24-bit address and 8-bits of data to be multiplexed in the EBI_ signal line to reduce pin count. These signals will be encoded by the EBI_ALE signal. The higher byte in the EBI_A signal line is bits EBI_A[15:8] and is the 8-bit address which has an order from the highest bit to the lowest. The lower byte in the EBI_A signal line, bits EBI_A[7:0] contain the middle 8-bit address and the 8-bit data. 16A16ALE: This mode supports the 16-bit address and 16-bits of data. It also requires an external latch and an additional signal EBI_ALE. The 16-bit address and 16-bit data are multiplexed on the EBI_A pin. Timing Configuration The EBI contains several timing setting parameters for use with different accessing protocols. RSETUP: Setup the number of cycles for the address setting before the bit is asserted. RSTRB: Setup the number of cycles that the bit is held active for. RHOL: Setup the number of cycles that the is held active for after the bit is de-asserted. SETUP: Setup the number of cycles for the address setting before the bit is asserted. STRB: Setup the number of cycles that the bit is held active for. HOL: Setup the number of cycles that the is held active for after the bit is de-asserted. RSETUP RSTRB RHOL EBI_ EBI_ Figure 1. EBI Non-multiplexed Read Timing AN0470E 2 / 10 November 14, 2017
SETUP STRB HOL EBI_ EBI_ Figure 2. EBI Non-multiplexed Write Timing Bits ARSETUP and ARHOL are used to control the external address latch timing in the multiplexed mode. Refer to the reference manual for more detailed information on the timing configuration. ARSETUP: Setup the number of cycles that the address is driven onto the A bus before the ALE bit is asserted. ARHOL: Setup the number of cycles the address is held on the A bus after the ALE bit is asserted. ARSETUP RSETUP RSTRB RHOL EBI_ALE EBI_ EBI_ Figure 3. EBI Multiplexed Read Timing ARSETUP ARHOL SETUP STRB HOL EBI_ALE EBI_ EBI_ Figure 4. EBI Multiplexed Write Timing Other Features Full page read operation Write buffer AHB processing width switch Read/write period extension Polarity configuration AN0470E 3 / 10 November 14, 2017
Asynchronous NOR Flash Interface EBI Configuration The EBI provides the following functions to control NOR Flash memory: Select Bank for NOR Flash memory mapping Select EBI mode: 8A8, 16A16ALE, 8A24ALE, 16 Enable or disable asynchronous ready or asynchronous ready overflow Configure control signal polarity Setup timing parameters Setup full page read function Asynchronous NOR Flash memory contains different AC specifications; therefore the timing parameter values for specific memory should be determined first. This document takes the MX29GL256F Memory as a reference. The read/write access timing parameters of the MX29GL256F Memory are listed in the Table 2. Symbol escription Value Unit Tcs Chip enable setting time 0 ns Twp # pulse width 35 ns Twph # pulse width high level time 30 ns Twc Write period time 100 ns Taa Toe Valid data output after address # valid data output after is de-asserted 100 ns 25 ns Trc Read period time 100 ns Table 2. MX29GL256F NOR Flash Memory Timing According to the memory timing listed in the Table 2, the EBI initialisation can be implemented by the following procedures. Here EBI Bank 0 in the 16 mode under a CPU operating frequency of 72MHz is taken as an example: AN0470E 4 / 10 November 14, 2017
Hardware Connection The following figures show the typical connections between the MX29GL256F NOR Flash Memory and four EBI modes. The unused EBI pins can be used as general I/O pins. 8A8 A[8] A[15:9] A[7:0] A[24:8] NOR [15] A[6:0] [7:0] A[23:7] BYTE# ARY Vss # # CE# RY/BY# Figure 5. Connection between NOR Flash and EBI in the 8A8 Mode 16 NOR [15:0] Vcc BYTE# A[23:0] ARY A[23:0] # # CE# RY/BY# Figure 6. Connection between NOR Flash and EBI in the 16 Mode 16A16ALE NOR A[23:16] A[23:16] Vcc A[15:0] ALE ARY BYTE# [15:0] # # CE# RY/BY# Figure 7. Connection between NOR Flash and EBI in the 16A16ALE Mode AN0470E 5 / 10 November 14, 2017
8A24ALE A[7:0] ALE A[15:9]/A[8] NOR A[14:7] [7:0] A[6:0]/[15] A[22:16]/A[15] Vss BYTE# A[24] A[23] CE Figure 8. Connection between NOR Flash and EBI in the 8A24ALEMode Asynchronous 16-bit SRAM Interface EBI Configuration The EBI provides the following functions to control SRAM: Select Bank for SRAM memory mapping Select EBI mode: 8A8, 16A16ALE, 8A24ALE, 16 Enable or disable bit group channel function Configure control signal polarity Setup timing parameters Asynchronous SRAM memory contains different AC specifications; therefore the timing parameter values for specific memory should be determined first. This document takes the IS61WV102416BLL Memory as a reference. The read/write access timing parameters of the IS61WV102416BLL Memory are listed in the Table 3. Symbol escription Value Unit Tsce Taw CE to write complete time Address setup and write complete time 8 ns 8 ns Tpwe pulse width 8 ns Twc Write period time 10 ns Taa Address accessing time 10 ns Tdoe accessing time 6.5 ns Trc Read period time 10 ns Table 3. IS61WV102416BLL SRAM Memory Timing AN0470E 6 / 10 November 14, 2017
According to the memory timing listed in the Table 3, the EBI initialisation can be implemented by the following procedures. Here EBI Bank 2 in the 16 mode under a CPU operating frequency of 72MHz is taken as an example: Considering the drive capability of the HT32 Series I/O, it may be necessary to increase some of the EBI timing parameters appropriately when the CPU is operating at 72 MHz. Hardware connection The following figures show the typical connections between the IS61WV102416BLL SRAM Memory and four EBI modes. The unused EBI pins can be used as general I/O pins. 8A8 A[15:8] A[7:0] SRAM A[7:0] [7:0] A[19:8] A[19:8] BL[1] BL[0] UB LB CE Figure 9. Connection between SRAM and EBI in the 8A8 Mode 16 A[19:0] BL[1] BL[0] SRAM [15:0] A[19:0] UB LB CE Figure 10. Connection between SRAM and EBI in the 16 Mode AN0470E 7 / 10 November 14, 2017
16A16ALE A[19:16] SRAM A[19:16] A[15:0] ALE BL[1] BL[0] [15:0] UB LB CE Figure 11. Connection between SRAM and EBI in the 16A16AL Mode SRAM A[15:8] 8A24ALE A[7:0] ALE A[15:8] [7:0] A[7:0] A[19:16] BL[1] UB BL[0] LB CE Figure 12. Connection between SRAM and EBI in the 8A24ALE Mode AN0470E 8 / 10 November 14, 2017
Intel 8080-like LC Module Interface EBI Configuration This is similar to the above description for an asynchronous NOR Flash or SRAM memory, but the EBI contains different accessing protocols. The related user LC protocol type must first be well-defined when operating with LC modules. The protocol type is determined by different control signals and the LC specific actions required for read/write processing. Hardware Connection The following figures show the typical connections between an Intel 8080 LC and four EBI modes. The unused EBI pins can be used as general I/O pins. 16 16A16ALE A[0] LC [15:0] WR R RS Figure 13. Connection between LC 8080-like Interface and EBI in the 16/16A16ALE Mode 8A8 8A24ALE A[7:0] A[0] LC [7:0] WR R RS Figure14. Connection between LC 8080-like Interface and EBI in the 8A8/8A24ALE Mode Revision and Modification Information ate Author Issue 2017.10.31 吳旭宏 Initial version AN0470E 9 / 10 November 14, 2017
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