UNIVERSITI MALAYSIA PERLIS. PLT106 Digital Electronics [Elektronik Digital]

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UNIVERSITI MALAYSIA PERLIS Peperiksaan Akhir Semester Kedua Sidang Akademik 2016/2017 Jun 2017 PLT106 Digital Electronics [Elektronik Digital] Masa : 3 jam Please make sure that this question paper has ELEVENT (11) printed pages including this front page before you start the examination. [Sila pastikan kertas soalan ini mengandungi SEBELAS (11) muka surat yang bercetak termasuk muka hadapan sebelum anda memulakan peperiksaan ini.] This question paper has SIX (6) questions. Answer ALL FOUR (4) questions in PART A and ONE (1) question from PART B. Each question contributes 20 marks. [Kertas soalan ini mengandungi ENAM (6) soalan. Jawab KESEMUA EMPAT (4) soalan dalam BAHAGIAN A dan SATU (1) soalan dalam BAHAGIAN B. Markah bagi tiap-tiap soalan adalah 20 markah.]

-2- PART A [BAHAGIAN A] Question 1 [Soalan 1] a) Electronic circuit can be divided into two broad categories which are digital and analog. Explain analog system and digital system by using your own words. [Litar elektronik boleh dibahagikan kepada dua cabang kategori iaitu digit dan analog. Terangkan sistem analog dan sistem digit dengan menggunakan ayat-ayat anda sendiri.] (4 Marks/ Markah) b) Convert the following numbers according to the base given. Show all steps clearly. [Tukarkan nombor-nombor berikut berdasarkan asas yang diberikan. Tunjukkan semua langkah dengan jelas.] (iii) (iv) 8410 to binary number. [84 10 kepada nombor perduaan.] 17E16 to decimal number. [17E 16 kepada nombor perpuluhan.] 7078 to hexadecimal. [707 8 kepada nombor perenambelasan.] 1010011.110112 to octal number. [1010011.11011 2 kepada perlapanan.] c) Add 11410 with 710 by converting to binary. Show your calculation clearly using basic binary addition. [Tambah 114 10 dengan 7 10 dengan menukarkan kepada perduaan. Tunjukkan kiraan anda dalam asas tambahan perduaan.] (3 Marks/ Markah) d) Given X = (EF)16 and Y = (AB)16, compute X + Y and X - Y using 8-bit two's complement binary arithmetic. [Diberi X = (EF) 16 dan Y = (AB) 16, kirakan X + Y dan X - Y dengan menggunakan aritmetik perduaan pelengkap dua 8-bit.] (5 Marks/ Markah)

Question 2 [Soalan 2] -3- a) Given a combinational logic circuit for function F as in Figure 1: [Diberi satu litar gabungan logik untuk fungsi F seperti dalam Rajah 1:] A B C F Figure 1 [Rajah 1] (iii) (iv) Express the expression for function F in the logic circuit given in Figure 1. [Nyatakan persamaan bagi fungsi F dalam litar logik yang diberikan di dalam Rajah 1.] Simplify the expression in Question 2(a) using Boolean algebra and De Morgan s theorem. [Ringkaskan persamaan di Soalan 2(a) mengunakan algebra Boolean dan teorem De Morgan.] (5 Marks/ Markah) Build a truth table for the simplified expression in Question 2(a). [Binakan satu jadual kebenaran bagi persamaan yang telah diringkaskan di Soalan 2(a).] Sketch the combinational logic circuit for the simplified expression. [Lakarkan litar gabungan logik bagi persamaan yang telah diringkaskan.]...4/-

-4- b) A Boolean expression from a combinational circuit is given as: [Satu persamaan Boolean dari litar gabungan diberi seperti berikut:] F ABC AB( AC) (iii) Simplify the expression given by applying Boolean algebra and De Morgan s theorems. [Ringkaskan persamaan yang diberi dengan menggunakan algebra Boolean dan teorem De Morgan.] (4 Marks/ Markah) Build a truth table for the simplified expression. [Binakan satu jadual kebenaran bagi persamaan yang telah diringkaskan.] Sketch the combinational logic circuit for the simplified expression. [Lakarkan litar gabungan logik bagi persamaan yang telah diringkaskan.] (3 Marks/ Markah)

Question 3 [Soalan 3] -5- a) Given a timing diagram for output logic function F(W,X,Y,Z) as in Figure 2: [Diberi satu gambarajah pemasaan untuk keluaran fungsi logik F( W,X,Y,Z) seperti dalam Rajah 2:] Z Y X W F Figure 2 [Rajah 2] Analyse the timing diagram for output logic function F(W,X,Y,Z) by producing a truth table and simplify using Karnaugh map (K-map) to implement the minimum Sum of Product (SOP) expression. [Analisa gambarajah pemasaan untuk keluaran fungsi logik F( W,X,Y,Z) dengan menerbitkan satu jadual kebenaran dan ringkaskan dengan menggunakan peta Karnaugh (peta-k) dengan melaksanakan ungkapan hasil tambah hasil darab (SOP) minimum.] (7 Marks/ Markah) Draw the logic diagram based on your answer obtained in Question 3(a). [Lukiskan gambarajah logik berdasarkan jawapan yang anda perolehi di Soalan 3(a).] (3 Marks/ Markah) b) Given a standard Sum of Product (SOP) expression for three variables as follows: [Diberi satu persamaan piawai hasil darab hasil tambah (SOP) bagi tiga pembolehubah seperti berikut:] F ABC ABC ABC ABC ABC ABC ABC...6/-

-6- Sketch the combinational logic circuit for the expression given. [Lakarkan litar logik bergabungan bagi persamaan yang diberi.] (4 Marks/ Markah) Produce a truth table from logic function F. [Hasilkan jadual kebenaran dari fungsi logik F.] (iii) Determine a minimization of Sum of Product (SOP) expression by using the Karnaugh map (K-map). [Tentukan persamaan hasil tambah hasil darab (SOP) minimum dengan menggunakan peta Karnaugh (peta-k).] (4 Marks/ Markah)

Question 4 [Soalan 4] -7- a) A Multiplexer (MUX) is a device that allows digital information from several sources to be routed onto a single line. Give THREE (3) advantages of multiplexer. [Satu Pemultipleks (MUX) adalah satu peranti yang membenarkan maklumat digital dari beberapa sumber-sumber untuk dilalukan ke atas satu talian. Berikan TIGA (3) kelebihan-kelebihan pemultipleks.] (3 Marks / Markah) b) A 8:1 multiplexer is given in Figure 4(a): [Satu pemultipleks 8:1 diberikan dalam Rajah 4(a):] 1 0 I0 I1 I2 I3 I4 Y I5 X I6 I7 S2 S1 S0 Figure 4(a) [Rajah 4(a)] Produce a truth table from Figure 4(a). [Hasilkan jadual kebenaran daripada Rajah 4(a).] Find the expression of the function Y in a standard Sum of Product (SOP). [Dapatkan persamaan bagi fungsi Y dalam satu bentuk piawai hasil tambah hasil darab (SOP).]...8/-

(iii) (iv) -8- Simplify the expression in Question 4(b) by using Karnaugh map. [Permudahkan persamaan dalam Soalan 4(b) dengan menggunakan peta Karnaugh.] (3 Marks/ Markah) Draw a complete circuit to implement the expression in Question 4(b)(iii). [Lukiskan litar lengkap untuk melaksanakan persamaan dalam Soalan 4(b)(iii).] c) A combination of flip-flops are given in Figure 4(b): [Satu kombinasi beberapa flip-flop diberikan dalam Rajah 4(b):] A X Y Z CLK Figure 4(b) [Rajah 4(b)] Give the complete name for each flip-flop in Figure 4(b). [Berikan nama lengkap bagi setiap flip-flop dalam Rajah 4(b).] Complete the following timing diagram in Appendix 1 by sketching the waveforms for the output X, Y and Z. Assume all of the output values are initially at 0 and both flip-flops operate in positive edge-triggered condition. [Lengkapkan gambarajah pemasaan pada Lampiran 1 dengan melakarkan gelombanggelombang keluaran X, Y dan Z. Anggapkan kesemua output bermula pada nilai 0 dan kedua-dua flip-flop beroperasi dalam keadaan terpicu-pinggir positif.] (6 Marks/ Markah)

-9- PART B [BAHAGIAN B] Question 5 [Soalan 5] Design a synchronous 4-bit binary counter with even number sequence as shown in Figure 5 below by using J-K flip-flops. Transition table for the J-K flip flop as shown in Table 5. [Rekabentuk pengira segerak perdua 4-bit dengan urutan nombor genap seperti ditunjukkan dalam Rajah 5 di bawah menggunakan beberapa flip-flop J-K. Jadual transisi flip flop J-K seperti yang ditunjukkan dalam Jadual 5.] 0 8 2 6 4 Figure 5 [Rajah 5] Table 5 [Jadual 5] Output Transition Flip-flop input QN QN+1 J K 0 0 0 X 0 1 1 X 1 0 X 1 1 1 X 0 (20 Marks / Markah)

Question 6 [Soalan 6] -10- Design a synchronous 4-bit binary counter with odd number sequence as shown in Figure 6 below by using J-K flip-flops. Transition table for the J-K flip flop as shown in Table 6. [Rekabentuk pengira segerak perdua 4-bit dengan urutan nombor ganjil seperti ditunjukkan dalam Rajah 6 dibawah menggunakan beberapa flip-flop J-K. Jadual transisi flip flop J-K seperti yang ditunjukkan dalam Jadual 6.] 1 9 3 7 5 Figure 6 [Rajah 6] Table 6 [Jadual 6] Output Transition Flip-flop input QN QN+1 J K 0 0 0 X 0 1 1 X 1 0 X 1 1 1 X 0 (20 Marks / Markah) -ooooooo-

Angka Giliran: No.Meja: -11- Appendix 1 [Lampiran 1] Question 4(c) [Soalan 4(c)] CLK A X Y Z