STEVAL-IPE00V Features Demonstration programmer board based on the STPM0 Full compatible with the STPM0 energy meter and with the appropriate manager software Integrated system designed to provide a complete, ready-to-use energy meter High-end solution for power metering based on the STR0 Microcontroller with embedded RTC External memory interface (EMI) ready to drive Mbyte of on-board SRAM. On-board optical insulated serial line On-board charge pump Access to the STPM0 device registers, using a dedicated SPI bus interface Applications Demonstration purposes: connecting the demonstration board to an AC power source and changing all the settings parameters through the GUI interface and the hardware programmer/ reader board To evaluate and develop a custom application Description The STEVAL-IPE00V demonstration board works in conjunction with the STPM0 energy meter ASSP device and with the STPM0 manager software. It is an integrated system designed to provide the user with a complete, ready-to-use energy meter application. This board is a high-end solution for power metering based on the STR0 microcontroller with an embedded RTC and an external memory interface (EMI) ready to drive Mbyte of on-board SRAM. The demonstration board also integrates an on-board optical insulated serial line allowing isolation of the board ground reference in order to avoid propagation of over-voltage on the PC side. STEVAL-IPE00V Data Brief Moreover, the on-board charge pump allows burning the STPM0 energy meter ASSP device registers. Access to the STPM0 device registers is ensured using a dedicated SPI bus interface. The STPM0 programmer kit demonstrates how effectively the STPM0 can be used in real-world energy meter applications and it helps the user to develop his own application. November 008 Rev / For further information contact your local STMicroelectronics sales office. www.st.com
Demonstration board schematics STEVAL-IPE00V Demonstration board schematics. Microcontroller and main parts schematic Figure. Microcontroller and main parts schematic CK RTCXT TCXTI RTCXT TCXTO Rx_0 RX_0 TX_0 D VOUT D D VOUT D D A D D A8 A D D A A8 D D0 A A D0 D A A D D8 A A D8 D A A D D A A D D A A D D A0 A D D A A0 D D A8 A D D A A8 D D0 A A D0 A A A A A A nwe0 A A WE0 nwe A A WE nrd A not OE CS. not CS_SRAM JTDI JTDO JTCK JTDI JTMS not JTRST JTDO not Reset JTCK DBGRQS JTMS not JTRst not Reset DBGRQS U JTDI JTCK I/O I/O JTMS JTDO I/O not JTRST I/O I/O MISO U not Reset DBGRQS MOSI I/O I/O SCLK I/O I/O I/O +V8 not Reset +V8 P0. P0. P0.0 P0. P0. P0.0 P0. WAKEUP WAKEUP ORANGE +V8 CS. Cn A0 A A A A A A A A8 A A0 A A A A A A A A8 A A0 A A A D0 D D D D D D D D8 D D0 D D D D D nrd rn nwe0 rn nwe rn P. 8 8 8 CK CK P.8 8 0 P. 0 0 P.0/USBCLK 0 USBDN 0 USBDP 0 not Reset RSTIN CKOUT RTCXTI RTCXTI RTCXTO RTCXTO 0 BOOTEN BOOTEN JTDI JTDI 0 JTDO JTDO JTCK JTCK JTMS JTMS not JTRST JTRST P.0 P.0/T.OCMPB/AIN.0 P. P./T.ICAPA/AIN. P. P./T.OCMPA/AIN. P./T.ICAPB/AIN. 88 P./CANRX 88 8 P./CANTX 8 0 P./HCLK/IO.SCL 0 08 P./HCLK/IO.SCL 08 P./HTXD P0.0 P0. P0.0/S0.MISO/U.TX P0. P0./S0.MOSI/U.RX P0./S0.SCLK/I.SCL P0./S0.SSN/I.SDA P0. P0. P0./S.MISO P0. P0./S.MOSI 0 P0. P0./S.SCLK P0./S.SSN Rx_0 Tx_0 P0.8/U0.RX/U0.TX P0./U0.TX/BOOT.0 P0.0 TX I/0 P0.0/U.RX/U.TX P0./U.TX/BOOT. P0./SCCLK SYSTEM_DEFAULT 0 P0./U.RX/T.OCMPA P0./U.TX/T.ICAPA 0 DBGRQS DBGROS TEST TEST 8 0 0 8 8 SYSTEM_DEFAULT P.0 P. P. POWER 8 0 8 0 0 0 8 0 08 0 8 08 0 BOOT BOOTEN TX I/0 BOOT_EN Tx_ x_0 SW SW J BOOT EMI_SRAM ESD ESDAV-W-SOT-L ESDAV-W-SOT-L R R R +V8 R 0 SW MOMENTARY POWER MANAGEMENT +V8 R 0 R 0 CHARGE PUMP 0 STPM0_SCS STPM0_SDA STPM0_SCL STPM0_SYN STR_SBG STR_SBS STR_OTP_EN ChargePump Enable UART0 TX TIMER GPIO PORT EMI DEBUG UART UART UART0 SPI SPI0 IC0 CAN ADC STS RTC SYSTEM USB GENERAL 8 00 0 0 8 0 0 8 80 8 8 8 8 8 P.0/CS.0 P./CS. P./CS. P./CS. A.0 A. A. A. A. A. A. A. A.8 A. A.0 A. A. A. A. A. A. A. A.8 A. P./A.0 P./A. P./A. P./A. D.0 D. D. D. D. D. D. D. D.8 D. D.0 D. D. D. D. D. RD WE.0 WE. P.8 P. P.0 P. P. P. P. P. P./T.ICAPA P./T.ICAPB P./T.OCMPB P./T.OCMPA SUPPLY U STR0FZT-TQFP 8 VSS VSS VSS VSS VSS VSS VSS VSS8 VSS VSSBKP AVSS P0./WAKEUP STBY V. V. 0 V. 8 V. 0 V. V. 8 V. AVDD V8. 8 V8. V8BKP CLK - RTC CK RTCXTI RTCXTO CLK R8 TP0 0uF C C 00n SW MOMENTARY OPTO ISOLATED UART UARTx JTAG C 00n RESET RESET R 0 R 0 SPI_BUFFER.V STR_SCS STR_MOSI STR_MISO STR_SCL STR_SYN STR_WRITE_EN STR_READ_EN SPI_BUFFER V STPM0_SCS STPM0_SDA STPM0_SCLK STPM0_SYN /
STEVAL-IPE00V Demonstration board schematics. Power management Figure. Power management schematic J CN DC-INV DC-INV C 0V 0n U C0 0V 0n D U VIN N00 VOUT LD088 - DPAK-A C 0V 0n C 0V 0n C uf C V 00n J Enable L FBEAD J Enable V8 +V8 +V8 +V8 C V 00n C V 00n R 0 R 0 R 0 TP TEST POINT TP TEST POINT D BLU D YELLOW VIN VOUT LD08 - DPAK-A LF0 B PSG BNX00 CB CG CG CG D GREEN /
Demonstration board schematics STEVAL-IPE00V. Reset and clock circuits Figure. Reset and clock circuits /
STEVAL-IPE00V Demonstration board schematics. Boot management and Jtag circuit Figure. Boot management and Jtag circuits /
Demonstration board schematics STEVAL-IPE00V Figure. Opto-isolated UART /
STEVAL-IPE00V Demonstration board schematics. External RAM memory Figure. External RAM memory /
Demonstration board schematics STEVAL-IPE00V. SPI signals buffering Figure. SPI signals buffering SPI SIGNALS BUFFER SPI BUFFER FROM STR TO STPM0 SPI BUFFER FROM STPM0 TO STR STR_SCL STPM0_SCLK STR_SYN STPM0_SYN rev_0_c8 CHARGE PUMP STR_MISO sclkv sclkv synv sy nv V read_env sdav misov U G A Y G A Y MHC U G A Y G A Y MHC VCC G A Y 0 G 0 A 8 Y VCC G A Y 0 G 0 A 8 Y V scsv scsv write_env mosiv sdav.v.v.v V V STR_SCS STPM0_SCS STR_MOSI STPM0_SDA.V R.k rev_0_c0 STR_WRITE_EN STR_READ_EN 8/
STEVAL-IPE00V Demonstration board schematics. Charge pump and SPI connector Figure 8. Charge pump and SPI connect SCS VOTP STR_SBG STR_SBG STPM0_SCS SCS VCC STR_SBS STPM0_SDA SCL SYN STR_SBG STR_OTP_EN R0 K SCL SYN VCC STPM0_SYN STR_SBG STPM0_SCL VCC 0 STPM0_SYN STR_OTP_EN STR_SBS STPM0_SCS STR_SBG STPM0_SCL STPM0_SDA J8 CON VCC STPM0_SYN STR_OTP_EN STR_SBS STPM0_SCS STR_SBG STPM0_SCL STPM0_SDA VOTP D BAS0-0/SOT D BAS0-0/SOT VCC C 0n C 0n C8 0n R8 0 R K Q BC80- R K C u Q BC80- U G A Y G A Y MHC J CON0 00nF C 8 0 VCC G A Y G 0 A Y 8 U G A Y G A Y MHC VCC G A Y G 0 A Y 8 00nF C0 C p U A Y A Y A Y MHC VCC A Y A Y 0 A Y 8 C 00nF R K + C 0uF /
Revision history STEVAL-IPE00V Revision history Table. Document revision history Date Revision Changes -Nov-008 Initial release. 0/
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