hapter 5 Seuential Systems Latches and Flip-flops Synchronous ounter synchronous ounter 7822 igital Logic esign @epartment of omputer Engineering U. Introduction Up to now everything has been combinational the output at any instant of time depends only on what inputs are at the time. Later on of this course: seuential systems systems that have memory. Thus, the output will depend not only on the present input but also on the past history what has happened earlier. 7822 igital Logic esign @epartment of omputer Engineering U. 2 lock Signals Two versions of a clock signal are as below. In the first, the clock signal is half of the time and half of the time. In the second, it is for a shorter part of the cycle. The period of the signal (T on the diagram) is the length of one cycle. The freuency is the inverse (/T). T 7822 igital Logic esign @epartment of omputer Engineering U. 3
Terminology State: what is stored in memory. State table: shows for each input combination and each state, what the output is and what the net state is what is to be stored in memory after the net clock. State diagram (or state graph): a graphical representation of the state table. (Finite) State Machine 7822 igital Logic esign @epartment of omputer Engineering U. 4 State Table and State iagram present state net state output * z input / / / / / / / / / State table State diagram 7822 igital Logic esign @epartment of omputer Engineering U. 5 The net state is a function of the present state and the input. The output also depends on the present state (and on the input). It may change on a clock transition, but it may change where the input changes, as well. In state diagram, there must be one path from each state for each possible input combination. 7822 igital Logic esign @epartment of omputer Engineering U. 6 2
Moore vs. Mealy Models Moore model circuit (state-based) the outputs depend on the present state of the system but not on the inputs. Mealy model circuit (input-based) the outputs depend on the inputs as well as the present state of the system. 7822 igital Logic esign @epartment of omputer Engineering U. 7 Moore: system with no input and three outputs, that represent a number from to 7, such that the outputs cycle through the seuence 3 2 4 5 7 and repeat on consecutive clock inputs. Mealy: system with two inputs, and 2, and three outputs, Z, Z 2 and Z 3, that represent a number from to 7, such that the output counts up if and down if and recycles if 2 and saturates if 2. Thus, the following output seuences might be seen: 7822 igital Logic esign @epartment of omputer Engineering U. 8 2 2 3 4 5 6 7 2 3 4 5 6 7.. 2 2 3 4 5 6 7 7 7 7 7 7.. 2 7 6 5 4 3 2 7 6 5 4 3 2.. 2 7 6 5 4 3 2.. 7822 igital Logic esign @epartment of omputer Engineering U. 9 3
esign Process of Seuential Systems Table 5. Page 338 State table Timing trace State table with binary states Truth table -map euations 7822 igital Logic esign @epartment of omputer Engineering U. esign Process of Seuential Systems * z State table Timing trace clk 2 3 4 5 6 7 8 9 2 z 7822 igital Logic esign @epartment of omputer Engineering U. esign Process of Seuential Systems State assignment 2 State table with binary states * 2 * z 7822 igital Logic esign @epartment of omputer Engineering U. 2 4
esign Process of Seuential Systems Truth table for system design 2 * 2 * z 2 2 2 2 * S + R State assignment 7822 igital Logic esign @epartment of omputer Engineering U. 3 Latches and Flip-flops latch is a binary storage device, composed of two or more gates, with feedback. The latch can store either a (Q and P ) or a (Q and P ) The P output is just labelled Q 7822 igital Logic esign @epartment of omputer Engineering U. 4 Latches (cont.) Eample: a latch constructed with 2 NORs. S R P Q The euations for this system: P S + Q and Q R + P Normal storage stage both inputs inactive (S R ). P Q and Q P 7822 igital Logic esign @epartment of omputer Engineering U. 5 5
Latches (cont.) ase : If S and R P (+ Q) Q ( + ) ase 2: If S and R Q (+ P) P ( + ) ase 3: Finally, the flip-flop is not operated with both S and R active (). P (+ Q) Q (+ P) S R P Q 7822 igital Logic esign @epartment of omputer Engineering U. 6 Latches (cont.) flip-flops (elay flip-flops) SR flip-flops (Set/Reset flip-flops) T flip-flops (Toggle flip-flops) flip-flops 7822 igital Logic esign @epartment of omputer Engineering U. 7 flip-flops * * * 7822 igital Logic esign @epartment of omputer Engineering U. 8 6
S SR flip-flops R * - - S * S + R Not allowed R * - SR SR R S S R R 7822 igital Logic esign @epartment of omputer Engineering U. 9 T flip-flops T * T * *T T 7822 igital Logic esign @epartment of omputer Engineering U. 2 flip-flops * * * + 7822 igital Logic esign @epartment of omputer Engineering U. 2 7
Latches (cont.) Edge-triggered rising/leading edge-triggered falling/trailing edge-triggered Level-triggered high level-triggered low level-triggered 7822 igital Logic esign @epartment of omputer Engineering U. 22 nalysis of Seuential Systems Figure 5.2 Page 342 ircuit Euations State table Timing trace Timing diagram Euations *,* State diagram 7822 igital Logic esign @epartment of omputer Engineering U. 23 Flip-flop esign Techniues 2 * 2 * z Main truth table From the truth table, it s clear that z 2 We need to create the appropriate flip-flop design table to obtain a truth table for the flip-flop inputs. * Input(s) flip-flops flip-flops SR flip-flops T flip-flops 7822 igital Logic esign @epartment of omputer Engineering U. 24 8
esign with Flip-flop * * From the main truth table 2 * 2 2 * 7822 igital Logic esign @epartment of omputer Engineering U. 25 esign with Flip-flop (cont.) 2 2 + 2 + 2 2 7822 igital Logic esign @epartment of omputer Engineering U. 26 Implementation using Flip-flops Fig 5.26 page 352 7822 igital Logic esign @epartment of omputer Engineering U. 27 9
7822 igital Logic esign @epartment of omputer Engineering U. 28 esign with Flip-flop * * * 2 * 2 2 2 From the main truth table 7822 igital Logic esign @epartment of omputer Engineering U. 29 esign with Flip-flop (cont.) 2 2 2 ; ; + 2 2 2 2 2 2 7822 igital Logic esign @epartment of omputer Engineering U. 3 esign with SR Flip-flop S - * R S R * * 2 * R S R 2 S 2 2 From the main truth table
esign with SR Flip-flop (cont.) 2 2 2 2 2 2 S 2 S2 2 ; ; R R2 + 2 7822 igital Logic esign @epartment of omputer Engineering U. 3 esign with T Flip-flop T * * T From the main truth table 2 * 2 * T T 2 7822 igital Logic esign @epartment of omputer Engineering U. 32 esign with T Flip-flop (cont.) 2 2 T + + 2 T2 2 + 2 2 7822 igital Logic esign @epartment of omputer Engineering U. 33
2 7822 igital Logic esign @epartment of omputer Engineering U. 34 * * + * * + ecause Notice that when nd when * + 7822 igital Logic esign @epartment of omputer Engineering U. 35 esign of Synchronous ounters esign a decimal or decade counter using flip-flops: * * * *,, 2, 3, 4, 5, 6, 7, 8, 9,,, 7822 igital Logic esign @epartment of omputer Engineering U. 36 esign of Synchronous ounters (cont.) * * * * * * * *
3 7822 igital Logic esign @epartment of omputer Engineering U. 37 esign of Synchronous ounters (cont.) * * ; From the main truth table of the * 7822 igital Logic esign @epartment of omputer Engineering U. 38 esign of Synchronous ounters (cont.) * * From the main truth table of the * 7822 igital Logic esign @epartment of omputer Engineering U. 39 esign of Synchronous ounters (cont.) * * ; From the main truth table of the *
4 7822 igital Logic esign @epartment of omputer Engineering U. 4 esign of Synchronous ounters (cont.) * * From the main truth table of the * 7822 igital Logic esign @epartment of omputer Engineering U. 4 2 * * 2 3 * 4 * 4 3 7822 igital Logic esign @epartment of omputer Engineering U. 42 esign of synchronous ounters Page 35. Figure 5.3(2-bit counter)&5.32(timing delay) dvantage: Simplicity of the hardware no combinational logic reuired isadvantage: Speed
erivation of State tables and State iagrams onsider the problem: system with one input and one output z such that z at a clock time iff is currently and was also at the previous two clock times. nother way of wording this same problem is Mealy system with one input and one output z such that z iff has been for three consecutive clock times. 7822 igital Logic esign @epartment of omputer Engineering U. 43 sample input/output trace is z First approach: save the previous 2 inputs. nowing them and the present input output. 2 * 2 * z ust discard the older input stored in memory and store the newer one plus the current input. 7822 igital Logic esign @epartment of omputer Engineering U. 44 Second approach: store in memory the number of consecutive s as follows: none, that is, the last input was one two or more / one / / / no s / two or more s / * z 7822 igital Logic esign @epartment of omputer Engineering U. 45 5
The second approach reuires only 3 states, whereas the first reuires 4. oth, however, use 2 flip-flops. onsider: the system produces a if the input has been for 25 consecutive clock times. Now the first approach reuires to store the last 24 inputs and a state table of 2 24 rows. The second approach reuires 25 states which can be coded with 5 flip-flops. 7822 igital Logic esign @epartment of omputer Engineering U. 46 6