Single-Event Upsets in the PANDA EMC Results from a neutron irradiation of the front-end digitiser board M. Preston, P.-E. Tegnér (Stockholm University) H. Calén, T. Johansson, K. Makònyi, P. Marciniewski (Uppsala University) M. Kavatsyuk, P. Schakel (University of Groningen) SFAIR Meeting, 27 th of October 2016, Göteborg
Single-Event Upsets in the PANDA EMC 2/14 The PANDA Electromagnetic Calorimeter Figure from EMC Technical Design Report, PANDA. First step of readout electronics: FPGA-based sampling-adcs.
The front-end digitiser board 2 Kintex-7 FPGAs 2 SFPs 8 ADCs, 64 channels 32 light sensors Single-Event Upsets in the PANDA EMC 3/14
Single-Event Upsets in the PANDA EMC 4/14 Front-end electronics in the Electromagnetic Calorimeter 600 front-end digitiser boards in the EMC 375 in Barrel 217 in Forward Endcap
Single-Event Upsets in the PANDA EMC 4/14 Front-end electronics in the Electromagnetic Calorimeter 600 front-end digitiser boards in the EMC 375 in Barrel 217 in Forward Endcap Figure courtesy of C. Schnier. Distributed over several crates placed around the detector perimeter (average 1.3 metres from the beam at the Forward Endcap). Exposure to a high flux of particles Radiation effects Of interest here: neutrons (but also other hadrons, photons, electrons... could cause problems)
Single-Event Upsets in the PANDA EMC 5/14 What does radiation do to electronics? Wide range of effects, but generally: Transient effects (device not permanently damaged) Permanent effects (device permanently damaged) A subset of transient effects is Single-Event Upsets (SEUs). Radiation-induced bit-flip (0 1) in memory cell.
What does radiation do to electronics? Incoming neutron not directly ionising n + A (e. g. 28 Si) ionising particle(s) Charge deposit change of state in cell. Figure from Introduction to Single-Event Upsets, Altera. Single-Event Upsets in the PANDA EMC 5/14
Single-Event Upsets in the PANDA EMC 6/14 Single Event Upsets in FPGAs Such a process affects an FPGA semiconductor device with several sensitive parts (Look-Up Tables, routing, etc.). Several types of memory: 1. Configuration Memory 2. Block Memory 3. Distributed Memory 4. Flip-Flops
Single-Event Upsets in the PANDA EMC 6/14 Single Event Upsets in FPGAs Such a process affects an FPGA semiconductor device with several sensitive parts (Look-Up Tables, routing, etc.). Several types of memory: 1. Configuration Memory 2. Block Memory 3. Distributed Memory 4. Flip-Flops # of bits (1) contains Function of design (2-4) contain State of design We looked only at neutron-induced errors in the Configuration Memory.
Single-Event Upsets in the PANDA EMC 7/14 Neutron irradiation The board was irradiated in June 2016 at the The Svedberg Laboratory (TSL) in Uppsala.
Single-Event Upsets in the PANDA EMC 7/14 Neutron irradiation The board was irradiated in June 2016 at the The Svedberg Laboratory (TSL) in Uppsala. Board placed in the Standard User Position (SUP), beam perpendicular to the board. One FPGA read out. Beam diameter: 130 mm Φ Figure from Prokofiev, A. V. et al. (2009) 2009 IEEE Radiation Effects Data Workshop. 166-173. Readout
Single-Event Upsets in the PANDA EMC 7/14 Neutron irradiation The board was irradiated in June 2016 at the The Svedberg Laboratory (TSL) in Uppsala. Board placed in the Standard User Position (SUP), beam perpendicular to the board. One FPGA read out. Neutron flux between 5 10 5 and 1 10 6 s 1 cm 2 (>10 MeV). 1.0 10-1 TSL PANDA, p pbar = 15 GeV/c Normalised Neutron flux 1.0 10-2 1.0 10-3 1.0 10-4 1.0 10-5 10 100 1000 10000 Neutron energy [MeV]
Error detection and correction Xilinx provides the Soft Error Mitigation (SEM) Controller, an IP core which may be implemented in the firmware. Correction capability depends on the structure of the error and SEM mode. Single-Event Upsets in the PANDA EMC 8/14
Single-Event Upsets in the PANDA EMC 8/14 Error detection and correction Xilinx provides the Soft Error Mitigation (SEM) Controller, an IP core which may be implemented in the firmware. Correction capability depends on the structure of the error and SEM mode. Memory divided into frames (1 frame = 101 32-bit words) SEM protected each frame with an Error Correction Code (ECC).
Single-Event Upsets in the PANDA EMC 8/14 Error detection and correction Xilinx provides the Soft Error Mitigation (SEM) Controller, an IP core which may be implemented in the firmware. Correction capability depends on the structure of the error and SEM mode. n 1 X Memory divided into frames (1 frame = 101 32-bit words) SEM protected each frame with an Error Correction Code (ECC). 1. Incident neutron ionising particle SEU?
Single-Event Upsets in the PANDA EMC 8/14 Error detection and correction Xilinx provides the Soft Error Mitigation (SEM) Controller, an IP core which may be implemented in the firmware. Correction capability depends on the structure of the error and SEM mode. 2 Memory divided into frames (1 frame = 101 32-bit words) SEM protected each frame with an Error Correction Code (ECC). 1. Incident neutron ionising particle SEU? 2. Single-Bit Upset (SBU). Corrected.
Single-Event Upsets in the PANDA EMC 8/14 Error detection and correction Xilinx provides the Soft Error Mitigation (SEM) Controller, an IP core which may be implemented in the firmware. Correction capability depends on the structure of the error and SEM mode. 3 Memory divided into frames (1 frame = 101 32-bit words) SEM protected each frame with an Error Correction Code (ECC). 1. Incident neutron ionising particle SEU? 2. Single-Bit Upset (SBU). Corrected. 3. Intra-Frame Multi-Bit Upset (MBU).Corrected.
Single-Event Upsets in the PANDA EMC 8/14 Error detection and correction Xilinx provides the Soft Error Mitigation (SEM) Controller, an IP core which may be implemented in the firmware. Correction capability depends on the structure of the error and SEM mode. 4 Memory divided into frames (1 frame = 101 32-bit words) SEM protected each frame with an Error Correction Code (ECC). 1. Incident neutron ionising particle SEU? 2. Single-Bit Upset (SBU). Corrected. 3. Intra-Frame Multi-Bit Upset (MBU).Corrected. 4. Inter-Frame MBU. NOT corrected
Single-Event Upsets in the PANDA EMC 8/14 Error detection and correction Xilinx provides the Soft Error Mitigation (SEM) Controller, an IP core which may be implemented in the firmware. Correction capability depends on the structure of the error and SEM mode. 5 Memory divided into frames (1 frame = 101 32-bit words) SEM protected each frame with an Error Correction Code (ECC). 1. Incident neutron ionising particle SEU? 2. Single-Bit Upset (SBU). Corrected. 3. Intra-Frame Multi-Bit Upset (MBU).Corrected. 4. Inter-Frame MBU. NOT corrected 5. Inter-Frame MBU + extra. NOT corrected
Single-Event Upsets in the PANDA EMC 9/14 Measurement process Start Configure FPGA Beam on Beam off Log file SEU time + address Yes Detect SEU Correctable? No
Single-Event Upsets in the PANDA EMC 10/14 Results SEU cross section The cross section for an SEU is given by Number of SEU σ SEU = N SEU T meas Φ n N bits Measurement duration Neutron flux Total number of bits
Single-Event Upsets in the PANDA EMC 10/14 Results SEU cross section The cross section for an SEU is given by Number of SEU σ SEU = N SEU T meas Φ n N bits Measurement duration Neutron flux Total number of bits Upset rate, r SEU : r SEU = σ SEU Φ n N bits Mean Time Between Failures, MTBF : 1 MTBF = σ SEU Φ n N bits
Results SEU cross section 1.2 10-14 1.0 10-14 σ SEU [cm 2 bit -1 ] 8.0 10-15 6.0 10-15 4.0 10-15 2.0 10-15 This measurement Wirthlin et al. [1] 4.0 10 5 5.0 10 5 6.0 10 5 7.0 10 5 8.0 10 5 9.0 10 5 1.0 10 6 1.1 10 6 1.2 10 6 Neutron flux Φ [cm -2 s -1 ] [1] Wirthlin, M. J. et al. (2014) JINST. 9 C01025. Larger Kintex-7 @ TSL Single-Event Upsets in the PANDA EMC 11/14
Results SEU cross section 1.2 10-14 1.0 10-14 σ SEU [cm 2 bit -1 ] 8.0 10-15 6.0 10-15 4.0 10-15 2.0 10-15 Average σ SEU = 7.48 10-15 (± 7%) cm 2 bit -1 4.0 10 5 5.0 10 5 6.0 10 5 7.0 10 5 8.0 10 5 9.0 10 5 1.0 10 6 1.1 10 6 1.2 10 6 Neutron flux Φ [cm -2 s -1 ] Cross section is independent of the neutron flux. Single-Event Upsets in the PANDA EMC 11/14
Single-Event Upsets in the PANDA EMC 12/14 SEU rates in the Electromagnetic Calorimeter A simulation of the neutron flux in the EMC has been made using PandaRoot. p pbar = 15 GeV/c, L = 2 10 32 cm 2 s 1 Φ n at position of digitisers is 150 cm 2 s 1. Assumptions: (i) neutron energy spectra are identical, (ii) only neutrons > 10 MeV cause SEUs, (iii) all boards are placed at same position (1 m from centre at FW endcap). MTBF 22000 s per FPGA.
Single-Event Upsets in the PANDA EMC 12/14 SEU rates in the Electromagnetic Calorimeter A simulation of the neutron flux in the EMC has been made using PandaRoot. p pbar = 15 GeV/c, L = 2 10 32 cm 2 s 1 Φ n at position of digitisers is 150 cm 2 s 1. Assumptions: (i) neutron energy spectra are identical, (ii) only neutrons > 10 MeV cause SEUs, (iii) all boards are placed at same position (1 m from centre at FW endcap). MTBF 22000 s per FPGA. But, 600 boards in the EMC, with 2 FPGAs per board. The results scale: rseu = 0.056 s 1 MTBF = 18.1 s. MTBF for errors not correctable by SEM = 584 s 9.7 min. That is, every 10 minutes reconfiguration would be needed somewhere in the EMC (300 ms from Flash).
Single-Event Upsets in the PANDA EMC 13/14 Summary and Outlook Soft errors in the Configuration Memory of the Kintex-7 FPGA have been studied.
Single-Event Upsets in the PANDA EMC 13/14 Summary and Outlook Soft errors in the Configuration Memory of the Kintex-7 FPGA have been studied. The cross section for SEU in the Kintex-7 Configuration Memory was determined to be 7.48 10 15 cm 2 bit 1, in agreement with previous results.
Single-Event Upsets in the PANDA EMC 13/14 Summary and Outlook Soft errors in the Configuration Memory of the Kintex-7 FPGA have been studied. The cross section for SEU in the Kintex-7 Configuration Memory was determined to be 7.48 10 15 cm 2 bit 1, in agreement with previous results. The Mean Time Between Failures in the Configuration memory in the whole EMC would be 18.1 seconds (any error type) 9.7 minutes (uncorrectable errors) The uncorrectable errors could be mitigated with other methods (for example TMR of the Configuration Memory).
Single-Event Upsets in the PANDA EMC 13/14 Summary and Outlook Soft errors in the Configuration Memory of the Kintex-7 FPGA have been studied. The cross section for SEU in the Kintex-7 Configuration Memory was determined to be 7.48 10 15 cm 2 bit 1, in agreement with previous results. The Mean Time Between Failures in the Configuration memory in the whole EMC would be 18.1 seconds (any error type) 9.7 minutes (uncorrectable errors) The uncorrectable errors could be mitigated with other methods (for example TMR of the Configuration Memory). Upcoming proton irradiation at KVI, Groningen (November). Thermal-neutron irradiation in Stockholm is planned.
Thank you for your attention! Single-Event Upsets in the PANDA EMC 14/14