Low Power Shift Register Design Based on a Signal Feed Through Scheme 1 Mr. G Ayappan and 2 Ms.P Vinothini, 1 Assistant Professor (Senior Grade), 2 PG scholar, 1,2 Department of Electronics and Communication, Sri Ramakrishna Institute of Technology,Coimbator, India Abstract: A Flip-flop has become a basic storage element in all kinds of digital design but there is a long discharging path problem in flip-flop. In order to overcome this problem a technique of low power pulse triggered flip-flop (P-FF) based on a signal feed through scheme is used. In this project shift registers are designed based on that flip-flop. This method provides low power, better speed and minimum area compared with other designs. PIPO shift register is designed because the output coming a single clock pulse. The technology used here is CMOS 250nm technology. The simulations are carried out using Tanner EDA software. This software contains S Edit, T Spice, W Edit and L Edit windows. S Edit window is used to design the circuit. T Spice window is used to generate the program for the circuit. The layout is generated automatically using the L Edit. The number of transistor is reduced from 116 to 96 and the power is reduced from 31μw to 25μw which in turn reduces layout area using this method Keywords: Shift register; Pass transistor; FF pulse generator; I. INTRODUCTION Shift Registers are a type of sequential logic circuit, mainly used for storing digital data. They are group of Flip-flops connected in a chain and the output from one Flip-flop becomes the input of the next Flip-flop. Register consist of set of n Flip-flop and each Flip-flop stores one data and they have two basic functions, they are data storage and data movement. A Register is a device that allows each of the Flip-flops to pass the stored information to its adjacent neighbour. The storage capacity of a register is the total number of bits (1 or 0) of digital data it can retain. Each stage (flip flop) in a shift register represents one bit of storage capacity. Therefore the number of stages in a register determines its storage capacity. It features parallelinputs, parallel outputs, right shift, left shift, serial inputs and reset. The appropriate choice of flip-flop (FF) topologies is of fundamental importance in the design of VLSI integrated circuits and low-energy Microprocessor. Indeed, FFs affect the clock frequency, since their delay occupies a significant fraction of the clock cycle, especially in fast microarchitectures with low logic depth. FFs are part of the clock network, which is responsible for 30% 50% of the whole chip energy budget [1]-[4]Reduced swing clock driver and a special flip-flop to reduce leakage current was designed in [5]. In order to reduce the total power of the system clock swing should be reduced because clock system power is directly proportional to clock swing or sometimes directly proportional to square of the clock swing. This Flip-flop consists of true single phase master latch and cross coupled NAND slave latch. The type the pulse generation control logic, an AND function is removed from the critical path to facilitate a faster discharge operation[6]. A simple two-transistor AND gate design is used to reduce the circuit complexity. Second, a conditional pulseenhancement technique is devised to speed up the discharge along the critical path only when needed. The conditional discharge flip-flop [7]-[10]is based on a new technology, known as the conditional discharge technology. This CDFF not only reduces the internal switching activities, but also generates less glitches at the output In this paper Shift registers are designed with the help of signal feed through scheme that is feeding the input directly to the internal node of the latch design to speed up the data transition and this is done with the help of pass transistor. The main aim of the paper is to reduce the long discharging path problem in conventional explicit type pulse triggered Flip-flop and to design a PIPO shift register using signal feed through scheme for providing better speed and performance with low power and minimum area consumption. This paper is organised as follows. Section II discusses about types of flipflop. Section III explained a Pass transistor design based flipflop. The PIPO shift register is described in section IV.The results of comparison and simulation of the shift registers in Section V. Finally, the conclusion is drawn in Section VI. II. TYPES OF FLIPFLOP The true single phase clocked register (TSPCR) uses a single clock, CLK. For the positive latch, when CLK is high, the latch is in the transparent mode and corresponds to two cascaded inverters; the latch is non-inverting, and propagates the input to the output On the other hand, when CLK=0, both inverters are disabled, and the latch is in the hold mode. Only the pull-up networks are still active, while the pull-down circuits are deactivated. As a result of the dual-stage approach, no signal can ever propagate from the input of the latch to the output in this mode. A register can be constructed by cascading positive and negative latches. Figure 1: Explicit Data Close to Output Explicit data close to output flipflip shown in figure1 consist of NAND-logic-based pulse generator and a semi dynamic True Single Phase Clock (TSPC) structured latch design. In this P-FF design, inverters I3 and I4 are used to latch the data, and inverters I1 and I2 are used to hold the internal node X. The pulse width is determined by the delay of three inverters. This design suffers from a serious drawback, i.e., the internal node X is discharged on every rising edge of the clock in spite Available Online@ 303
of the presence of a static input 1.This gives rise to large switching power dissipation To overcome this problem, many remedial measures such as Conditional capture, conditional precharge, conditional discharge, and Conditional pulse enhancement scheme have been proposed. An extra nmos transistor MN3 controlled by the output signal Q_fdbk is employed so that no discharge occurs if the input data remains 1. In addition, the keeper logic for the internal node X is simplified and consists of an inverter plus a pull-up pmostransistor. Figure 2: Conditional Discharge Flipflop To overcome this delay for better speed performance, a powerful pull-down circuitry is needed, which causes extra layout area and power consumption. The modified hybrid latch Flip-flop (MHLFF) shown in Figure 3. The keeper logic at node X is removed. A weak pull-up transistor MP1controlled by the output signal Q maintains the level of node X when Q equals 0. Figure 3: Modified Hybrid Latch Flipflop III. PASS TRANSISTOR FLIPFLOP Recalling the four circuits discussed chapter they all encounter the same worst case timing occurring at 0 to 1 data transitions. Referring to Figure 4 the pass transistor Flip-flop adopts a signal feed-through technique to improve this delay. Similar to the SCDFF design, this Flip-flop also employs a static latch structure and a conditional discharge scheme to avoid superfluous switching at an internal node. However, there are three major differences that lead to a unique TSPC latch structure and make the pass transistor design distinct from the previous one Figure 4: Pass Transistor Flipflop First, a weak pull-up pmos transistor MP1 with gate connected to the ground is used in the first stage of the TSPC latch. This gives rise to a pseudo nmos logic style design, and the charge keeper circuit for the internal node X can be saved. In addition to the circuit simplicity, this approach also reduces the load capacitance of node second, a pass transistor MNx controlled by the pulse clock is included so that input data can drive node Q of the latch directly (the signal feed-through scheme).along with the pull-up transistor MP2 at the second stage inverter of the TSPC latch, this extra passage facilitates auxiliary signal driving from the input source to node Q. The node level can thus be quickly pulled up to shorten the data transition delay. Third, the pull-down network of the second stage inverter is completely removed. Instead, the newly employed pass transistor MNx provides a discharging path. The role played by MNx is thus twofold, i.e., providing extra driving to node Q during 0 to 1 data transitions, and discharging node Q during 1 to 0 data transitions. Compared with the latch structure used in SCDFF design, the circuit savings of the pass transistor logic include a charge keeper (two inverters), a pull-down network (two nmos transistors), and a control inverter. The only extra component introduced is an nmos pass transistor to support signal feed through. This scheme actually improves the 0 to 1 delay and thus reduces the disparity between the rise time and the fall time delays. In comparison with other P-FF designs such as EP-DCO, CDFF, and SCDFF, the pass transistor design shows the most balanced delay behaviour. The principles of FF operations of the pass transistor logic are explained as follows. When a clock pulse arrives, if no data transition occurs, i.e., the input data and node Q are at the same level, on current passes through the pass transistor MNx, which keeps the input stage of the FF from any driving effort. At the same time, the input data and the output feedback Q_fdbk assume complementary signal levels and the pull-down path of node X is off. Therefore, no signal switching occurs in any internal nodes. On the other hand, if a 0 to 1 data transition occurs, node X is discharged to turn on transistor MP2, which then pulls node Q high. Referring to Figure 4.this corresponds to the worst case timing of the FF operations as the discharging path conducts only for a pulse duration. However, with the signal feed through scheme, a boost can be obtained from the input source via the pass transistor MNx and the delay can be greatly shortened. Although this seems to burden the input source with direct charging/discharging responsibility, which is a common pitfall of all pass transistor logic, the scenario is different in this case because MNx conducts only for a very short period. Available Online@ 304
Referring to Figure 4.6 when a 1 to 0 data transition occurs, transistor MNx is likewise turned on by the clock pulse and node Q is discharged by the input stage through this route. Unlike the cascade of 0 to 1 data transition, the input source bears the sole discharging responsibility. Since MNx is turned on for only a short time slot, the loading effect to the input source is not significant. In particular, this discharging does not correspond to the critical path delay and calls for no transistor size weaking to enhance the speed. In addition, since a keeper logic is placed at node Q, the discharging duty of the input source is lifted once the state of the keeper logic is inverted. IV. PIPO SHIFT REGISTER The are many types of shift registers used for storing purpose the are SISO,SIPO,PISO,PIPO etc. but parallel in parallel out is used in this paper because the output will comes in a single clock pulse For parallel in - parallel out shift registers, all data bits appear on the parallel outputs immediately following the simultaneous entry of the data bits. The figure 4.11 shows a four-bit parallel in - parallel out shift register constructed by D flip-flops. Figure 8: Output of Pass Transistor Flipflop Figure 5: block diagram of shift register The D's are the parallel inputs and the Q's are the parallel outputs. Once the register is clocked, all the data at the D inputs appear at the Corresponding Q outputs simultaneously. Figure 4.11 shows the block diagram of PIPO shift register Figure 9: Layout of pass transistor flipflop Figure 6: Circuit Diagram of Shift Register V. SIMULATION AND COMPARISON RESULTS The simulation and the layout are generated using TANNER EDA software and the simulation results are shown in the figure 7 to 15 and the comparison results for the flipflop and the shift registers are shown in the table 1 and 2 Figure10: Circuit diagram of EPDCOflipflop Figure 7: circuit diagram of pass transistor Available Online@ 305
Figure 14: Output of pass transistor Figure 11: Output of EPDCO Figure 12: Layout of EPDCO Figure 15: Layout of pass transistor Table 1: Comparison Results for Flipflop PARAMETER EP DCO C D F F SCDFF PASS TRANSIST OR LOGIC No.of 28 30 31 24 transistor Power(µw) 24.0 3 19.0 6 19.28 17.89 PARAMETER Table 2: Comparison results for shift register EP DCO CDFF MHLFF PASS TRANSISTOR LOGIC No.of 112 124 120 96 transistor Power(µw) 31.2 30 29 25.8 Figure 13: Circuit diagram of pass transistor The comparison result shows that the number of transistors for the flipflop is reduced to 24 and the number of transistors for the shift registers are reduced to 96 as the same way the power is reduced to 17.89 µw for flipflops and then the shift register power is reduced to 25.8µw. CONCLUSION The comparison result shows that the shift register using pass transistor Flip-flop has less number of transistor compared to Available Online@ 306
other shift register and consume less power compared to other shift register. It also seen that the number of transistor for pass transistor shift register is 96 but for other shift register like EPDCO, CDFF, SCDFF, MHLFF is greater than 100 and this reduce area and the simulation are carried out using tanner EDA software and the layout were generatedthe same method can be extended to more number of bits and can be used for higher data storage. It can be also used for other shift register like Serial In Serial Out (SISO), Serial In Parallel Out (SIPO) and Parallel In Serial Out (PISO). In the future References [1] B. Kong, S. Kim, and Y. Jun, Conditional-capture flip-flop for statistical power reduction, IEEE J. Solid-State Circuits, vol. 36, no. 8, pp. 1263 1271, Aug. 2001 [2] E. Consoli, M. Alioto, G. Palumbo, and J. Rabaey, Conditional pushpull pulsed latch with 726 fjops energy delay product in 65 nm CMOS, in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2012, pp. 482 483. [3] F. Klass, C. Amir, A. Das, K. Aingaran, C. Truong, R. Wang, A. Mehta, R. Heald, and G. Yee, A new family of semi-dynamic and dynamic flip-flops with embedded logic for high-performance processors, IEEEJ. Solid-State Circuits, vol. 34, no. 5, pp. 712 716, May 1999. [4] H. Partovi, R. Burd, U. Salim, F.Weber, L. DiGregorio, and D. Draper, Flow-through latch and edge-triggered flip-flop hybrid elements, in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 1996,pp. 138 139. [5] H. Kawaguchi and T. Sakurai, A reduced clockswing flip-flop (RCSFF) for 63% power reduction, IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 807 811, May 1998. [6] H. Mahmoodi, V. Tirumalashetty, M. Cooke, and K. Roy, Ultra low power clocking scheme using energy recovery and clock gating, IEEETrans. Very Large Scale Integr. (VLSI) Syst., vol. 17, no. 1, pp. 33 44, Jan. 2009. [7] Jin Fa Lin Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, No. 1, January 2014. [8] J. Tschanz, S. Narendra, Z. Chen, S. Borkar, M. Sachdev, and V. De, Comparative delay and energy of single edge-triggered and dual edge triggered pulsed flip-flops for high-performance microprocessors, in Proc. ISPLED, 2001, pp. 207 212. [9] K. Chen, A 77% energy saving 22-transistor single phase clocking D-flip-flop with adoptive-coupling configuration in 40 nm CMOS, in Proc. IEEE Int. Solid-State Circuits Conf., Nov. 2011, pp. 338 339. [10] M. Alioto, E. Consoli, and G. Palumbo, General strategies to design nanometer flip-flops in the energy-delay space, IEEE Trans. CircuitsSyst., vol. 57, no. 7, pp. 1583 1596, Jul. 2010. [11] M. Alioto, E. Consoli, and G. Palumbo, Flip-flop energy/performance versus Clock Slope and impact on the clock network design, IEEETrans. Circuits Syst., vol. 57, no. 6, pp. 1273 1286, Jun. 2010. [12] M. Alioto, E. Consoli, and G. Palumbo, Analysis and comparison in the energy-delay-area domain of nanometer CMOS flip-flops: Part I- methodology and design strategies, IEEE Trans. Very Large ScaleIntegr. (VLSI) Syst., vol. 19, no. 5, pp. 725 736, May 2011. [13] M. Alioto, E. Consoli and G. Palumbo, Analysis and comparison in the energy-delay-area domain of nanometer CMOS flip-flops: Part II -results and figures of merit, IEEE Trans. Very Large Scale Integr. (VLSI)Syst., vol. 19, no. 5, pp. 737 750, May 2011. [14] M.-W. Phyu, W.-L.Goh, and K.-S. Yeo, A lowpower static dual edge triggered flip-flop using an output-controlled discharge configuration, in Proc. IEEE Int. Symp. Circuits Syst., May 2005, pp. 2429 2432. [15] P. Zhao, T. Darwish, and M. Bayoumi, Highperformance and low power conditional discharge flip-flop, IEEE Trans. Very Large ScaleIntegr. (VLSI) Syst., vol. 12, no. 5, pp. 477 484, May 2004. Available Online@ 307