VELAMMAL COLLEGE OF ENGINEERING AND TECHNOLOGY, MADURAI 65 009 Department of Information Technology Model Exam-II-Question bank PART A (Answer for all Questions) (8 X = 6) K CO Marks Find the equivalent value for the given decimal number. Decimal to other number system ( Sample). Find the equivalent decimal value for the given value Other number system to decimal ( Sample)
Show the result after arithmetic operation. Division ( Sample) Show the result after arithmetic operation. Subtraction:( sample)
Find the result of BCD addition. Sample Outline the operation of GATES Gate: Boolean functions may be practically implemented by using electronic gates.
. Show the Duality expression. The principle of duality in Boolean algebra states that if you have a true Boolean statement (equation) then the dual of this statement (equation) is true. The dual of a boolean statement is found by replacing the statement s symbols with their counterparts. This means a 0 becomes a, becomes a 0, + becomes a. and. becomes a +. Example: 0. = 0 Dual expression of this + 0 = Show the canonical POS for the following Boolean expression. Example: What are Minterm and Maxterm? Give an Example. Each individual term ( product term ) in standard/canonical SOP is called Minterm. Each individual term ( Sum term ) in standard/canonical POS is called Maxterm. Min term: Maxterm: 4. State and Explain Demorgans law.
4 Reduction of Boolean expression using laws. Sample:
Show logic AND operation using only NAND gate. 4 5 What is Magnitude Comparator? A digital comparator or magnitude comparator is a hardware electronic device that takes two numbers as input in binary form and determines whether one number is greater than, less than or equal to the other number.
Show the symbol and truth table for Half Subtractor. The half subtractor is a combinational circuit which is used to perform subtraction of two bits. It has two inputs, the minuend and subtrahend and two outputs the difference and borrow out. 5 5 6 List out the applications of decoder. The applications of decoder are a. Decoders are used in counter system. b. They are used in analog to digital converter. c. Decoder outputs can be used to drive a display system. What is priority encoder? In priority encoder, if two or more inputs are equal to at the same time, the input having the highest priority will take precedence. It's applications includes used to control interrupt requests by acting on the highest priority request to encode the output of a flash analog to digital converter Show :4 demux. 6 6 Compare combinational and sequential circuit.
7 7 Explain analysis procedure for combinational circuit? Find the given circuit is combinational or sequential. Combinational circuit has a logic gate with no feedback paths or memory elements. A feedback path is a connection from the output of one gate to the input of second gate that forms part of the input to the first gate. Find out the Boolean function from the logic diagram. ( Label all gate o/p s that are function of input variables) b. Design a combinational circuit which accepts three inputs a, b and c and generate only one output. The output is equal to 0, if the input contains odd number of s. Otherwise output is equal to one. Design 4:6 decoder using :8 decoder. 7 E A B C Y0... Y7 Y8 Y5 0 0 0 0 0 0... 0... 0 0 0 0 0 0 0 0 0 0... 0 0 0
8 What is Multiplexer/Data selector? List out the applications of multiplexer. A multiplexer is a device that selects one of several analog or digital input signals and forwards the selected input into a single line. The various applications of multiplexer are a. Data routing. b. Logic function generator. c. Control sequencer. d. Parallel-to-serial converter. Design 4: mux using :. 8 8 Show the block diagram and Truth table of : and 4:Mux.
9 What do you mean by triggering of flip-flop? The output of a flip flop can be changed by bring a small change in the input signal. This small change can be brought with the help of a clock pulse or commonly known as a trigger pulse. When such a trigger pulse is applied to the input, the output changes and thus the flip flop is said to be triggered. 9 Distinguish latch and flip flop The difference between a latch and a flip-flop is that a latch is asynchronous, and the outputs can change as soon as the inputs do (or at least after a small propagation delay). A flip-flop, on the other hand, is edge-triggered and only changes state when a control signal goes from high to low or low to high. 9 Summarize about SR Latch.
. Show the excitation table of SR flip flop. 0 Show the block diagram of SIPO shift register. 0
What is the characteristic equation for SR and JK flip flop. 0
PART B Answer for all questions 5*=65 () Find the duality and complement of the following. () Show that the logic diagram of OR GATE using only NAND and NOR operation. Definition of universal gate- Mark OR gate using NAND with expression 4 Marks 4+ 9 OR Gate using NOR with expression- 4 Marks Utilize K-Map technique and find the minimized POS for the following switching function. Construction of KMap with variables Placing Maxtern in K map with don t care Grouping of Max terms- 4 Minimized expression- Circuit diagram for minimized expression - Identify the minimized expression for the following: Construction of KMap with variables Placing Maxterm in K map with don t care Grouping of Max terms- 4 Minimized expression- Circuit diagram for minimized expression - Identify minimal Boolean expression using K-Map Conversion of expression into standard POS format 4 Marks Construction of KMap with variables Placing Maxterm in K map Grouping of Max terms- Minimized expression- Circuit diagram for minimized expression - What are universal gate? Why it is called so? Show the AND, OR, NOT, EX OR operation using. NAND. NOR Definition of universal gate and justification - Marks Each gate with circuit diagram and expression AND, OR, NOT Mark for each gate EX-OR Marks
4 4 4 5 5 5 Identify minimal Boolean expression using K-Map. Conversion of expression into standard SOP format 4 Marks Construction of KMap with variables Placing Maxterm in K map Grouping of Max terms- Minimized expression- Circuit diagram for minimized expression Build a full subtractor and discuss the operation using truth table. Definition for Full subtractor Marks Block Diagram Mark Truth table 5 Marks K map for Borrow and Difference Marks Circuit diagram for B and D- Marks a. Construct 8: MUX using 4: MUX 7+6 Definition for MUX Mark Block diagram Marks Truth Table Marks b. Implement the following function using 4: Multiplexer. Implementation table Marks Block Diagram Marks Design priority encoder. Truth Table 5 Marks K map- 5 Marks Circuit diagram Marks Build a Carry look Ahead adder circuit and discuss the operation with an example. Build combinational logic circuit which converts Gray into BCD code. Code conveter definition mark Conversion table 6 Marks Kmap 4 Marks Circuit diagram Marks Build combinational logic circuit which converts BCD into Binary code. Code conveter definition mark Conversion table 6 Marks Kmap 4 Marks Circuit diagram Marks Convert SR flip flop into JK flip flop. Truth table and excitation table of flip flop Marks Conversion Table 5 Marks K map 5 marks Circuit diagram - Design sequence generator using T flip flop for the following sequence. 000 Definition of counter: marks Table and sequence diagram Marks Counter design table 5 Marks K map Marks Circuit diag4ram mark Design counter using SR flip flop for the following sequence. Avoid lockout condition. 0---7-6-5 Definition of counter: marks Sequence diagram Marks
Counter design table 5 Marks K map 4 Marks Circuit diag4ram mark PART C ( X5 = 5) 6 Build bit Asynchronous Down counter. Definition for counter Mark Construction using JK 6 Marks Explanation 6 Marks Timing Diagram K 5 6 Deign a sequential circuit for a state diagram shown in figure. Use state assignment rules for assigning states and compare the required combinational circuit with random assignment. K 5 6 Definition : Mark Random Assignment table marks K map marks Requirements of gate for RA marks State assignment rule marks Truth table for SA - marks K map- marks Requirements of gate for SA marks Construct bit synchronous up counter. Definition for counter Mark Construction using JK 6 Marks Explanation 6 Marks Timing Diagram K 5