SCIENTIFIC DATA SYSTEMS. Reference Manual

SCENTFC DATA SYSTEMS Reference Manual

SOS 92 BASC NSTRUCTONS (CENTRAL PROCESSOR) Mnemnic Octal Cde Name Mnemnic Octal Cde Name LOAD/STORE BRANCH LDA A, T 64 Lad A BRU A, T 73 Branch Uncnditinally LDB A, T 24 Lad B BRC A, T 32 Branch, Clear nterrupt, and Lad Flag STA A, T 44 Stre A BRL A, T 33 Branch and Lad Flag STB A, T 04 Stre B BFF A, T 31 Branch n Flag False XMA A, T 74 Exchange Memry and A BFT A, T 71 Branch n Flag True XMB A, T 34 Exchange Memry and B BDA A, T 70 Branch n Decrementing A BAX A, T 30 Branch and Exchange A and B FLAG BRM A, T 77 Branch and Mark Place BMC A, T 37 Branch, Mark Place, and Clear Flag XMF A, T 17 Exchange Memry and F LDF A, T 57 Lad F SHFT SFT 0044 Set Flag True SFF 0042 Set Flag False CYA A, T 42 Cycle A NF 0046 nvert Flag CYB A, T 02 Cycle B CFA A, T 43 Cyc e Flag and A ARTHMETC CFB A, T 03 Cycle Flag and B CYD A, T 02 r 42 Cycle Duble ADA A, T 62 Add t A CFD A, T 43 Cycle Flag and Duble ADB A, T 22 Add t B CF A, T 03 Cycle Flag and Duble nverse ACA A, T 63 Add with Carry t A ACB A, T 23 Add with Carry t B CONTROL SUA A, T 60 Subtract t A SUB A, T 20 S ubtrac t t B EXU A, T 72 Execute SCA A, T 61 Subtract with Carry t A HLT 0041 r Halt SCB A, T 21 Subtract with Carry t B 00000000 MPA A, T 76 Memry Plus A t Memry MPB A, T 36 Memry Plus B t Memry TRAP MPO A, T 16 Memry Plus One t Memry MPF A, T 56 Memry Plus Flag t Memry SCT 0061 Set Prgram-cntrlled Trap MUA A, T 13 Multiply A (Optinal) RCT 0060 Reset Prgram-cntrlled Trap MUB A, T 53 Multiply B (Optinal) TCT 0160 Test Prgram-cntrlled Trap DVA A, T 52 Divide AB (Optinal) DVB A, T 12 Divide BA (Optinal) BREAKPONT TESTS LOGCAL BPT 1 0144 Breakpint N. 1 Test BPT 2 0145 Breakpint N. 2 Test ANA A, T 65 AND t A BPT 3 0146 Breakpint N. 3 Test ANB A, T 25 AND t B BPT 4 0147 Breakpint N. 4 Test ORA A, T 67 OR t A ORB A, T 27 OR t B NTERRUPTS EOA A, T 66 Exclusive OR t A EOB A, T 26 Exclusive OR t B ER 0051 Enab e nterrupt MAA A, T 75 Memry AND A t Memry DR 0050 D i sab e nterrupt MAB A, T 35 Memry AND B t Memry let 0150 nterrupt Enabled Test AR 00020001 Arm nterrupts COMPARSON COA A, T 45 Cmpare Ones with A COB A, T 05 Cmpare Ones with B CMA A, T 47 Cmpare Magnitude f Memry with A CMB A, T 07 Cmpare Magnitude f Memry with B CEA A, T 46 Cmpare Memry Equa t A CEB A, T 06 Cmpare Memry Equal t B Legend: A = address; * A = indirect address; =A = immediate address; T = index tag

SOS 92 COMPUTER REFERENCE MANUAL June 1965 Ell' -\!J SCENTFC DATA SYSTEMS/1649 Seventeenth Street/Santa Mnica, Cal ifrnia @1965 Scientific Dt Systems, nc. Printed in U.S.A.

REVSONS Th is pu bl icatin, 90 05 05C, supersedes the SDS 92 Cmputer Reference Manual, 900505B. Revisins, crrectins, and clarificatins t the previus editin are indicated by a vertical ine in the left r right marg in f the page. ii

CONTENTS GENERAL DESCRPTON.... 1-1 1-1 1-3 1-4 1-4 1-4 1-6 APPENDXES ntrductin.... SDS 92 Registers.... SDS 9.2 Memry.... Memry Wrd Frmats.... Addressing Facil ities.... Trapping Facil ity.... MACHNE NSTRUCTONS Lad;Stre nstructins.... Flag nstructins.... Lgical nstructins.... Cmparisn nstructins.... Branch nstructins.... Shift nstructins.... Cntrl nstructins Trapping nstructins.... Breakp i nt Tests.... NPUT/OUTPUT SYSTEM.... 2-1 2-1 2-2 2-3 2-4 2-4 2-5 2-6 2-7 2-7 3-1 3-1 3-2 3-3 3-5 3-6 3-7 3-8 3-9 3-9 3-10 3-13 3-15 3-15 3-17 3-18 3-21 3-25 APPENDX A APPENDX B SDS Character Cdes Table f Pwers f Tw.... Octal-Decimal nteger Cnversin Table.. Octal-Decimal Fractin Cnversin Table. Tw's Cmplement Arithmetic.... Optinal Equipment Real-Time Clck Autmatic Pwer Fail-Safe.... Data Mu tiplexing System.... Memry Parity nterrupts.... Trapping Return Subrutine Example.... SDS 92 Memry Allcatin.... 92 nstructin List - Functinal Categries. 92 nstructin List - Numerical Order... 92 nstructin List - Alphabetical Order A-1 A-2 A-3 A-7 A-lO B-1 B-1 B-1 B-1 B-4 B-5 B-6 B-7 B-11 B-15 ntrdu ct in.... Data Transfer nstructins.... /O Channel Operatin.... EOM nstructins.... SES nstructins.... nterlace.... POT/BPO, PN/BP nstructins Single Bit nput/output.... /O Terminatin Prgramming Ntes.. Pririty nterrupt System (Optinal).. Cntrl Cnsle.... Peripheral Equ ipment Descriptin.... nput/output Typewriter.... Paper Tape nput/output.... Card nput/output.... Magnetic Tape nput/output Line Printer.... 1-1 1-2 3-1 3-2 3-3 3-4 3-5 3-6 3-1 3-2 3-3 FGURES SDS 92 Cmputer (Frntispiece).... SDS 92 Cmputer Cnfiguratin.... Basic Register Flw Diagram.... ROT/RN Data Transmissin.... SDS 92 Channel Buffer.... nterrupt Arm-Enable Respnse.... SDS 92 Cmputer Cntrl Panel.... Card Read int Memry in Hllerith.... Printer Cntrl ndicatrs and Switches TABLES Unit Address Cdes nterrupt Lcatin Assig nments.... Frmat Cntrl Characters.... iv 1-2 1-3 3-2 3-3 3-12 3-14 3-19 3-25 3-4 3-11 3-26 iii

J liin, ~" SDS 92 Cmputer iv

. GENERAL DESCRPTON NTRODUCTON The SDS 92 is a small, high-speed, very lw-cst, generalpurpse cmputer designed especially t include applicatin in the fllwing areas: High-speed cmputer-based systems featuring speed and flexibility Frmat cnversin featuring cmplete versatility in frmats and equipment invlved Small, general-purpse applicatins featuring repetitive, high-speed cmputatin The SDS 92 has the fllwing characteristics: The first cmmercia cmputer using mnlithic integrated circuits; all fl ip-flps are integrated 12-bit wrd plus parity bit 1.75 jjsec memry cyc e Binary, integer arithmetic 12- and 24-bit instructins mmediate, direct and indirect addressing 2048-wrd basic memry Memry expandable t 4096, 8192, 16,384 r 32,768 wrds, all directly addressable Tw independent arithmetic registers, either f which may be an accumulatr True ndex Register; adds n time t executin nstructin set cmparable t medium-scale cmputer; includes shift instructins 4096 single-bit cntrl utputs; 4096 single-bit sense inputs ndependent /O buffer with autmatic assembly/ disassemblyf 6-bit characters t/frm wrds (standard) /O blck transfer standard Three standard /O mdes: 6-bit characters, 286,000 characters/secnd, parity checked and packed 1 per wrd 6-bit characters, 286,000 characters/secnd, parity checked and packed 2 per wrd 12-bit parallel wrds, 572,000 wrds/secnd, parity checked /O transfer f 12-bit characters, 286,000 characters/ secnd, parity checked, ptinal Fur cnsle sense switches Optinal features nterlace feature fr standard /O buffer High-speed multiply and divide instructins, 5 and 13 cycles, respectively Many-channel Data Multiplexing System using a secnd, independent path t memry 24-bit parallel /O Up t 256 levels f true pririty interrupt Autmatic pwer fai -safe Memry parity checking Real-time clck Peripheral equipment fr the SDS 92 Sftware Keybard/printer (teletype) with r withut paper tape reader and punch, 10 cps Paper tape reader and punch, 300 and 60 cps, respectively MAGPAK Magnetic Tape System All equipment in SDS standard peripheral line Basic uti lity package Symblic assembler /O packages fr ptinal peripheral equipment Mathematical subrutines, including flatingpint arithmetic, fixed-pint multiply and divide, and elementary mathematical functins All silicn semicnductrs O perating temperature range: 100 t 40 0 C Dimensins: 65 in. x 30 in. x 25-1/2 in. Pwer: 1 kva 1-1

EOM SES 12-bit Wrd POT/PN Para e, Single Wrd BPO/BP r Blc k (24-bit Single Wrd 0 ptinal).--_.. 12 bits Optinal L 6 bits (plus parity) {} Pririty nterrupt up t 256 Levels J t t t SDS 92 Cmputer Basic /O Channel ~ External Devices ~ 12 bits WOT;WN ROT/RN t t f t t Cre Memry 2048 Wrds Expandable t : 4K 8K 16K 32K t Secn d Memry Path Data Multiplex System! 4 f t f Subchannels (6-bit, 12-bit, r 24-bit) tems with dtted lines (---) are ptinal. Figure 1-1. SDS 92 Cmputer Cnfiguratin 1-2

SDS 92 REGSTERS The 92 Central Prcessr cntains the fllwing arithmetic and cntrl registers. They are full-wrd, 12-bit registers except as nted. AVALABLE TO THE PROGRAMMER (dark lines) The A Register and the B Register are tw independent, 12-bit accumulatrs. The A Register is als the index register. The P Register is a 15-bit register that cntains the memry address f the current instructin. Unless mdified by the prgram, the cntents f P increase by ne during ne-wrd instructins and increase by tw during tw-wrd instructins. The Flag Bit Register is a ne-bit register used fr arithmetic carry, strage and testing. NOT AVALABLE TO THE PROGRAMMER (light lines) The S Register is a 15-bit register that cntains the address f the memry lcatin being accessed fr instructins r data. The C Register, is a 12-bit register that is used in arithmetic and cntrl peratins. The 0 Register is a 6-bit register that cntains the peratin cde f the instructin being executed. The M Register is a 13-bit register that hlds each wrd as it cmes frm memry. Recpying f a wrd int memry takes place frm the M Register. 1 Flag B;, F j B (Accumu latr) A (Accumulatr and/ r ndex) j Adder,, -- S (Memry Address) - C (Arithmetic and Cntrl) P (Prgram Cunter) -- M (Memry Access) (Opcde) --------------------~ Memry Figure 1-2. Basic Register Flw Diagram 1-3

SDS 92 MEMORY The basic 92 memry cntains 2048 wrds, cnsisting f 12{,its plus parity. Memry is available in 4096-, 8192-, 16,384- and 32,768-wrd sizes. The central prcessr can directly address all memry. Addresses fr memry wrds extend frm lcatins 00000 t 77777 (ctal). f the address f the next instructin t be executed is utside f available memry (fr less than 32,768-wrd memries), the 92 executes a halt instructin (00000000); the P Register wi cntain the requested address + 2. Fr example, assume a 3777-wrd memry and ffers great versatility bth in addressing and indexing capabilities. n mst cases, the instructin can select either the A r B fr use as the accumulatr. Bit Psitin 1-5 6 Meaning Register Selectin: 1 = A Register r = B Register nstructin Cde Scratch Pad Bit 1. the instructin "Branch-t" 4000, r 2. the instructin "Lad A" whse lcatin is 3777. 7 8 ndirect Address Bit ndex Register Bit n bth cases, a halt ccurs after executin f the instructin and the P Register cntains 4002 which is utside f available memry. Nte that the P Register respnds as if there were always 32,768 wrds f memry. With a 32,768-wrd memry, the memry is a "wrap-arund" r circular memry where the next lcatin after 77777 is 00000. An attempt t read frm a lcatin whse address is nt avai lable causes zers t be read. An attempt t stre int such a lcatin essentially results in a "n-p" peratin, with the next instructin in sequence being executed. A prgram can use th is prperty t determine the cre size avai lable in the machine. A pwer fai -safe ptin is avai lable such that: befre accessing each memry wrd, the c;"puter checks the pwer t ensure that it can cmplete the entire read/write cycle. f it detects a pwer lss, the cmputer halts. With the memry parity ptin, the cmputer autmatically generates even parity r checks fr it during each read/write cycle (ptinal). Setting a cntrl panel pa~ity switch causes the cmputer t halt autmatically in case f parity errr detectin. MEMORY WORD FORMATS A cmputer wrd is 12 binary digits (bits) lng: " 2 3 4 5 6 7 8 9 10 11 The wrd frmat numbers the bits frm the left, r mst significant end f the wrd, t the right, r least significant end f the wrd. This numbering frmat serves as a basis f reference t bit psitins r bit numbers. Octal ntatin mst easi y describes the cntents f the 12 bits f a wrd. Thus, ne ctal digit, 0 thrugh 7, represents three binary digits. Fr example, the ctal number, 0123, represents its binary equivalent, 000 001 010 011. The 92 instructin wrd: Opcde 5 6 7 8 y 9 10 11 9-11 Part f the Address Field The flexibility f addressing in the 92 allws bits 7, 8, and 9 thrugh 11 t be used in mre than ne way as explained belw. ADDRESSNG FACLTES The 92 has ne-wrd r tw-wrd instructins with the length depending n the addressing mde being used. The addressing mdes are: Direct, Tw Wrds ndirect, One Wrd ndirect, Tw Wrds Direct, One Wrd mmediate, One Wrd Addressing Area Full Memry ndirect Thrugh Scratch Pad ndirect Thrugh Full Memry Scratch Pad Next Lcatin ndirect addressing can be cascaded indefinitely. The standard assembler frms fr instructins are: Frm Type Label Opcde n Direct, One and Tw Wrds Label Opcde n, 1 Direct, Tw Wrds, ndex Label Opcde *n ndirect, One and Tw Wrds Label Qpcde =c mmediate where n is a label r a 1- t 5-digit number, c is a 1- t 4-digit number «4096). The fllwing sectin describes the bit cnfiguratins that the ctal prgrammer r the symblic assembler must prvide t select the varius addressing mdes. Direct Addressing The prgrammer selects direct addressing by setting bth bits 6 and 7 t zer. Bits 9 thrugh 11 f the first wrd cmbine with the entire secnd wrd t frm a 15-bit address t directly address up t 32,768 wrds. Bit 8 f the first wrd can specify indexing. r The multiply instructins are exceptins. 1-4

nstructin Frm: LOW H 2 3 4 5 6 7 8 9 10 11 Direct Addressing With N ndexing The cmputer cnstructs the 15-bit direct address frm bits 9, 10, 11 f the instructin wrd and bits 0 thrugh 11 f the next lcatin. Example 1: R 0 Opcde 1 0 1 0 101 3 1M 5 6 7 8 9 10 11 2 0 0 0 M+ 1 0 2' 3 4 51 6 7 8 1 9 10 11 Assembler Frm: LDB 024300 Machine Language Frm: 2 4 2 4 3 234 5 6 7 8 9 10 11 Nte:.. 32000 n the standard assembler, a 0 precedes any ctal number; nth i ng precedes a dec i ma number written as a literal (i. e., immediate). Direct Addressing With ndexing When the prgrammer sets the ndex Bit (number 8) t 1, the cmputer subtracts the cntents f the A Register frm the direct address t btain the effective address. Example 2: Assume (A)=OOOl MMMMM NNNN Effective Address Assembler Frm: LDB 024300, Machine Language Frm: 2 4 2 M M+ 1 10 11 This instructin lads the cntents f lcatin 24277 int the B Register. Nte: Althugh the A Register is nly 12 bits lng, the tp three bits f the address will be mdified by indexing if a "brrw" ccurs. Scratch Pad Addressing Memry lcatins 00001 t 000378 are referred t as the "scratch pad" memry and are special nly in that they can be addressed mre si mply. When the prgrammer sets the Scratch Pad ndicatr (bit 6) t 1, the instructin addresses ne f the 31 scratch pad lcatins. This allws a cmplete instructin in a single wrd. The frm f the instructin is: Opcde 1 Scratch Pad., Address 1 5 6 7 8 9 10 11 The value f n must be in the range 1 ~ n ~ 31 10, Example: Assume. --- lcatin 34 Then the instructin: LDB 034 2 4 0 2 3 4 5 yields (8) = 2333 mmediate Addressing 7 Cntents 2333 4 6 7 8 9 1011 When the prgrammer sets the Scratch Pad ndicatr t 1 and sets bits 7 thrugh 11 t 00, the instructin acquires its address by adding ne t the current cntents f the $ Register. That is, the next lcatin cntains the perand. The cmputer autmatically increments the Prgram Cunter by an additinal ne t take the next instructin frm the wrd fllwing the immediate perand wrd. The frm f the instructin is: 1 Opcde 0 0 OPERAND t 2 3 4 5 6 7 8 9 10 11 The standard assembler frm is: LDA =, where "=" means "take the fllwing number literally". Example: -- LDA = 04311 6 4 2 3 4 5 6 7 8 9 10 11 n the standard assembler, a 0 precedes any ctal number; nthing precedes a decimal number written as a literal (i. e., immediate). 1-5

ndirect Addressing Take LDB *032000 which is! The indirect addressing facility prvides tw ways f specifying the pinting address. ndirect Frm Scratch Pad First, the single-wrd instructin specifies that the pinting address is within the secnd 16 lcatins f the Scratch Pad area (lcatins 208 thrugh 378). The specified pinting address used in the standard assembler frm must be in the range: 20.::; n ::; 36, n even. n this mde, the instructin bits have the frm: Opcde 2 13 4 where bit 6 is 0 and bits 7 and 8 are l. Bits 8 9 10 11 and C frm a five-bit address that selects the fi;st ~f t~ c~ntiguus address wrds. The cmputer always supplies a least significant fifth bit (C) that is zer, making all such Scratch Pad addresses even. When the addressing lgic selects the even address, it reinitiates addressing and interprets that lcatin and the next ne as an instructin wrd-pair withut an instructin cde. These tw (r ne) wrds can specify all frms f addressing. Bit 8 f the instructin des nt effect indexing in this perating mde. Example: Then, LDB *034 Lcatin Cnte~ts 34 0002 35 0010 20010 0004 yields reinitialized addressing n lcatins 34, 35. 34 35 0002 0010 Since the 0 in bits 6,7,8 f lcatin 34 indicates direct addressing, the instructin des the fllwing: ndirect Full Addressing (20010) = 0004~B The secnd frm f indirect addressing is: OP:Ode! : ~ :! 2 3 4 5 6 7 8 9 10 11 where the 0 in bit 8 specifies that the pinting address cnsists f a 15-bit address cnstructed as in Direct Addressing. Example: Assume Lcatin 32000 32001 14020 H Cntents 0001 4020 2200 2 2 0 2 This yields: : 3 4 2 0 0 4 5 : 6 7 (32000) = 0001 (32001) = 4020 8: 9 The lgic reinitializes addressing and ( 14020) :r: 2200----B The tw Pinter wrds can specify all frms f addressing. TRAPPNG FACLTY Prgram-Cntrl ed 3 0 10 11 The prgram-cntrlled trapping facility permits the calling f subrutines with a single instructin f the same frm as builtin, machine instructins. The trapping is cntrlled by the status f the Prgram-Cntrlled Trap (PCT) bit. When PCT is a 0, the cmputer decdes the eight trapping Opcdes as special instructins and executes the Opcde in the unique trapping lcatin determined by the Opcde. When PCT is a 1, the cmputer decdes the eight Opcdes as nrmal instructins. The Opcdes, their nrmal names, and their respective trapping lcatins fllw. Opcde Trapping Lcatin Nrmal Mnemnic 10 130 POT 50 132 BPO 11 134 WOT 51 136 ROT 14 140 PN 54 142 BP 15 144 WN 55 146 RN One f the "branch and mark place" instructins BRM r BMC placed in the trapping lcatin (and lcatin plus ne) by the prgrammer branches t the assciated subrutine. The mark infrmatin prvides the subrutine inkage back t the main prgram, i. e., the address stred in the mark is the address f the instructin that caused the trap. The prgram sets, resets, and tests the PCT bit via the instructin: SET PROGRAM-CONTROLLED TRAP (SCT) RESET PROGRAM-CONTROLLED TRAP (RCT) TEST PROGRAM-CONTROLLED TRAP (TCT) Multiply and Divide When the high-speed multiply/divide ptin is nt prese~t in a system, an attempt t execute the assciated instructin cde causes a transfer t a special trap lcatin. These lcatins are: Mnemnic Opcde Lcatin MUA 13 124 MUB 53 126 DVA 52 122 DVB 12 120 When the ptin is absent, the trapping prcess is always active and cannt be inhibited by the prgrammer. 1-6

Trapp i ng Ntes When a trap ccurs, the P cunter is nt incremented. t is therefre mandatry that nly branch instructins be placed in the trap instructins; therwise, the prgram ges int an unrecverable lp: Assume there is n multiply ptin. 124 L~A 1000 1200 MUA 5000 f MUA is executed, the executin sequence is: 1200 MUA 124 LDA 1200 MUA 124 LDA Appendix-B-5 cntains a cmplete trap-subrutine example. that is useful as a guide t writing subrutine return cde. Nmenclature Thrughut the fllwing discussins, the term "next lcati~n" refers t the lcatin immediately fllwing the lcatin f the instructin under discussin. The simi lar term "next address" is als used. The term "effective memry lcatin" describ~s the lcatin in memry frm which the cmputer takes the final perand at the cnclusin f all indirect addressing and indexing. The effective memry lcatin is the lcatin whse address is the effective address. 1-7

. MACHNE NSTRUCTONS This sectin describes SDS 92 instructins; they are presented in functinal grups. Lists f instructins in functinal, numerical and alphabetical rder are in Appendices B-7 thrugh B-17. The fllwing statements apply t the instructin descriptins. All instructin times are in memry cycles, where each cycle is 1.75 micrsecnds. All timings assume that the instructin addresses perands in scratch-pad memry (even thugh the instructin may, in fact, preclude this mde f addressing). Fr mre cmprehensive addressing, add cycles t the given executin times as fllws: mmediate Direct Full Addressing Direct Full with ndexing ndirect Addressing One-Wrd, even scratch-pad address ndirect Addressing Tw-Wrd, Fu add ress Cycles a P 1 + P where P is the number f cyc les required t prcess the indirect address pair. Parentheses dente cntents f ", as, fr example, (A) represents the cntents f the A Register. The interrupt system (ptinal) can interrupt the prgram sequence at the end f any instructin except as nted. STA (STB) a 44(04) STORE A (STORE B) Y 5 6 789 11 STA stres the cntents f the A Register in the effective memry lcatin. Registers Affected: M Timing: 2 XMA (XMB) EXCHANGE M AND A (EXCHANGE M AND B) a 74(34) 56789 11 XMA lads the cntents f the effective memry lcatin int the A Register and stres the cntents f the A Register in the effective memry lcatin. Registers Affected: A(B), M FLAG NSTRUCTONS XMF a 17 EXCHANGE M AND FLAG 56789 11 Timing: 3 XMF lads the cntent f the Flag Bit int bit a f the effective memry lcatin and lads the cntent f bit a int the Flag Bit; it leaves bit psitins 1 thrugh 11 f the effective memry lcatin the same as they were. Thse instructins that apply t the A and the B Registers appear with the B Register peratin cde and mnemnic in parentheses. Registers Affected: F, M LDF LOAD FLAG Timing: 3 With each instructin descriptin is a diagram depicting the instructin frmat. Preceding this diagram is the mnemnic cde and the instructin name. n the diagram, S stands fr Scratch Pad Bit, stands fr ndirect Address Bit, X stands fr ndex Bit, and Y stands fr part f the address. The letter M depicts a general memry lcatin. a 57 5 6 7 8 9 11. LDF lads the cntent f bit a f the effective memry lcatin int the Flag Bit. LOAD /STORE NSTRUCTONS LDA (LDB) a 64(24) LOAD A (LOAD B) 56789 11 LDA lads the cntents f the effective memry lcatin int the A Register. Registers Affected: A(B) Timing: 2 Registers Affected: F SFT a SET FLAG TRUE 00 5 6 44 SFT uncnditinally sets the Flag Bit t a ne. SFT cannt be interrupted. Registers Affected: F 11 Timing: 3 Timing: 3,4 2-1

SFF SET FLAG FALSE SUA (SUB) SUBTRACT TO A (SUBTRACT TO B) 00 5 6 SFF uncnditinally resets the Flag Bit t a zer. SFF cannt be interrupted Registers Affected: F Timing: 3,4 42 11 60(20) 5 6 7 8 9 11 SUA subtracts the cntents f the effective memry lcatin frm the cntents f A and places the result in Ai it stres the carry frm bit 0 in the Flag (F) bit. [(M) > (A) sets Fi (A) ~ (M) resets F.J NF NVERT FLAG Registers Affected: A(B), F Timing: 2 00 5 6 46 NF uncnditinally inverts the Flag Bit. it t a Oi if it is a 0, NF sets it t a 1. NF cannt be interrupted. Registers Affected: F ARTHMETC NSTRUCTONS 11 f it is a 1, NF sets Timing: 3,4 Example: Assume (A) = 3003 (10) = 4010 (F) = 0 SCA (SCB) Perfrming SUB 010 yields (A) = 6773 (F) = 1 SUBTRACT WTH CARRY TO A (SUBTRACT WTH CARRY TO B) ADA (ADB) 62(22) ADD TO A (ADD TO B) 5 6 7 8 9 11 ADA adds the cntents f the effective memry lcatin t the cntents f A and stres the result in Ai it stres the carry frm bit 0 f the additin in the Flag Bit. Registers Affected: A(B), F Example: Assume (A) = 4300 (1000) 3700 (F) = 0, Flag Bit ACA (ACB) Perfrming ADA 01000 (A) 0200 (F) = 1 yields Timing: 2 ADD WTH CARRY TO A (ADD WTH CARRY TO B) 61(21) 5 6 7 8 9 ]] SCA subtracts the cntent f the effective memry lcatin frm the cntents f the A Register, then subtracts the cntent f F frm the least significant end f the difference and places the result in A. t places the carry frm bit 0 in the Flag (F) bit. [(M) +F > (A) sets Fi (A)~(M)+FresetsF.] Registers Affected: A(B), F Timing: 2 MPA (MPB) 76(36) MEMORY PLUS A TO MEMORY (MEMORY PLUS B TO MEMORY) 5 6 7 8 9 11 MPA adds the cntents f the effective memry lcatin t the cntents f A and places the result in the effective memry lcatin; it stres the carry frm bit 0 in the Flag Bit. Registers Affected: M, F Timing: 3 63(23) MPO MEMORY PLUS ONE TO MEMORY 5 6 7 8 9 11 ACA adds the cntents f the effective memry lcatin t the cntents f Ai it als adds the cntent f the Flag Bit t bit psitin 11 f the result. ACA places the final result in Aand recrds the carry frm bit 0 in the Flag Bit. Registers Affected: A(B), F Timing: 2 16 56789 11 MPO increments the cntents f the effective memry lcatin by ne and places the result back int the same lcatin; it places the carry bit frm bit 0 in the Flag Bit. Registers Affected: M, F Timing: 3 2-2

MPF MEMORY PLUS FLAG TO MEMORY Exampl e: Assume (A) = 0027 (B) = 4335 (1000) = 0036 234 5 6 7 8 9 10 11 MPF adds the cntent f the Flag Bit t the cntents f the effective memry lcatin at bit psitin 11 and places the result back int the effective lcatin. The carry frm bit f the additin ges int the Flag Bit. Registers Affected: M, F Timing: 3 PerfrmingDVA01000 (B) = 6217 (A) = 0033 yields The div is in is perfrmed as fllws: B A MUA MULTPLY A (Optinal) 13 Y / 5 6 7 8 9 11 MUA multiplies the cntents f A by the cntents f the effective memry lcatin and places the prduct in A and B with the mre significant prtin in A. Registers Affected:. A, B Example: Assume (A) = 3411 (1000) = 0220 Timing: 5 1000 0 1 0 1 3 1 6 1 J 0 0 1217 H * 151 LOGCAL NSTRUCTONS ANA (ANB) AND TO A (AND TO B) 65(25) A B 5 6 7 8 9 11 ANA perfrms a lgical AND with the cntents f the A Register and the cntents f the effective memry lcatin; it places the result in A. The previus cntents f A are lst. Perfrming MUA 01000 (A) = 0077 (B) = 2420 yields Registers Affected: A, (B) Timing: 2 MUB MULTPLY B (Optinal) ORA (ORB) OR TO A (OR TO B) 53 56789 11 MUB multiplies the cntents f B by the cntents f the effective memry lcatin and places the prduct in A and B with the mre significant prtin in A. Registers Affected: A, B DVA(DVB) 52(12) DVDE AB (DVDE BA) (Optinal) 5 6 7 8 9 11 Timing: 5 DVA(DVB) divides the cntents f the A and B Registers (B and A Registers) treated as a duble-precisin number by the cntents f the effective memry lcatin and places the qutient in the B Register with the remainder in the A Register. The A Register (B Register) must initially cntain the mre significant half f the dividend. The cntents f the effective memry lcatin must be greater than the cntents f A (B). Registers Affected: A, B Timing: 13 67(27) 5 6 7 8 9 11 ORA perfrms a lgical "inclusive OR with the cntents f the A Register and the cntents f the effective memry lcatin; it places the result in A. The previus cntents f A are lst. Registers Affected: A, (B) Timing: 2 EOA (EO B) EXCLUSVE OR TO A (EXCLUSVE OR TO B) 66(26) 56789 11 EOA perfrms a lgical "exclusive OR with the cntents f the A Register and the cntents f the effective memry lcatin; it places the result in A. The previus cntents f A are lst. Registers Affected: A, (B) Timing: 2 2-3

MAA(MAB) 75(35) t MEMORY AND A TO MEMORY (MEMORY AND B TO MEMORY) 5 6 7 8 9 MAA perfrms a lgical AND with the cntents f the A Register and the cntents f the effective memry lcatin; it places the result in the effective memry lcatin. The previus cntents f the memry lcatin are lst; MAA leaves the cntents f A undisturbed. Y 11 BRANCH NSTRUCTONS BRU 73 BRANCH UNCONDTONALLY 5 6 7 8 9 11 The cmputer takes the next instructin frm the lcatin determined by the effective address. BRU cannt be interrupted. Registers Affected: Nne Timing: 1 Registers Affected: M Timing: 3 COMPARSON NSTRUCTONS COA(COB) COMPARE ONES WTH A (COMPARE ONES WTH B) BRC 32 BRANCH, CLEAR NTERRUPT AND'LOAD FLAG 5 6 7 8 9 11 45(05) 56789 11 COA cmpares the cntents f the A Register, bit by bit, with the cntents f the effective memry lcatin. f the cntents f A and the cntents f the effective lcatin have any nes in crrespnding bit psitins, COA resets the Flag Bit. f there is n such crrespnding pair f ne bits, COA sets the Flag Bit. The cmputer takes the next instructin frm the lcatin determined by the effective address; it als clears the currently active interrupt level. f BRC uses direct addressing, it clears the Flag Bit and sets the PCT bit. f it uses indirect addressing, BRC places int the Flag Bit and PCT bit the cntent f bits 0 and 1 f the first wrd f the last indirect address pair. Registers' Affected: F, PCT BRL BRANCH AND LOAD FLAG Timing: 3 Registers Affected: F Timing: 2 'CMA(CMB) COMPARE MAGNTUDE OF M WTH A (COMPARE MAGNTUDE OF M WTH B) 33 56789 11 47(07) 5 6 7 8 9 11 f the cntents f the A Register are arithmetically less than the cntents f the effective memry lcatin, CMA resets the Flag Bit. Otherwise, it sets the Flag Bit. BRL transfers t the effective memry lcatin. f BRL uses direct addressing, it clears the Flag Bit and sets the PCT bit. f it uses indirect addressing, BRL places int the Flag Bit and the PCT bit the cntent f bits 0 and 1 f the first wrd f the last indirect address pair. BRL cannt be interrupted. Registers Affected: F, PCT Timing: Registers Affected: F Timing: 2 BFF BRANCH ON FLAG FALSE CEA(CEB) 46(06) COMPARE M EQUAL TO A (COMPARE M EQUAL TO B) 56789 11 f the cntents f the A Register are equa t the cntents f the effective memry lcatin, CEA resets the Flag Bit. Otherwise, it sets the Flag Bit. Registers Affected: F Timing: 2 31 5 6 7 8 9 11 f the cntent f the Flag Bit is zer, the cmputer takes the next instructin frm the lcatin determined by the effective address. f the cntent is ne, the ~mputer executes the next instructin in sequence. f a branch ccurs, there can be n interrupt. Registers Affected: Nne Timing: 1 if Branch 2 if N Branch 2-4

BFT BRANCH ON FLAG TRUE BMC BRANCH, MARK PLACE, AND CLEAR FLAG 71 5 6 7 8 9 11 37 5 6 7 8 9 y 11 f the cntent f the Flag Bit is ne, the cmputer takes the next instructin frm the lcatin determined by the effective address. f the cntent is zer, the cmputer executes the next instructin in sequence. f a branch ccurs, there can be n interrupt. Registers Affected: Nne Timing: 1 if Branch 2 if N Branch BOA 70 BRANCH ON DECREMENTNG A 56789 11 BOA decrements the cntents f the A Register by ne. t then tests the result unequal t 7777 8, f unequal, the cmputer takes the next instructin frm the lcatin determined by the effective address. f equa, the cmputer executes the next instructin in sequence. t f a branch ccurs, there can be n interrupt. f this instructin specifies indexing, the indexing is perfrmed befre A (the index register) is decremented. Registers Affected: A Timing: 1 if Branch 2 if N Branch BAX 30 BRANCH AND EXCHANGE A AND B 2 3 4 5 6 7 8 9 10 11 BAX exchanges the cntents f A with the cntents f B; then it branches t the lcatin determined by the effective memry address. BAX cannt be interrupted. f this instructin specifies indexing, the indexing wi be perfrmed befre the interchange f A and lib. Registers Affected: A, B BRM 77 BRANCH AND MARK PLACE 5 6 7 8 9 11 Timing: 1 BRM stres the cntents f the Prgram Cunter (which cntains the address f the next instructin in sequence) in bits 9 thrugh 11 f the effective memry lcatin and bitso thrugh 11 f the effective lcatin plusne. t stres the cntent f the Flag Bit in bit 0 and the cntent f the PCT bit in bit 1 f the effective lcatin; bits 2 thrugh 5 f the effective lcatin are unpredictable. Bits 6 thrugh 8 f the effective lcatin are cleared. BRM then branches t the effective memry lcatin plus tw. mmediate addressing is nt allwed. Registers Affected: M, M+ 1 Timing: 3 tas with any instructin, when using immediate addressing with a BOA, the phrase lithe next instructin in sequence refers t the instructin tw lcatins beynd the BOA. BMC stres the cntents fthe Prgram Cunter in bits 9 thrugh 11 f the effective memry lcatin and bits 0 thrugh 11 f the effec.. tive lcatin plus ne. t stres the cntents f the Flag Bit in bit 0 and the cntents f the PCT bit in bi t 1 f the effective lcatin; bits 2 thrugh 5 f the effective lcatin are unpredictable. Bits 6 thrugh 8 f the effective lcatin are cleared. The Flag Bit is cleared and the PCTbit isset. BMCthen branches t the effective memry lcatin plus tw. mmediate addressing is nt allwed. Registers Affected: M, M + 1, F, PCT Timing: 3 Nte that the BMC instructin is the ne nrmally executed when an interrupt ccurs. The add ress stred in th i s case is the lcatin f the next instructin t be executed in the main prgram. SHFT NSTRUCTONS Shift instructins perate n. the A, B, and Flag Registers. The shifts can be single r duble register. All sh ifts are t the left. The number f shifts N is specified in the least significant 4 bits f the effective address. The maximum number f shifts is 15 (178); zer is allwed. N is written in the 4 bits, in nels cmplement frm (i.e., a shift N =7 appears as 10 ), 8 The single r duble shift is determined via bit 7 f the effective address; it is a 0 fr single-register shift and a 1 fr dubleregister shift. The cnventinal address frmats are: One-Wrd Address Tw-Wrd Address Opcde 0=1 lis Cmplef 11 Shift Timing Shift Cunt (Decimal) 0-3 4-6 7-9 10-12 13-15 11 Timing (Cycles) 3 4 5 6 7 2-5

CYA(CYB) CYCLE A (CYCLE B) CF CYCLE FLAG AND DOUBLE NVERSE 42 (02) 56 7 8 9 11 CYA shifts the cntents f the A Register N places t the left. All bits shifting past psitin 0 shift int psitin 11. The ne's cmplement f N, the number f psitins t be shifted, is placed in the least significant 4 bits f the effective address. Registers Affected: A(B) d A(B) b CFA(CFB) CYCLE FLAG AND A (CYCLE FLAG AND B) 3 5 6 7 8 9 11 CF shifts the cntents f the B and A Registers and the F lag Bit, taken as a single 25-bit register, N places t the left. Bits shift frm psitin 0 f A int psitin 11 f B, frm psitin f B int the Flag Bit, and frm the Flag Bit int psitin 11 f A. The ne's cmplement f N is placed in the least significant 4 bits f the effective address. Registers Affected: A, B,F CONTROL NSTRUCTONS r0j_b ---,H,--_A -----h 43 (03) EXU EXECUTE 11 CFA shifts the cntents f the A Registerand the Flag Bit, taken as a single 13-bit register, N places t the left. All bits shifting past psitin 0 shift int the Flag Bit, bits frm the Flag Bit g int psitin 11. The ne's cmplement f N is placed in the least significant 4 bits f the effective address. Registers Affected: A(B), F reh A(B) b CYD CYCliDOUBli 02 r 42 56 7 8 9 11 5 [ X y CYD shifts the cntents f the A and B Registers N places t the left. All bits shifting ut f psitin 0 f A shift int psitin 11 f B; all bits shifting ut f psitin 0 f B shift int psitin 11 f A. The ne's cmplement f N is placed in the least significant 4 bits f the effective address. Registers Affected: A, B A H... _B_h CFD CYCLE FLAG AND DOUBLE 4 3 11 CFD shifts the cntents f the A and B Registers and the Flag Bit, taken as a single 25-bit register, N places t the left. Bits shift frm psitin 0 f B int psitin 11 f A, frm psitin 0 f A int the Flag Bit, and frm the Flag Bit int psitin 11 f B. The ne's cmplement f N is placed in the least significant 4 bits f the effective address. Registers Affected: A, B, F r0j,---a ---,H,--_B -b 72 5 6 7 8 9 11 EXU executes the instructin in the effective memry lcatin. Then the cmputer executes the next instructin fllwing EXU. f the effective memry lcatin cntains a branch, cntrl ges t the branch-t lcatin. f the effective lcatin cntains anther EXU, the prcess repeats with cntrl always returning t the next lcatin after the first EXU r t the branch-t 10-' catin if the last instructin is a branch instructin. mmediate addressing is nt allwed n EXU (this restrictin des nt apply t the instructin executed}. N "trappable" instructin that wi trap can be executed. Registers Affected: Nne HLT 00 HALT One Wrd 5 6 41 2 3 5 6 8 9 11 Timing: 11 1 + time f instructin executin HLT halts instructin executin and lights the HALT light. T resume cmputatin, the peratr sets the mde switch t DLE and then t RUN r STEP at which time the cmputer executes the instructin in the lcatin addressed by the cntents f the Prgram Cunter. (This wi be the instructin fllwing the ti LT instructin if the peratr has nt changed the cntents f the Prgram Cunter. ) f an interrupt ccurs while halted by a HALT (while still in RUN), the cmputer acknwledges the interrupt and cmputatin resumes. (The instructin fllwing the HLT instructin will be executed fllwing the prcessing f the interrupt.) Registers Affected: Nne Timing: 3,4 2-6

TRAPPNG NSTRUCTONS SCT 00 SET PROGRAM-CONTROLLED TRAP 5 6 SCT uncnditinally sets the PCT bit t a ne. SCT cannt be interrupted. 61 11 TCT 01 TEST PROGRAM-CONTROLLED TRAP TCT tests the status f the PCT bit. f PCT is a ne, it sets the Flag Bit t a ne. f PCT is a zer, it sets the Flag Bit t a zer. Registers Affected: F Timing: 3,4 60 11 Registers Affected: PCT Timing: 3,4 BREAKPONT TESTS RCT RESET PROGRAM-CONTROLLED TRAP 00 )6 60 RCT uncnditinally sets the PCT bit t a zer. RCT cannt be interrupted. 11 This instructin tests the status f the Breakpint switches. f the selected switch is set, the Flag Bit is set t a 1. f the switch is reset, the Flag is set ta O. Mnemnic BPT 1 BPT2 BPT 3 BPT 4 Cding 0144 0145 0146 0147 Registers Affected: PCT Timing: 3,4 Regi sters Affected: F Timing: 3,4 2-7

. NPUT/OUTPUT NSTRUCTONS NTRODUCTON The SDS 92 has a cmprehensive input/utput system t cmplement its high internal prcessing speed. This system can transmit data in wrd, character, and single-bit frm t and frm the cmputer at the speed f internal cmputatin. The input/ utput system is f great variety and can assume cntrl f cnditins impsed by a wide range f input/utput j special system devices; but the cmputer always leaves a high degree f flexible input/utput cntrl t the prgrammer. Central Prcessr Memry The system cntains: Buffered input/utput f data wrds, under prgram cn. trl in blcks r as single wrds. nput/utput f blcks f data via subchannels; up t 64 channels simultaneusly perating thrugh a multiplexing system (ptinal). Direct parallel input/utput f 12-bit wrds, singly r in blcks, t and frm external static registers. WOT causes a wrd t be taken frm the specified memry lcatin and placed in the /O Channel t be utput when requested by the currently active peripheral device. Single bit input/utput, such as equipment n/ff status, sense switches, and pulsing and sending f special signals. /O CHANNEl Central Prcessr Memry The /O Channel, standard equipment in the cmputer, perfrms input/utput f wrds singly r in blcks. On utput, the /O channel transmits wrds in 6-bit characters, ne r tw characters per wrd as selected, r in 12-bit (ptinal) single character frm. On input, the /O channel receives wrds in 6-bit characters, ne r tw per wrd, r 12-bit (ptinal) characters as desired. This channel transmits single wrds r blcks. The prgram places the blck cunt in the A Register prir t the transfer and the cmputer cunts this dwn t 7777 autmatically t terminate the transfer peratin. SNGLE WORD TRANSMSSON Using the /O Channel, a prgrdm can transmit data wrds between memry and peripheral devices under single instructin cntrl. T d this, the prgram first activates the channel and the peripheral device with an energize r "alert" instructin (ne f the cnfiguratins f the multi -purpse instructin, ENERGZE OUTPUT M (EOM)). WOT is the WORD OUT instructin; WN is the WORD N instructi.n. WN causes a wrd frm a peripheral device t be taken frm the /O channel and placed directly int the specified memry lcatin with.ut disturbing any internal registers.. T transfer blcks f data wrds via the /O channel, the prgram uses the same EOM cnfiguratin t set the channel fr peratin; the prgram specifies the number f wrds in the transfer.by placing the wrd cunt minus ne in the A Register ((A) + 1 = N). The RECORD OUT (ROT) instructin causes the cmputer t utput wrds frm the effective address M thrugh the effective address plus the cntents f A (M thrugh M + (A)). The RECORD N (RN) instructin causes the cmputer t input frm the actively transmitting peripheral device; the peratin terminates when the cmputer receives N wrds, r when it receives an "end-f-recrd" frm the peripheral device. RN and ROT tie up the cmputer during the entire input/utput transmissin. 3-1

Central Prcessr Memry Fr a PN, EOM alerts the sending device, PN stres the least significant 12 bits, the high-rder bits fill the extender, EOM a erts the extender, and anther PN stres the cntents f the extender. Ne i ther f these cd i ng sequences can be interrupted. See the nterrupt System paragraphs fr the Alert Extender EOM fr bth POT and PN. (A) = N-1 N-1 SNGLE BT NPUT/OUTPUT The EOM and SES instructin prvide a general single bit transmitting and sensing facility fr use as test and cntrl signals with special systems and standard peripheral devices. DATA TRANSFER NSTRUCTONS Figure 3-1. ROT/RN Data Transmissin Tw instructins cntrl the prcess f transmitting and receiving data-between peripheral equipment and the central prces \ sr using the /O Channel. These instructins are: EOM S-ES ENERGZE OUTPUT M SENSE EXTERNAL SGNAL The EOM instructi n activates the /O Channel, selects the peripheral device, and requests the desired peratin. The prgrammer uses the SES instructin t test fr all input/utputperatinal cnditins; SES is multipurpse like the EOM. Later sectins describe the exact cnfiguratins f EOM and SES. DRECT PARALLEL NPUT/OUTPUT, 12 BT The parallel input/utput facility allws full, 12-bit wrds t be transmitted directly ut f and int the memry. After activating the peripheral device r special system device with an activating EOM, the PARALLEL OUTPUT (POT) and PARALLEL NPUT (PN) cause any selected wrd in cre memry t be presented t the peripheral device cnnectr; r cnversely, cause a wrd (12-bit signa ) received int the device cnnectr t be stred in the selected lcatin. POT/PN als check r generate crrect memry parity with each wrd transmitted. The system prvides a blck transfer frm f POT and PN with the instructins, BLOCK PARALLEL N (BP) and BLOCK PAR ALLEL OUT (BPO). By placing the wrd cunt N minus ne in the A Register, BP and BPO prvide the identical functin f PN and POT, respectively, n N cnsecutive wrds. Parity checking/generating is autmatic fr these peratins n machines equipped with the memry parity feature. N interrupt can ccur between any f these instructins and the instructin fllwing it. WOT WORD OUT 5 6 7 8 9 11 WOT transfers the cntents f the effective memry lcatin int the /O channel buffer. f the buffer is nt ready, the central prcessr hangs Upll unti the buffer empties frm a previus instructin and is ready t accept the new data wrd. Registers Affected: Nne ROT 51 RECORD OUT 5 6 7 8 9 Timi ng: 4 + wait Starting with the effective memry lcatin, ROT transfers N sequential wrds int the /O channel buffer. The cntents f the A Register are the wrd cunt N minlfs ne; ROT can utput t 4096 wrds per executin. The central prcessr must wait as with WOT befre it transfers the first wrd t the buffer; it als must wait fr the buffer t clear between each wrd transfer. ROT cmpletely ties up the cmputer until the Nth wrd transfers int the channel buffer. The next instructin executes befre the Nth wrd transfers ut f the channel buffer t the cnnected peripheral device. Registers Affected: A WN WORD N 11 Timing: 2 + 2N + wait See POT/BPO, PN/BP nstructins in this sectin. DRECT PARALLEL NPUT/OUTPUT, 24-BT (Optinal) 15 5 6 7 8 9 11 A 12-bit register is available t extend the wrd fr POT/PN peratins t 24 bits. Fr a POT, the device perates as fllws: EOM t activate the extender, POT t place the mst significant 12 bits in the extender, EOM t activate the externa device t get the data, and POT t transmit the lwer -12 bits. This last POT transmits the entire 24 bits. WN transfers the cntents f the channel buffer int the effective memry lcatin. f the buffer is nt already fi lied, the central prcessr hangs Upll unti the buffer fi lis with the wrd being received frm the peripheral device. Registers Affected: M Timing: 5 + wait 3-2

RN 55 RECORD N 5 6 7 8 9 11 Starting with the effective memry lcatin, RN transfers N wrds frm the channel buffer int sequential lcatins. The cntents f the A Registerare the wrd cunt N minus ne; RN can input up t 4096 wrds per executin. The centra prcessr must wait as with WN befre it receives the first wrd frm the channel buffer; it als must wait fr the buffer t fill between each wrd transfer. RN cmpletely ties up the cmputer until the Nth wrd is in memry. This input will als terminate if the cmputer receives an END signal frm the peripheral device befre the Nth wrd. n either case, the cmputer executes the next instructin after RN terminates. Registers Affected: M t M + (A), A / CHANNEL OPERATON Timing: 3 + 2N + wait The /O Channel can cntrl up t 30 input/utput devices; it autmatically handles character, wrd assembly/disassembly, and input/utput parity detectin and generatin. The channel is bi-directinal and cmmunicates with 6-bit character devices (12-bit ptinal). The prgram specifies whether ne r tw characters are t be assembled/disassembled in each wrd during the transmissin. The prgram uses a Buffer Cntrl EOM t set the peratin cntrls such as frward/backward tape directin, t place the unit address in the channel, and t initiate the prper assembly/disassembly mde. The presence f the unit address activates the channel causing it t lk fr data cming frm a peripheral device r frm memry, as determined by the unit address (see the Unit Address Cde, Table 3-1). T get data frm the channel buffer after it is received there frm a peripheral device during input, the prgram uses a WORD N (WN) instructin, r its blck transfer equivalent, r----------------------------- T /O Device : ~~~~~J ~ L RN. T place data int the channel buffer s that the channel can transmit it t the waiting peripheral device, the prgram uses WORD OUT (WOT), r its blck transfer equivalent, ROT. /O CHANNEL BUFFER DESCRPTON (See Figure 3-2.) During the executin f ROT/RN, the cmputer is cmpletely tied up whi e it handles the data transfers, increments the memry lcatin address fr the data transfers, and tests fr transfer terminatin using the wrd cunt N (by decrementing A by ne whenever a wrd is transferred). Each f the 30 devices which can be attached t a buffer has a unique, tw-digit, ctal address by which it is chsen fr an input/utput peratin. T chse the peripheral device, the prgram lads the prper unit address int the 6-bit Un it Address Register (UAR). This address selects bth thedeviceand, if apprpriate, the functin t be perfrmed. Placing a nn-zer unit address in the Unit Address Register "cnnects" the peripheral unit addressed t the buffer and the buffer becmes "active tl When the UAR cntains a zer address, r any time that a terminal r initial cnditin clears the cntents f UAR, the buffer is "inactive", and it is nt cnnected t a peripheral unit. The Wrd Assembly Register (WAR) and the Single Character Register (SCR) cmprise the active prtin f a buffer. The Wrd Assembly Register, a 12-bit, wrd~sized buffer, cntains the wrd f data actively being received r transmitted during an input r utput peratin. During input, 6-bit characters (plus parity) cme int the Single Character Register where the channel assembles them, ne at a time, int the WAR. Depending n the number f characters per wrd specified, the wrd assembled during input has the frm: Parity Wrd Mde One character 1 st Unpredictable per wrd 5 6 11 1st Errr Character Cunt E1 Wrd Assembly '-- ~ ~ 5 6 11-0- Figure 3-2. SDS 92 Channel Buffer J6 2nd 11 Tw characters per wrd ----------, 5 _J 3-3

Table 3-l. Unit Address Cdes 00 Discnnect 40 01 Type nput N. 1 41 Type Output N. 1 02 Type nput N.2 42 Type Output N.2 03 Type nput N.3 43 Type Output N.3 04 Paper Tape nput N. 44 Paper Tape Punch Output N. 05 Paper Tape nput N.2 45 Paper Tape Punch Output N.2 06 Card Reader nput N. 1 46 Card Punch Output N. 1 07 Card Reader nput N.2 47 Card Punch Output N.2 10 Magnetic Tape nput N. 0 50 Magnetic Tape Output N. 0 11 Magnetic Tape nput N.1 51 Magnetic Tape Output N.1 12 Magnetic Tape nput N.2 52 Magnetic Tape Output N.2 13 Magnetic Tape nput N.3 53 Magnetic Tape Output N.3 14 Magnetic Tape nput N.4 54 Magnetic Tape Output N.4 15 Magnetic Tape nput N.5 55 Magnetic Tape Output N.5 16 Magnetic Tape nput N.6 56 Magnetic Tape Output N.6 17 Magnetic Tape nput N.7 57 Magnetic Tape Output N.7 20 60 High-Speed Printer Output N. 21 61 High-Speed Printer Output N.2 22 62 23 63 24 64 ncremental Pltter Output N. 25 65 ncremental Pltter Output N.2 26 Disc File nput N. 66 Disc File Output N. 1 27 Disc File nput N.2 67 Disc File Output N.2 30 Scan Magnetic Tape N. 0 70 Magnetic Tape Erase N. 0 31 Scan Magnetic Tape N.1 71 Magnetic Tape Erase N.1 32 Scan Magnetic Tape N.2 72 Magnetic Tape Erase N.2 33 Scan Magnetic Tape N.3 73 Magnetic Tape Erase N.3 34 Scan Magnetic Tape N.4 74 Magnetic Tape Erase N.4 35 Scan Magnetic Tape N._5 75 Magnetic Tape Erase N.5 36 Scan Magnetic Tape N.6 76 Magnetic Tape Erase N.6 37 Scan Magnetic Tape N.7 77 Magnetic Tape Erase N.7 3-4

An unfi lied character psitin is unpredictable. When assembled during a single-wrd peratin, a WN instructin places the wrd int memry. With RN, the cmputer places each wrd in memry when assembled. During utput, wrds cme frm memry int the WAR where the channel disassembles them int the SCR, ne 6-bit character at a time. Depending n the characters per wrd mde specified, the channel transmits the 6-bit characters (with generated parity) as fllws: Functin Output ne character frm bits thrugh 5 Mde One character per wrd The Buffer Cntrl EOM perates essentially as a setup r preparatin facility fr data transmissins r ther peripheral functins using the /O Channel. The nput/output Cntrl EOM directs peripheral devices directly in such peratins as rewind tape and upspace the printer. EOM in the nternal Cntrl mde perfrms internal cntrl peratins such as activating the (ptinal) 24-bit PN/POT extender lgic. The System EOM is specifically cncerned with special systems; the system determines the particular uses. EOM in any f the last three mdes als can alert a device fr a POT r PN type peratin. NOTE: f an interrupt ccurs during the executin f an EOM, n acknwledgement ccurs until the cmpletin f the executin f the instructin fllwing the EOM. Output tw characters frm bits thrugh 5, 6 thrugh 11 Tw characters per wrd Registers Affected: Nne Timing: 3,4 After the first character transfer, the wrd in the WAR shifts left six bits t be ready fr the next transfer, when tw characters frm each wrd are used. Under ROT cntrl, a new wrd cntail")ing the next characterls) cmes t the WAR when it is required. (OM NSTRUCTONS (pcde 00) BUFFER CONTROL EOM (effective address) U N T 2 3 4 5 6 7 8 9 10 11 1213 14 Designatin Functin BASC CONFGURATON The EOM instructin is a multipurpse instructin that perates in fur distinct mdes with many functinal cnfiguratins. The mdes are Buffer Cntrl, nput/output Cntrl, nternal Functin Cntrl, and System Cntrl. EOM ENERGZE OUTPUT M nstructin Wrd 234 5 6 7 8 9 10 11 Effective Address! \ 2 3 4 5 6 7 8 9 10 11 12 13 14 The EOM uses the 15 bit cnfiguratins f the effective memry address asa cntrl wrd t select the different cntrl mdes and tselectall additinal cntrl functins. EOM allws a addressing mdes in btaining the effective address. Setting the tw bits (1, 2) in the address determines the mde f the EOM: 2 Cntrl Mde 0 0 Buffer 0 1 nput/output 0 nternal System /N 00 F/R L/N D/B C/W UNT Bit psitin 0 specifies nterlace peratin. A "0" specifies n nterlace peratin. A "1" alerts the nterlace. Bit psitins 1 and 2 cntain the EOM mde indicatr fr the Buffer Cntrl mde. Bit psitin 3 specifies the directin in which the peripheral device perates. A "0" specifies the frward directin. A "1" specifies the reverse directin. Bit psitin 4 specifies whether the device shuld be started with a leader as in paper tape. A "0" specifies a start with leader. A "1" specifies a start withut leader. Bit psitin 5 specifies the mde f character frmat. A "0" specifies BCD frmat. A "1" specifies Binary frmat. When this is nt apprpriate,,bit 5 prvides special cntrl. Bit psitin 6 is unassigned. ' Bit psitin 7 specifies the number f characters t be assembled int, rdisassembled frm, each transmitted wrd. 0 specifies ne character per wrd, 1 specifies tw. One character per wrd, 0, is used fr full-wrd (12-bit characters) transmissin (ptinal). Bit psitin 8 must always be 1. Bit psitins 9 thrugh 14 specify the unit and the functin t be perfrmed with that unit. 3-5

NPUT/OUTPUT CONTROL EOM (effective address) UN T 01 2 345 6 789 10 111 12 ' 13 14 YNl 1 FUN CT ON 11 Designatin /N 01 FUNCTON UNT Functin Bit 0 specifies nterlace peratin. A "0" specifies n nterlace. A "" alerts the nterlace. Bits 1, 2 specify the nput/output Cntrl mde. Bits 3 thrugh 7 specify cntrl peculiar t each device. Bit 8 must be l. Bits 9 thrugh 14 cntain the Unit Address f the specified device. A Unit Address f 00 refers t the / Channel itself. STANDARD EOM NSTRUCTONS These EOM effective address cnfiguratins have standard uses. DSC DSCONNECT CHANNEL 10 13 14 DSC discnnects the / Channel. This instructin uncnditinally sets the UNT Address Register t 00 regardless f whether the channel is currently addressing a device. DSC discnnects any device cnnected t the channel; it uncnditinally makes the channel inactive and clears the errr indicatr. Registers Affected: Nne Timing: 3, 4 TOP TERMNATE OUTPUT ON THE CHANNEL 10 11'12 13 14 During utput when the last wrd f a blck ges t the channel, TOP terminates utput. After executin f TOP, the fllwing ccurs. When the channel del ivers the last character t the peripheral device, the channel discnnects. TOP must always terminate a channel utput peratin. Registers Affected: Nne Timing: 3, 4 TP TERMNATE NPUT ON THE CHANNEL 10 13 14 During input when the last (desired) wrd has been stred in memry, T P term i nates input. TP r DSC shuld always terminate a channel input peratin. Registers Affected: Nne Timing: 3, 4 After TP isgiven during an input peratin, the fllwing ccurs: 1. The / channel receives any further characters frm the input device - as befre. 2. All errr checks are perfrmed - as befre. 3. Hwever, the Wrd Assembly Register is never again cnsidered "full". This means: a. nterlace peratins stre n mre wrds. b. Nn-interlace peratins give n mre End-f-Wrd (11) nterrupts. 4. The abve "scanning-type" sequence cntinues until the End-f-Recrd at which time: a. The End-f-Recrd (12) nterrupt is sent (if armed). b. The channel discnnects. c. The channel becmes inactive. ASC ALERT TO STORE NTERLACE COUNT 5 4 7 10 13 14 ASC alerts the interlace ptin that the PN t fllw is a request fr the cntents f the current COUNT cntents. The sequence: ASC PN stres the current cntents f the COUNT register int lcatin M. See nterlace Optin, this sectin. NOTE: The abve sequence must be cnsecutive; n ther instructin shuld be interpsed. Registers Affected: Nne SES NSTRUCTONS (pcde 01) BASC CONFGURA non Timing: 3, 4 The SES is a multipurpse test instructin used fr testing respnses t the input/utput channel and attached peripheral devices as well as fr testing internal and external indicatrs. SES SENSE EXTERNAL SGNAL nstructin Wrd i i 5 1 6 7 8 19 111 12 13 14 2 3 4 10 Effective Address 0 0 s\x! 2 3 4 5 6 7 8 9 10 11 Like the EOM, the SES uses the bit cnfiguratin f the effective address t select the different tests and als perates in fur mdes that are selected by address bits 1 and 2: 1 1.. Test Mde 0 0 Buffer 0 1 nput/output 1 0 nternal 1 1 System When executed, an SES tests fr a specified cnditin and sets r resets the Flag Bit in respnse t the cnditin. The prgram determines the Flag Bit status via ne f the branch-nflag instructins. SES allws all addressing mdes in btaining the effective address. The Buffer and nput/output Test SESs are the cmplement f the Buffer and nput/output Cntrl EOMs; they sense 3-6

the cnditins f the / Channel and its cnnected peripheral devices. NPUT/OUTPUT TEST SES (effective address) YN 0 1 CO N D 11 UNT 1 2 3 4 5 1 6 7 8 9 10 11'12 13 14 Designatin /N 01 COND UNT Functin Bit 0 specifies nterlace peratin. A "0" specifies n nterlace. A "1" alerts the nterlace. Bits 1 and 2 specify the nput/output Test mde. Bits 3 thrugh 7 specify cnditins t be sensed. Bit 8 must be 1. Bits 9 thrugh 14 cntain the Unit Address f the specified device. STANDARD BUFFER SES NSTRUCTONS (effective address) CAT 4 CHANNEL ACTVE TEST; SET FLAG F NOT ACTVE 2 1 34 5 1 6 7 8'9 13 14 f the channel is ready t accept a new input/utput instructin, CAT sets the Flag Bit. f the channel is active, CAT resets the Flag Bit. (The channel wi test active during an input peratineven after the peripheral has terminated its peratin - until all meaningful data wrds in the character buffer have been stred in memry.) Registers Affected: F Timing: 3,4 CET CHANNEL ERROR TEST; SET FLAG F ERROR 10 11112 13 14 CET tests the errr indicatr in the /O Channel fr being set. f set t n errr, CET resets the Flag Bit. f set t errr, CET sets the F lag Bit. Registers Affected: F Timing: 3,4 NTERLACE The /O Channel interlace is an ptinal hardware device that can cntrl and perfrm input/utput peratins independent f, and simu taneus with, central prcessr prgram executin. n using the interlace, the prgram sets up a starting address fr data in r ut, sets up a recrd length f the data t be read r written, and starts the interlaced peratin. The prgram then cntinues cmputatin while the interlace mnitrs the /O peratin, accessing memry when necessary, incrementing the data address as needed, and cunting the number f wrds in the recrd. Usually, when the cunt ges thrugh zer, the peratin is cmpleted and the prgram can use the newly entered data and/r can reset the nterlace fr anther independent, /O transm issin. The nterlace cntains tw registers: the 12-bit COU NT register t cntain the recrd cunt and the 15-bit ADDRESS reg ister t cnta in the data address. When lad ing the recrd cunt (N), the prgram places N-l (ne less than the recrd cunt) in the COUNT register. The prgram can use any /O r Buffer Cntrl EOM t "alert" the nterlace fr peratin. A l-bit in bit ps it ins 0 and 8 f the effective address generated by the EOM will alert the nterlace. The standard assembler frm fr alerting the nterlace is an asterisk (*) in the first clumn f the address f the EOM that activates the peripheral device in the /O transmissin. Fr example, t alert the nterlace while activating the magnetic tape unit number 1 t read tape decimal, ne culd write: RTD *1, 2 A special EOM t alert nly the nterlace, ALC ALERT CHANNEL NTERLACE has the address frm 50100; n 11*.. is needed. The PARALLEL OUTPUT (POT) instructin transmits the starting address and recrd cunt t the nterlace. The three POTs" that are needed functin as fllws (RTD * 1, 2 is used as the alerting EOM): RTD *1,2 POT HADDR POT LOWADDR POT NLESSONE (NOTE: This sequence must be cnsecutive; n ther instructins shu d be interpsed.) where: The least significant bits f the cntents f lcatin HADDR frm the high r mst significant three bits f the starting address, the cntents f lcatin LOWADDR frm the least significant 12 bits f the 15-bit starting address, and the cntents f NLESSONE are the recrd length minus ne (N-1). n each case, the POT transmits the infrmatin int the prper nterlace register. The terminatin f an interlace peratin can be determined by using a CAT, CHANNEL ACTVE TEST; r the prgress f an peratin may be mnitred thrugh the use f the ALERT TO STORE NTERLACE COU NT. ASC (10500) alerts the nterlace that a PN is t fllw t get a recrd f the current COU NT cntents. 3-7

The sequence: ASC PN M alerts the nterlace and PNs" the current cntents f the COU NT register int lcatin M. The cntents f COU NT are N-1 minus the number f wrds f the recrd already transm itted. /O CHANNEL NTERRUPTS OPTON Tw interrupts 11 and 12 are directly assciated with the /O channel. These are pririty interrupts with 11 having pririty ver 12. When 11 is requested, it interrupts each time the /O channel buffer empties r fi lis; that is, when requested it ccurs n input each time the buffer cllects a wrd, r it ccurs n utput each time the buffer transmits a cmplete wrd. When 12 is requested, it interrupts when an End-f-Recrd ccurs; that is, it interrupts nly after a cmplete recrd is input r utput. 11 and 12 are always enabled (as described in the nterrupt Paragraphs, nput/output Sectin f this manual). A special instructin, EOM 11XOO, arms/disarms these interrupts. The values f X are: X Functin Disarm 11 and 12 3 Arm 11, disarm 12 5 Arm 12, disarm 11 7 Arm 11 and 12 The instructin EOM 13XOO, as a terminate utput EOM, can be used effectively in cnjunctin with the arming feature. Fr "instance, EOM 13500 terminates utput, arms 12 and disarms 11. t functins like this: When the current utput frm the /O channel is finished and the Jl buffer is free, the 12 interrupt ccurs. The standard assembler mnemnic and instructin frm is: ARM where X is as described abve. X nterrupts Used with the nterlace Optin During nterlace peratin, the basic interrupts functin accrding t the names they are given belw: 11 is COU NT EQUAL 77778 12 is END OF RECORD When requested, 11 ccurs when COU NT ges thrugh zer. When requested, 12 ccurs when an End-f-Recrd ccurs. On utput r input: f 11 is nt armed, the nterlace terminates the channel (i. e., effects a~ autmatic TOP r TP) when the COU NT ges thrug h zer. Nte: During input, this means that the peripheral cntinues t the end-f-recrd, but n mre input wrds are stred in memry. f 11 is armed, the nterlace des nt terminate the channel n COUNT passing zer; instead an 11 interrupt is generated. This allws the prgram t re-initiate the COU NT and starting ADDRESS in the nterlace and cntinue perfrming the same / peratin. The Channel always discnnects when the endf-recrd ccurs with n regard t the interrupt arms. Nte: When armed by ARM X, an interrupt cnditin ccuring n 11 r 12 causes the interrupt level t g t the Waiting state. f the nterrupt System is Enabled, the respective interrupt will g t the Active state as its pririty perm its. f the nterrupt System is Disabled, the interrupt stays in the Waiting state indefinitely. POT/BPO, PN/BP NSTRUCTONS Tw instructins, PARALLEL OUTPUT (POT) and PARALLEL NPUT (PN), cause any wrd in cre memry t be presented in parallel at a cnnectr; r, inversely, cause signals sent t a cnnectr t be stred in any cre memry lcatin. The executin f a POT r PN instructin causes a signal t be sent t the external device invlved in the input/utput peratin. During a PN, this signal tells the device t send its data wrd as sn as it is peratinal. Wehn a device becmes peratinal duringareadrpn peratin, ittransmitsaready signal t the central prcessr while at the same time presenting its data wrd. The cmputer places the received data wrd int a specified memry lcatin withut disturbing any arithmetic registers. The cmputer hangs Up" during the executin f PN until it receives the Ready signal frm the external device. During the executinfa POT 'instructin, the central prcessr transmits a signal t the external device alerting it t receive a data wrd. When the device becmes peratinal, it transmits a Ready signal t the central prcessr which releases the data wrd t the external device. The cmputer hangs Up" during the executin f POT until it receives the Ready signal frm the external device. The blck transfers frms f these instructins are BLOCK PARALLEL NPUT (BP) and BLOCK PARALLEL OUTPUT (BPO). Special system requirements demand that cmplete wrds f cntrl r data infrmatin be transferred between the central prcessr and the special external devices. The PN r POT preceded by the activating EOM gives exactly this facil ity. The EOM alerts the system device by specific address and the PN r POT transfers the requ i red wrd. That is, the EOM activates andalertsthespecialdevice and the PN/POT transfers 12 bits t r frm the effective memry lcatin specified. T avid a psssible cmputer hang... up", the SES instructin can test the Ready signal f the specia device prir t the EOM and PN/ POT. f the Ready signal frm the external device sets ne f the pririty interrupts (ptinal), parallel input/utput peratin can ccur as sn as the external device is able t transmit r receive. Since the Ready signal initiating the interrupt persists thrugh the POT r PN executin, n hang-upll ccurs. N interrupt can ccur during the executin f, r between any f these instructins and the instructin fllwing it. 3-8

POT POT PARALLEL OUTPUT 4 5 6 7 8 9 10 11 POT transm its the cntents f the effective memry lcatin in parallel t 12 utput lines f an external device. Registers Affected: Nne BPO Y BLOCK PARALLEL OUTPUT 5 Y 4 5 6 7 8 9 10 11 Timing: 4 +.wait (h igh-speed) and 4,5 + wait Starting with the effective memry lcatin, BPO transfers the cntents f N sequential lcatins in parallel t 12 utput lines f an external device. The cntents f the A Register are the wrd cunt N minus ne; BPO can utput up t 4096 wrds per executin. The utput lines fi and empty under cntrl f BPO and the Ready signa. Registers Affected: A PN PARALLEL NPUT Timing: 3 + N + wait (high-speed) and 2,3 + 2N + wait Pin stres the cntents f 12 input ines in parallel in the effective memry lcatin. Registers Affected: M BP BLOCK PARALLEL NPUT 5 4 Y 4 5 6 7 8 9 10 11 Timing: 5 + wait (h igh-speed) and 5,6 + wait Starting with the effective memry lcatin, BP transfers N wrds frm the 12 input lines in parallel int sequential lcatins. The cntents f the A Register are the wrd cunt N minus ne; BP can input up t 4096 wrds per executin. The input lines fill and empty under the cntrl f the Ready signal and BP. Registers Affected: M t M + (A), A SNGLE BT NPUT/OUTPUT Timing: 4 + N + wait (h igh-speed) and 3,4+ 2N + wait Operating in the System mde, the tw instructins, ENERGZE OUTPUT M (EOM) and SENSE EXTERNAL SGNAL (SES), prvide single-bit input/utput transmissins. Executin f an EOM (System Mde) causes a 1.15-micrsecnd signal t be transmitted t ne f a pssible 4096 signal destinatins. The system EOM frmat is: SYSTEM MODE EOM (effective address) 3 012345 1 678 1 9 10 d 12 13 14 Bit psitins 0-2 cntain the System Mde ndicatr. Bit psitins 3 thrugh 14 cntain the address field that specifies the special system destinatins. Registers Affected: Nne Timing: 3,4 SYSTEM MODE SES (effective address) J 3 3 10 13 14 Executin f an SES (System Test Mde) causes an address t be presented t the cllectin f special system devices. f the addressed external device is supplying a set signal t the central prcessr, the Flag Bit is set. f there is n signal, the Flag Bit is reset. The SES System Test Frmat is identical t the System EOM Frmat. Timing is 3,4 cycles. /O TERMNATON PROGRAMMNG NOTES 1. There is a test t see whether the /O channel is ready t accept a new input/utput instructin - the CHANNEL ACTVE TEST (CAT). 2. Fllwing the terminatin f an input peratin by an Endf-Recrd, the channel remains active until all significant data wrds have been stred by the prgram r interlace. 3. Fllwing the terminatin f a nn-magnetic tape utput peratin by TERMNATE OUTPUT (TOP), the channel remains active unti the last cha racter has been del ivered t the peripheral device. 4. Fllwing the term inatin f a magnetic tape utput peratin by TOP, the channel remains active unti the magnetic tape un it cmmences stpping. Th is is lng after the last character has been del ivered t the magnetic tape un it. 5. The End-f-Recrd (12) nterrupt is never sent unti the /O channel becmes inactive. Thus, an input prgram (using End-f-Wrd, 11, nterrupts fr example) must take care t stre every input character presented t it by the /O channel (in ur example, every 11 nterrupt must result in a W Nil r "DSC" r "TP"). f nt, the input devicewill prceed t End-f-Recrd and stp, but n 12. nterrupt will ever be given and the channel will never g inactive. The prgrammer has several ptins after he has read as much f a recrd desired: " 1. Discnnect (DSC) - but nt if the peripheral device is a magnetic tape. 2. D nthing - but nly if n mre wrds remain in the recrd (i.e., the entire recrd has been read). 3. Give TP - the input peripheral device wi" cntinue t End-f-Recrd with all nrmal errr checks n the remainder f the recrd. 3-9

4. TERMNATE NPUT (TP) and TERMNATE OUTPUT (TOP) have the same ctal cnfiguratin - the /O channel differentiates TP and TOP accrding t the type f peratin it is perfrming. 5. The prgrammer can have n prblem by giving a TP when the input device is cncurrently sending an End-f-Recrd signal r when the channel is already inactive. 6. mprper prgramming (especially n input) can leave the /O channel in an active state. THE 11 NTERRUPT A nn-interlace, nn-character-interrupt /O prgram shuld disarm the 11 nterrupt. f this disarming is nt effected, spurius 11 nterrupts may result: 1. On utput, the first l nterrupt is generated immediately fllwing the activating EOM. 2. During ROT/RN (and WOTjWN), l nterrupts may be generated -even thugh the /O channel is being prperlyattended t by the ROT/RN cmmand. This disarming des nt create many prgramming prblems r cmpatibility prblems-the RESET buttn clears bth /O channel interrupt arms. Thus, nly prgrams which use bth the interrupt and the nn-interrupt mdes f /O prgramming need take heed. PRORTY NTERRUPT SYSTEM (Optinal) NTRODUCTON As an ptin, the SDS 92 may cntain a pririty interrupt system. This system prvides added prgram cntrl f input/ utput peratins, aids in prgramming multiplexed peratins, and'allws immediate recgnitin f special external cnditins. When an interrupt is received, the internal lgic examines the interrupt signal and causes the cmputer t interrupt the prgram sequence at the end f the executin cycle f the current instructin. Withut disturbing the Prgram Cunter Register, the cmputer transfers prgram cntrl t ne f a selected set f memry lcatins. One f the branch and mark place BRM r BMC instructins in this lcatin saves the cntents f the Prgram Cunter, Flag, and PCT. t als transfers t the particular interrupt servicing rutine required. This enters the prper service rutine since each interrupt has a unique interrupt lcatin. T exit frm the rutine, a BRANCH AND CLEAR NTERRUPT (BRC) instructin using indirect addressing returns cntrl t the next instructin in prper sequence in the main prgram; it als clears the interrupt and restres the riginal cntents f the Flag and PCT. The pririty interrupt system has up t 256 System interrupt levels. The levels, numbered evenly upward frm 200a, have pririty accrding t number, with the higher pririty levels having a smaller number. Additinal interrupts btained with SDS ptinal hardware are lcated at interrupt levels numbered frm 150a. n general, these als have pririty accrding t number. Nte that interrupts 150 thrugh 176 have pririty ver any System interrupt (200 r mre). When an interrupt has ccurred and its service subrutine has been entered, an interrupt f higher pririty can interrupt the subrutine and gain prgram cntrl fr the servicing f its mre imprtant peratin. But an interrupt f lwer pririty cannt interrupt an interrupt-prcessing subrutine f a higher level. Thus, the pririty interrupt system allws interrupts t be arranged accrding t their imprtance and/r accrding t their need fr speedy servicing. The abve type f interrupt is called a nrmal pririty interrupt t differentiate it frm anther interrupt feature, the singleinstructin interrupt. This is a different kind f interrupt that causes the executin f nly ne instructin befre autmaticallyclearing itself and returning t the prgram which it interrupted. f the executed instructin is a branch instructin which branches (i.e., BRM r BMC), the interrupt is cleared but cntrl des nt return t the interrupted rutine. Th is type f interrupt needs n branch instructin t clear it. Fr example, by cnnecting an external clck surce t the cmputer, the prgram can maintain a prgrammed real-time clck. Each time the external pulse causes an interrupt, the prgram executes the single instructin, MEMORY PLUS ONE TO MEMORY, t add ne t the selected memry wrd. The main prgram examines this lcatin whenever necessary t determine hw many time increments have elapsed since the clck was started. N new interrupt can ccur between any singleinstructin interrupt and the return t the main prgram. Any f the ptinal, system interrupts can be single- r nrmalinstructin interrupts in any cmbinatin desired. PRORTY NTERRUPT OPERATONS A nrmal pririty interrupt level has three peratinal states: nactive, Wai ting, and Active. n the inactive state, n interrupt signal has been received int the level and nne is currently being prcessed by its interrupt servicing subrutine. N recrd is maintained if the interrupt cannt g int the waiting state. n the waiting state, an interrupt request signal has been received int the level, but is nt being prcessed. This situatin may be due t an interrupt f higher pririty being prcessed at this time. When the system is enabled and all higher waiting interrupts have been prcessed, this level ges t the active state. n the active state, the interrupt has been acknwledged, meaning it has caused the main prgram t recgnize its presence and has transferred t its assigned interrupt lcatin and/r rutine where it is being prcessed. When the interrupt prcessing is cmpleted, executin f a BRANCH AND CLEAR (BRC) sets the interrupt level t the inactive state. A single-instructin interrupt perates in the same way as the nrmal pririty interrupt in the inactive and waiting states. Hwever, when acknwledged, this interrupt enters the active 3-10

state, and remains there during the executin f ne instructin. At the cmpletin f the ne instructin, the single-instructin interrupt returns t the inactive state withut the aid f a branch and clear instructin. NTERRUPT CONTROL Tw prgram cntrl features are available in the interrupt system. These features are Enable/Disable and Arm/Disarm. Arm/Disarm (ptinal hardware) cntrls whether an interrupt can prceed frm the inactive state t the waiting state. The disarm cnditinfan interrupt level prhibitsan interrupt signal entering the level frm causing the interrupt t enter "waiting" frm inactive ll With Enable/Disable, the entire set f interrupts in the system can be enabled and disabled under prgram cntrl. When the interrupt system is enabled, interrupts can prceed frm the waiting state t the active state. 150 152 154 156 160 162 164 166 170 172 174 176 200 l 1177 Table 3-2. nterrupt Lcatin Assignments Pwer On (always armed) Pwer Off (always armed) Main Frame Parity Errr (armed via a cnsle switch) Data Multiplexing System Parity Errr (armed via a cnsle switch) Unassigned Unassigned nterrupt, Clck Sync (always armed) nterrupt, Clck Pulse (arm furnished) 11 (arm furn ished) 12 (arm furnished) Unassigned Unassigned System nterrupts (arms ptinal, single instructin discretinary) l System nterrupts The fllwing interrupts are exceptins and are always enabled: 1. Pwer fa ii-safe (2 interrupts) 2. Memry parity errr (2 interrupts) 3. Real-time clck (2 interrupts) 4. /O Channel (2 interrupts) The cntrl f the ptinal Arm/Disarm feature perates n individual interrupt levels f the System interrupts (200-1176), that is, any chsen interrupt level may be selectively armed r disarmed. But the instructin structure fr Arm/Disarm allws these interrupts t be perated n in grups f sixteen. SNGLE NSTRUCTON NTERRUPTS ROUTNES Only the fllwing instructins will be meaningfully interpreted as single-instructin interrupt rutines: 1. EOM 2. BMC, BRM 3. MPO - MPO, in this case, will nt alter the Flag. Hwever, if the restred, incremented perand equals 00008, a different interrupt pu se wi be generated (see Real-Time Clck Optin, Appendix B-1). 4. EXU - Can nly execute the abve-listed instructins. NON-NTERRUPTABLE NSTRUCTONS An interrupt cannt ccur between the executin f ENERGZE OUTPUT M (EOM) and the instructin fllwing it. This is als true fr the input/utput instructins, POT/BPO, PN/BP, WOT/ROT, and WN/RN. N interrupt can ccur between a single-instructin interrupt and the return t the main prgram. When these instructins branch, an interrupt cannt ccur between their executin and the executin f the branch-t instructin: BRU BRL BDA BAX BFF BFT ENABLE/DSABLE NTERRUPT NSTRUCTONS Three instructins are available fr setting, resetting, and testing the state f the NTERRUPT ENABLED indicatr. ER 00 ENABLE NTERRUPT 5 6 ER uncnditinally sets the NTERRUPT ENABLED indicatr and enables the interrupt system. At the end f the next interruptable instructin, if any interrupt levels are waiting, the ne with the highest pririty becmes active. ER cannt be interrupted. Registers Affected: Nne DR 00 51 DSABLE NTERRUPT 5 6 50 11 Timing: 3,4 DR uncnditinally resets the NTERRUPT ENABLED indicatr and disables the interrupt system. The current state f all interrupt levels is unchanged by this instructin. DR cannt be interrupted. Registers Affected: Nne Timing: 3,4 let 01 NTERRUPT ENABLED TEST; SET FLAG F NTERRUPT SYSTEM ENABLED f the pririty interrupt system is enabled, let sets the Flag Bit. f the pririty interrupt system is disabled, let resets the Flag Bit. Registers Affected: F Timing: 3,4 50 11 11 3-11

ARMNG FEATURE The arming feature is cntrlled fr a grup f 16 interrupts at ne time. (The 24-bit POT/PN ptin is a prerequisite fr the arming feature. ) The sequence f instructins required t arm the selected interrupts is: EOM POT AR HTWELVE Alert the extender Lad mst significant 12 bits int extender Arm interrupts POT LOWTWELVE Transmjt entire 24 bits t the arming chassis and arms selected interrupts EXTENDER ALERT EOM The Extender EOM alerts the extender t accept the next POTted"wrd. AR alerts the arming chassis that a 24-bit cntrl wrd is cming with the POT that fllws. The secnd POT triggers the entire 24-bit transmissin. The effective address f the Extender Alert EOM (an internal type) is: AR 2 4 ARM NTERRU PTS 2 2 3 4 5 6 7 8 9 10 11 12 13 14 AR prepares the arm interrupt cntrl unit t receive a cntrl wrd fr a grup f 16 interrupt levels. A PARALLEL OUTPUT (POT) must always fllw AR, r an unpredictable peratin results. AR cannt be interrupted. Registers Affected: Nne Timing: 3,4 The tw wrds which the PARALLEL OUTPUT (POT) instructins address have the fllwing frmat: High-Order 12-bit Wrd Address 56 Lw-Order 12-bit Wrd 12 Select Bits nterrupt 78 11 The address field in bit psitins 0 thrugh 5 identifies wh ich grup f 16 interrupts in the system is being addressed. The C field cntrls what is dne t the particular interrupt levels selected in bit psitins 8 thrugh 23. Bit psitin 8 refers. t the lwest-numbered level f the grup, therefre the ne with the highest pririty. Bit psitin 23 refers t the last r highestnumbered level, the ne with lwest pririty. The first grup f 16 is grup 0, Fr example, wrds f 0024 and 0000 arm level number 202 (the level f secnd highest pririty), The cntrl peratins are: 6-7 Functin 00 Nt used 01 10 11 Arm all interrupt levels that are selected by a 1 in bit psitins 8-23 Disarm all interrupt levels that are selected by a in bit psitins 8-23 Arm all interrupts selected by a 1 and disarm all interrupts selected by a 0 in bit psitins 8-23 23 NACTVE +, Prceed if ARMED + WATNG + Prceed if ENABLED ACTVE + Prceed if PROPER PRORTY Figure 3-3. nterrupt Arm-Enable Respnse 3-12

CONTROL CONSOLE The basic cmputer system includes a cnsle fr peratr cntrl. This cnsle cnnectsdirectly t the central prcessr, cntains switches fr peratin, and displays the cntents f peratinal registers. DSPLAYS The registers displayed n the cnsle directly reflect the cntents f the hardwa re reg isters. f the peratr clears r changes a display, the cntents f the actual reg ister change identically. PROGRAM LOCATON This display cnsists f 15 binary indicatrs with a CLEAR buttn fr the entire register and a set buttn fr each indicatr. The prgram cunter cntains the lcatin f the next instructin t be executed. The peratr may change the cntents f the prgram cunter via the CLEAR and set buttns. When the peratr places the cmputer in RU N, the first instructin cmes frm the lcatin shwn in the PROGRAM LOCATON display. NPUT -OUTPUT The UNT lights cntain the unit address f the peripheral device currently cnnected t the /O Channel. The ERROR ight reflects the status f the /O Channel errr indicatr. HALT The HALT light lights whenever the cmputer executes a halt instructin while in the RUN psitin. Setting the RUN/DLE/ STEP switch t DLE clears the halt. REGSTER DSPLAY This display cnsists f 12 binary indicatrs with a CLEAR buttn fr the entire register and a set buttn under the P Register indicatrs that als serve the A, B, and C Registers. The Register switch selects the internal register t be displayed. The selectable registers are: C A B C Register, which usually cntains the cntents f the memry wrd whse address is in the prgram cunter A Register B Register Placing the cmputer in DLE, clearing the register, and then pressing the buttn in the crrespnding bit psitins under the indicatrs sets the cntents f the selected register. Pressing a buttn places a 1-bit int the selected psitin f the register. MEMORY PARTY f an perand r instructin access frm memry encunters a parity errr and the memry switch is in the HALT psitin MEMORY PARTY lights. Setting the memry parity switch t CONTNUE clears the indicatr and turns ff the light. ENABLE ENABLE lights whenever the interrupt system is enabled. FLAG The FLAG indicatr cnsists f a single binary indicatr. FLAG is lit when the Flag Bit is a 1. SWTCHES POWER The POWER switch turns the cmputer system pwer n r ff. When pwer is n, the switch is it. FLL T initiate a fill ", 1. Press the RESET buttn. 2. Hld dwn the FLL switch crrespnd ing t the peripheral dev ice frm wh ich a fi is desired. 3. Mve the RUN/DLE/STEP switch frm DLE t RUN while cntinuing t hld the apprpriate FLL. 4. Release the FLL switch. Fill causes the fllwing: 1. An EOM pcde is generated. Bit 0 = 0 Bit 1 =0 Bit 2 = 0 ~ Buffer Cntrl Mde Bit 3= 0--- Frward Directin Bit 4 = 0 Bit 5 = 1 ---.~ Binary Mde Bit 6 = 0 Bit 7 = 1 ---~. Tw Characters per Wrd Bit a = 1 Bit 9 - Bit 14 = The unit address f the indicated peripheral: Paper Tape Cards Mag Tape Disc 04a 06 a loa 26 a 3-13

--flll-- NT(RRUPT ---- NPUT OUTPUT ---- REGSTER DSPLAY UNT HALT (NABLEO [RROR ---- - ----- W PAP(Jt MEMORY TAPE CARDS PARTY flac PROGRAM loc. lion HO RESE T.l>-.. AC O"UM CLUt TAPE =1 " " " NCRE MENT NTERRUPT RUN - HALT RE SET DLE CONTNUE p. SET STEP. BREAKPONT OtH MEM ORY Figure 3-4. SDS 92 Cmputer Cntr l Pnel

2. 9 wrds (r t End-f-Recrd) read int memry starting in lcatin 00000 8. 3. Cmputatin begins at lcatin 00000 8. 4. NOTE: The /O Channel is still active and the input peripheral device is sti sending characters t the channel. (f the fill rutine is less than 9 wrds, the End-f Recrd makes the channe inactive; cmputatin sti ges t 00000.) RUN/DLE/STEP The RUN/DLE/STEP switch is a three-psitin, tggle switch with tw statinary psitins and a spring-laded mmentary psitin in STEP. n the RU N psitin, cmputatin ccurs at machine speed. n the DLE psitin, the cmputer idles immediately after an instructin has been read frm memry. f the Register switch is in the C psitin, the first wrd f an instructin may be viewed in the REGSTER DSPLAY. Depressing the switch t STEP reaccesses and executes the instructin; the cmputer returns t the dle state. T "step" anther instructin, the peratr releases the switch t the DLE psitin and then depresses it again t STEP. N interrupts can ccur (i.e., g int the active state) while stepping. HOLD/NCREMENT Placing the HOLD/NCREMENT switch in the "up" psitin causes the current cntents f the prgram cunter t be held. This inhibits the prgram cunter frm cunting. Mmentarily placing the HOLD/NCREMENT switch in the NCREMENT psitin increments the prgram cunter by ne and brings the cntents f the newly addressed lcatin t the C Register. RESET This switch initializes the cntrl sectin f the cmputer. t resets the /O Channel, clears the FLAG, sets PCT, clears the NTERRUPT ENABLED, clears any parity errr indicatin, clears all interrupts arms, and clears a interrupt levels. The peratr must set the RUN/DLE/STEP switch t DLE befre pressing this switch. Switch Select This tw-psitin tggle (labeled C and P) selects which REG STER DSPLAY/PROGRAM LOCATON will be affected by the C LEAR and set buttns. Register Select This three-psitin switch selects the register t be shwn n the REGSTER DSPLAY lights. MEMORY PARTY n the HALT psitin, this switch causes the cmputer t enter the dle state whenever a memry parity errr ccurs. n the CONTNUE psitin, the cmputer des nt change state when a memry parity ccurs. n the NTERRUPT state, any memry parity will result in ne f tw interrupts (ptinal). BREAKPONT The fur BREAKPONT switches are externally cntrlled, internally testable prgram switches. Breakpint test instructins test them. MEMORY OUT This is a mmentary switch that causes the cmputer, in DLE, t place the cntents f the lcatin specified by the prgram cunter int the C Register. MEMORY N Th is is a mmentary swi tch that causes the cmputer, in D LE, t place int the lcatin specified in the prgram cunter fhe cntents f the C Register. PERPHERAL EQUPMENT DESCRPTON This sectin describes sme f the input/utput devices thatcan be attached t a buffer and explains their use. NPUT/OUTPUT TYPEWRTER The cntrl cnsle may cntain an electric, input/utput typewriter fr peratr cntrl, errr r status messages, and similar functins. The typewriter cnnects t the /O Channel, has the input unit address 01, and the utput unit address 41. Appendix 1-1 cntains the typewriter cdes. The typewriter cntrl instructins fllw. The sample instructins use Typewriter N. 1 with 2 characters per wrd mde. RKB 1,2 READ KEYBOARD 2 Characters/Wrd 02301t This instructin activates the /O Channel and cnnects t it Typewriter N. 1. RKB readies the channel t read input frm the keybard. This instructin lights the input light n the typwriter. TYP 1,2 WRTE TYPEWRTER 2 Characters/Wrd 02341 This instructin activates the /O Channel and cnnects t it Typewriter N.1. TYP readies the channel t write utput t the typewriter. t This ctal number is the EOM r SES effective address cnfiguratin. 3-15

EXAMPLE: Typewriter Output This example types the fllwing message: DO frm lcatin OUTWD; the internal cdes fr these characters are in this lcatin. The rutine uses Typewriter N.1; the rutine assumes the channel t be initially inactive. Lcatin nstructin Cmments N RES 2 This assembler directive reserves tw lcatins fr the mark entry. TYP 1,2 This EOM instructin cnnects Typewriter N. 1 t the channel fr utput and spec ifies tw characters per wrd. The ctal cnfiguratin f the EOM address is 02341. WOT OUTWD This instructin transfers the cntents f lcatin OUTWD t the /O Channel. The new cntents f the channel are utput t the typewriter as tw 6-bit charactersand typed. The next instructin in sequence is executed as sn as the wrd is placed in the channel. TOP Th is instructin terminates utput n the channel. When the channel and the Sing e Character Register are c lear f characters t be utput, the channel sets its Unit Address Register t zer; th is discnnects the channel. When accessed, this instructin executes immediately; the next instructin in sequence is then executed. The ctal cnfiguratin f this EOM address is 12100. BRU *N This instructin transfers t sme ther prgram area. OUTWD 24 46 This wrd cntains the internal cde fr the characters DO. EXAMPLE: Typewriter Output then nput This example types ut the message: PROG then awaits the input f a single character. nput terminates with a carriage return typed by the peratr; the husekeeping necessary t determine when the carriage return has been input is nt given. N TEST RES TYP WOT WOT TOP CAT BFF RKB WN 2 1,2 MSSGE MSSGE+l TEST 1,1 KEYWD Cnnect channel t Typewriter N. 1. Output first wrd f message. The central prcessr "hangs Up" n this instructin until the secnd character frm the preceding instructin has cleared the channel buffer int the Single Character Buffer fr utput. Then this WOT executes filling the channel buffer with cntents f lcatin MSSGE + 1. Terminate utput when channel system is clear. The prgram "hangs Up" here unti the channel transmits the last character. This instructin cnnects Typewriter N. 1 t the channel fr input and specifies ne character per wrd. The ctal cnfiguratin is 02101. The cmputer "hangs Up" n this instructin until a characterentersthechannel frm the keybard; then the wrd in the channel buffer is placed int lcatin KEYWD. The input character is in bit psitins 0 thrugh 5 f KEYWD. Bit psitin 6 thrugh 11 are unpredictable At this pint, the wrd in KEYWD is placed elsewhere in memry and the rutine returns t the WN abve. When executed, a test is made t determine if the new input character is the carriage return cde. ndexing r indirect addressing can be used with the WN t facilitate input. When the carriage return is detected, the fllwing is executed. DSC BRU *N This instructin discnnects the channel by immediately clearing the Unit Address register t zer. The cta cnfiguratin f the EOM address is 00100. Return t main prgram. 3-16

PAPER TAPE NPUT/OUTPUT Frmat The paper tape used is ne-inch wide, affrding space fr eight data hles and a sprcket hle in each frame f infrmatin. There are ten frames per inch f paper tape. Six hle psitins are used fr infrmatin, ne is used fr an dd parity check, and the eighth is unused. frames). Bit psitin 4 f the EOM that addresses the punch cntains a "0" t punch leader; bit psitin 4 cntains a "1" t punch withut leader. The EOM instructin that addresses and alerts the punch prduces gap. N terminal punch peratin prduces gap after punching a blck. The punch perates asynchrnusly. f the channel des nt supply characters t the punch fast enugh, the punch waits fr each character, lsing n data and creating n errrs. p 0 000 00 00000 B 0 0 00 A 0 0 00 B 0 0 0 0 00 '0'......... 0'0. '000 0 00 0 00 0 00 0 0 00 0 0 i ~ Directin f Travel Blck f nfrmatin nfrmatin is rganized n the tape in blcks. A blck is a grup f frames set ff by a gap f at least ne blank frame (in which nly the sprcket hle is punched) at either end. Blcks may be f variable lengths. n sme peratins, a tape may cnsist f nly ne blck, such as a surce language tape prepared ff-line. n this case, the prgram need nt read the entire blck at ne time, but may stp the reader between frames, by discnnecting via DSC, and then start again t read the remainder r anther prtin f the blck. Prgramming There are n status tests fr the reader r punch, that is, they are always ready fr peratin. When the channel addresses either device, the device starts t send r accept data within apprximately ne character time. The reader and punch perate nly in the binary mde and the frward directin. The reader r punch ignres any different mde specified, and uses the frward-binary mde. Unit address f 04 is fr Paper Tape Reader 1, and unit address 44 is fr Paper Tape Punch 1. Paper Tape nstructins The fllwing instructins use the /O channel, Paper Tape Number 1 with tw characters per wrd frmat. RPT 1, 2 READ PAPER TAPE 02304 This instructin initiates a paper tape read peratin n tape read statia number 1 cnnected t the channel in the tw characters per wrd frmat. A prgram reads paper tape in a straightfrward way, using RN r a WN in a read lp unti the desired number f wrds are input r until gap is detected. The tape stps in less than n~ frame; this means that n frame is missed between subsequent read peratins. An input peratin that terminates because f gap (End-f-Recrd) stps the tape after the first blank f the gap. When starting the tape fr reading, the tape reader ignres any leading blank frames. After reading a meaningful data wrd (ne r tw characters as defined by the prgram) frm the tape, the reader recgnizes the next blank frame as gap and signals the channel with an End-f-Transmissin indicatin. Punching The EOM t alert the tape punch als turns n the punch mtr (if nt already n). f the punch instructin (EOM) s indicates, the punch unit punches a segment f leader (gap, r blank PTL 1, 2 PUNCH PAPER TAPE WTH LEADER 00344 This instructin initiates a paper tape punch peratin n tape punch statin number 1 cnnected t the channel in the tw characters per wrd frmat. t generates apprximately twelve (12) frames f leader preceding the first punched frame. PPT 1, 2 PUNCH PAPER TAPE WTHOUT LEADER 02344 This instructin initiates a paper tape punch peratin n tape punch statin number 1 cnnected t the channel in the tw characters per wrd frmat. t generates n leader preceding the first punched frame. 3-17 -

EXAMPLE: Punch Paper Tape This rutine punches ne blck f eight wrds (16 characters) frm lcatins 02000 thr~gh precedes the blck. The rutine is a clsed subrutine. Lcatin nstructin Address Cmments 02007. A twelve-frame leader FRST RES 2 This instructin is an assembler mnemnic used fr cnvenience t reserve the subrutine entry lcatins. PTL 1,2 This instructin cnnects the channel t Paper Tape Punch N. 1 and specifies tw characters per wrd mde. The instructin asks fr leader t be punched. The ctal cnfiguratin fr this EOM is 00344. LDA =7 This instructin sets (A) equal t 7. ROT 02000 This instructin transfers each wrd as needed t the channel beginning in lcatin 02000. TOP This instructin is executed in 4 r 5 cyc les and then the cmputer executes the next instructin. The executin f TOP causes the channel t discnnect when the last character shifts ut f the buffer and transmits ut f the Sing e Character Register. BRU *FRST This instructin returns t the main prgram. EXAMPLE: Read Paper Tape This rutine reads a 64-character blck frm paper tape int memry beginning at lcatin 02000. The rutine uses the tw character per wrd mde, making the input 32 wrds. The rutine is a 'c lsed subrutine. FRST RES 2 This assembler instructin reserves the entry lcatins. RPT 1,2 This instructin cnnects t the channel the Paper Tape Reader N. 1 and specifies tw characters per wrd mde. The cta cnfiguratin fr this EOM is 02304. LDA =33 The 33 represents tw mre than the expected recrd size. RN 02000 This instructin receives each wrd in the blck beginning in lcatin 02000 and ging thrugh 02037, 8 When the channel detects the End signal (gap) fllwing the blck during the input transmissin, the RN finishes executin and the cmputer ges t the next instructin. CARD NPUT/OUTPUT Frmat The cmputer uses 80-clumncards in tw frmats: Hllerithand binary. The reader reads Hllerith-cded infrmatin frm cards and the crrespnding SDS character cdes g int memry. n th is mde, each card clumn cntains the equivalent f ne 6-bit internal character. The character cdes are in Appendix -l. Binary-cded infrmatin ges nt the card with tw 6-bit characters per clumn. n binary mde, ne clumn frms a wrd. The reader reads the card frm clumn 1 t 80 in a tp-bttm rder. A single card hlds 160 characters. Figure 3-5 shws the relatin f Hllerith infrmatin n a card and in memry. Reading The card reader scans the card, clumn by clumn, starting with clumn ne, and transmits either 80 r 160 characters depending n the mde f peratin. With pwern and cards in the hpper, the peratr readies the reader by pressing the START buttn. During prgram peratin, the prgram must test fr the Ready cnditin befre initiating a card-read. A Read EOM instructin starts the card-reading peratin; then the prgram cntrls the flw f infrmatin int memry via a RN r WN lp. The end f the card sets the End-f-Recrd cnditin. n the Hllerith mde, any clumn-read that is nt punched in ne f the 64 cmbinatins listed in Appendix 1-1 results in a Validity check. Presence f a Validity check causes an errr signal t be sent t the channel and lights the VALDTY CHECK ight n the reader. f the stacker shu d becme fu, r the hpper empty, the reader ges Nt Ready and ights the NOT READY light. The card reader remains in the Nt Ready state until the peratr crrects the situatin and presses the START buttn. Upn reading the last card, the reader sets an End-f File signal if its EOF ON switch is n. The central prcessr can test the End-f-Fi e signal which determines if mre cards are in the hpper. Punching The punch punches cards a rw at a time, starting with rw 12. The punch cupler in bth Hllerith and binary mdes autmatically rearranges the infrmatin t be punched. The card punch prgram must present the entire image, 80 r 160 characters, t the punch 12 times fr each card. The punch perates in the fllwing manner. As each rw f the card appraches the punch statin, the cupler examines every character f the image t determine which clumn psitin in that rw shu d be punched. After the 12th utput, the punch punches rw 9 and cmpletes the card cyc e. The card punch is Ready t punch if there are cards in the magazine, the stacker is nt full, and the START buttn has been 3-18

~CD _... Card A.. - - C> ~ ~ U1......,...,... ~ - c::>......... - = - c... en c.n......... - - c....., ~ = CD... O'J.,.. 00 en c.n... -~_ (,,(,0 01)... c.n :~c;t CD c... a" U1.,.. r-~ ~... ~..... 00=_ CO... c.n... =0<.:0 CD en c.n... ~Nc.c c -." en c.n...... 1110 <.0 CO en c.n... ~ (Q CD... 0') c.n.,........, c; CD g -.. en - c.n... -N g; (l:) CO "... en ~CD c -... en c.n......... 00... en c.n... C>..., ~ CD O'J c.n... ~c:.... C') c.n...... Cn"" '"'" ~ - i:j... c.n... t..) ~... ""... c.n... c,...) C=> ""...,cnc.n.,..w...:.-c..., en W N - ~... -.... W Q t.: '-0 QO c..n... w t;'j <"" "" ti....... W f:) = = ~~ e... en c.n ~ W ::;:<.0 0:>...... w ~ - c:::)... c.n"" W N - = t CD (X... en c.n W c.n... c..,) r-.,) D.:..::. ~U)... Q ~ 00... :: CD g... ext... en c.n... c.." ex)... en c.n.,.. w c.n...... CX'... C') c.n... w == "" _ = c.n...... e!u:) Cr:)... en <.n.-. Ct.) <;;'-0 c -.. c.n"" Ct.) ~c. c -.t en U" -:jq -!!- N ~ _u: -~ VJ.--i -:!."> :;0-0 ;.0 - B Memry S T 62 63 A R -i B+ 1 21 51 0; T 15 63 60 C R ~ 23 51 ~ T.t; 63 60 15 15 60 60 15 0 60 00, 1 73 01 15 15 60 60 B + 39 15 0 60 00 1 0 01 00 Figure 3-5. Card Read nt Memry in Hllerith pressed. The punch remains Ready as lng as the abve cnditins are true. A punch card instructin given when the punch is Ready causes a card t feed past the punch statin. The prgram must then give the same instructins 12 times t transmit the card image t the cupler. Prgramming nstructins The card reader instructins belw use unit number 1 with the tw characters per wrd transmissin mde. CRT 1 CARD READER READY TEST 12106 This test determines if the selected card reader is Ready t read. f the reader is Nt Ready, the cmputer resets the Flag Bit. CFT 1 CARD READER END-OF-FLE TEST 11106 This test determines if the End-f-File cnditin frm the card reader has been detected. f nt, the cmputer sets the Flag Bit. f the EOF cnditin has been detected, the cmputer resets the Flag Bit. The reader remains in the End-f-Fi e cnditin unti cardsare added t the hpper r until the EOF ON switch is turned ff. RCD 1,2 READ CARD DECMAL (Hllerith) 02306 RCD alerts the card reader, causes a card t feed frm the hpper, and selects the Hllerith mde (as each clumn is read, it is translated t an SDS internal cde). This mde reads up t 80 characters (40 wrds) frm a card. RCB 1,2 READ CARD BNARY 03306 RC B a erts the card reader, causes a card t feed frm the hpper and selects the binary mde (as each clumn is read it is transmitted as tw 6-bit binary characters). This mde reads up t 160 characters (80 wrds) frm a card. Card Punch nstructins CPT 1 CARD PUNCH READY TEST 14146 This test determines if the selected card punch is Ready t punch. f s, the cmputer sets the Flag Bit. f the punch is Nt Ready, the cmputer resets the Flag Bit. The peratr makes the punch Ready by placing blank cards in the magaz ine and pr-essi ng the START buttn. PC D 1,2 PUNCH CARD DECMAL (Hllerith) 02346 PC D alerts the punch, causes a card t feed past the punch statin and selects the Hllerith mde. A transmissin f 80 characters (40 wrds) must fllw this instructin. The instructin PC D fllwed by the transmissin instructins fr 80 characters per card must be repeated 12 times. PCB 1,2 PUNCH CARD BNARY 03346 PCB alerts the punch, causes a card t feed past the punch statin and selects the binary mde. A transmissin f 160 characters (80 wrds) must fllw this instructin. The instructin PCB fllwed by the transmissin instructinsfr 160 characters per card must be repeated 12 times. 3-19

EXAMPLE: Card Read This prgram reads ne card in Hllerith mde. t is a clsed subrutine. The prgram enters the rutine via a BRM. Lcatin nstructin Address Cmments FRST RES 2 This assembler instructin reserves lcatins fr the subrutine entry. TEST CRT This instructin is the card reader Ready test fr Card Reader Number 1. t sets the Flag Bit if ready. BFF TEST This instructin branches back t the test n Nt Ready. An exit t a Nt Ready crrective rutine can be put here. RCD, 2 This instructin cnnects the Card Reader 1 and starts a card mving tward the read statin. Hllerith mde is specified. The ctal cnfiguratin fr this instructin is 02306. LDA =39 This is the repeat cunt fr RN. RN READ Beginning in READ, this instructin transfers wrds frm the channel int the lcatins until the entire card is read. BRU "'FRST This instructin branches back t the main prgram. EXAMPLE: Card Punch The prgram punches ne card in Hllerith mde beginning frm lcatin 03740. the prgram presents the card image t the punch. The B Register cunts the 12 times FRST RES 2 This instructin reserves the lcatins fr the subrutine entry. LDB =11 TEST CPT This instructin tests the card punch fr a Ready cnditin. t sets the F lag Bit if Ready. BFF TEST This instructin branches back t the test, CPT, if the Flag is reset. An exit t a time lp with.the facility t tell the peratr that the card punch wi nt becme Ready can be placed here. GEE PCD, 2 This instructin executes if the punch is Ready. t cnnects the channel t the Card Punch Number, and starts a card mving tward the punch statin. The tw characters per wrd and Hlleriih mde are specified. LDA =39 Starting with lcatin 03740, ROT transmits 40 wrds t the Punch. ROT 03740 TOP This terminates utput. CTEST CAT Wait fr the last character t be transmitted. BFF CTEST SUB =1 SUB decrements (B) by ne and sets F if the new (B) is equal t 7777 8, BFF GEE Nte that the card image must be sent t the channel twelve times t punch a card. BRU *FRST Return t main prgram via lcatin FRST. 3-20

MAGNETC TAPE NPUT/OUTPUT Magnetic tape units used in SDS cmputer systems are BMcmpatible. The tape is ne-half inch wide, Mylar base material, 1.5 mils thick. Tape reels (10 1/2 inch, plastic) cntain up t 2400 feet f tape. A reflective marker, placed n the back f the tape apprximately ten feet frm the beginning f it, indicates the lad pint. The leading ten feet leave space fr threading tape thrugh the guides n the unit. The lad pint marker is n the My-ar side f the tape alng the edge nearest the peratr when the tape is munted. A similar marker is alng the ther edge f the tape t mark the end-freel. Abut 14 feet f tape are reserved between the end-freel marker and the end f the tape. This space includes at least ten feet f leader and enugh tape t hld a recrd f 9,600 characters in 200 bpi density after the end-f-reel marker is sensed. The lngitudinal check character always reflects an even parity check fr each channel. n the BCD mde, the check character itself always has an even number f 1-bits. n the binary mde, hwever, the check character may have either an even r an dd number f 1-bits. This means that a reverse scan ver a binary recrd may result in turning n the errr indicatr in the buffer even thugh the recrd itself is crrect. As a general rule, the prgram ignres the errr indicatr after a reverse peratin. Rutines shuld always place a TAPE READY TEST (TRT) between tape peratins f ppsite directin t ensure that the tape unit stps and reverses. Gd prgramming terminates tape writing by several inches f erasure whenever subsequent resumptin f recrding is anticipated. This eliminates the effects f a pssible extraneus character that might arise thrugh subsequent tape repsitining. Characters are recrded n tape in seven parallel tracks. A change in the magnetic flux in a track recrds a 1-bit fr a given character psitin. N change in magnetic flux indicates a O-bit. Six f the tracks cntain infrmatin; the seventh track is a parity check. The system allws bth even and dd parity, as needed. Binary recrding uses dd parity. n this mde, the tape recrds the six-bit charcicters frm memry withut change. Binary-cded decimal (BCD) recrding uses even parity. n this mde, the tape cntrl unit transfrms characters frm the channel t cnfrm with standard BM, BCD interchange cde (see Appendix A-1). Only the capacity f available cre strage in the cmputer limits blck length. A recrd gap (sectin f blank tape) abut 3/4-inch lng separates blcks n tape. n writing, the tape autmatically prduces gap at the end f a recrd. Reading begins with the first character sensed after the gap and cntinues until the next gap is encuntered. An inter-recrd gap, fllwed by a special, single-character recrd, marks the end f a file f infrmatin. The character is a Tape Mark (0001111). Writing a ne-wrd recrd in BCD with ne-character-per-wrd frmat can recrd such a mark. A prgram may write ne r mre files n a reel f tape. On reading an End-f -File recrd, the tape cntrl unit stps the tape and sets its End-f-File indicatr which may be tested by the prgram. The tape cntrl unit cnsiders any recrd cntaining nly Tape Mark (0001111) characters an End-f-File. The tape reads such characters int m-emry like any ther characters. As the tape unit writes infrmatin, it makes an dd-even cunt f the number f 1-bits in each track. At the end f each recrd, it writes a bit fr each track such that the ttal number f 1-bits in each track is even. This parity check sum is always even whether the character parity is even r dd. The character cntaining these check bits is the lngitudinal parity character; the tape unit writes it slightly past the end f recrded infrmatin in the blck. A Read Binary r Read BCD EOM starts a tape which cntinues until the tape unit detects an End-f-Recrd gap. f the cmputer des nt instruct the tape unit t cntinue, it stps in the middle f that gap. When the tape stps, the tape unit discnnects frm the channel. f the tape encunters an End-f-File, the tape cntrl unit sets its EOF indicatr. The central prcessr can test this indicatr which remains set until the tape unit cntrl receives a new EOM. The tape always stps after the Tape Mark. At the end f the file, the prgram reads the EOF character (0001111) int memry alng with its check character. n a tw character per wrd read, this appears in the first wrd f the input area as a 1717 wrd. When the tape unit is writing n tape, it may transmit flux disturbing surges ahead f the current writing psitin; these surges affect previusly written recrds further dwn the tape. This means that a recrd in the middle f a fi e cannt be updated r rewritten if the recrds that fllw it are t be read. Any errr detected either by the channel in the character parity check r by the cntrl unit with the lngitudina parity check sets the channel errr -indicatr. When detecting such an errr in reading, the rutine shuld backspace the tape ver the errneus recrd and attempt t lire-read the recrd. The tape backspaces ver recrds using the Scan feature. A Scan reverse EOM starts the tape in reverse. A TERMNATE NPUT (TP) EOM shuld immediately fllw. The prgram then waits fr the channel t becme inactive (r awaits the End-f-Transmissin interrupt if armed and the interrupt system is enabled). When the channel becmes inactive (r the Endf-Transmissin interrupt ccurs), the tape stps in frnt f the backwardly traversed recrd. A Scan peratin is similar t a Read peratin except that the channel shifts the characters read thrugh its Wrd Assembly Register, but des nt cnsider a wrd cmplete unti a tape 3-21

gap is encuntered. When the tape reaches the gap, the channel uses the last tw characters in the wrd assembly as the nly wrd read frm the recrd. When scanning in reverse, the wrd cnsists f the last tw characters scanned that are the first tw lgical characters f the recrd. This peratin assembles these characters in reverse. Fr example, if the first tw characters f the recrd are 12 and the tape scans the recrd in reverse, these appear as 21 in the wrd stred fr that recrd. The same peratins ccurs in the frward scan with the last tw characters f the recrd frming the wrd stred. The Scan is useful fr reverse searching n the first wrd f the recrds in the fi e being searched. n this case, the rutine starts the tape in a reverse scan and hangs Upll n a WN. When the tape reaches the beginning f the recrd, the first wrd f the recrd transfers t the buffer. The WN stres the first wrd and the prgram checks the key wrd against the search key. f they agree, then the prgram need nly wait fr the channel t becme inactive and the rutine reads the recrd frward. f the recrd is nt the desired ne, the prgram gives anther Scan reverse withut waiting fr the channel t becme inactive. f the tape encunters the End-f-Reel marker while reading, the tape lgic sets the End-f-Reel indicatr in the tape unit; the prgram can test this at any time. An End-f-File nrmally indicates the end f recrded infrmatin n tape. Pssibly, hwever, the End-f-Reel indicatr may mark the last recrd n the reel. Writing A Write rutine writes tape after testing the tape unit fr Ready and testing fr the fi e prtect ring n the tape reel (i.e., the flag was set by the test). The Write tape EOM starts tape mtin; the tape remains in mtin unti it receives the terminatin signal frm the channel. The tape cntrl unit then writes the remaining characters f the recrd (thse in the channel buffer) and writes the lngitudinal check character. When the read-after-write head reads this check character, the tape signals the channel that it has reached Gap. f the tape receives n further Write instructin within ne millisecnd, the tape stps and discnnects. f the user wishes t backspace r rewind and then t return at sme later time t recrd additinal infrmatin at the end f the previus series f recrds, the rutine shuld write an Endf-File character r erase a segment f t~pe after the series f written recrds. This practice prvides psitive identificatin f the end f a file and facilitates return t a specific lcatin n the tape. f the prgrammer des nt use this methd, the tape may nt subsequently stp in the same lcatin at the end f the series f recrds as it did when writing the last recrd. This wuld leave a segment f tape in the gap which has nt been written and may cause errneus peratin when reading the,tape. n additin t writing under prgram cntrl, the prgram can als erase tape. When an Erase EOM with an erase unit address is used, the tape perates as thugh it were in a Write mde, except that it recrds n infrmatin. The prgram cunts the number f wrds t be erased. The use f this type f erase is fr the crrectin f a Write errr. When a Write errr ccurs, an ERASE REVERSE TAPE starts the tape in reverse. Then the same cunt used t write the recrd riginally cntrls the erase. This prcedure ensures that the tape always returns t the beginning f the errneus recrd, even if a bad spt n the tape might appear as a gap. The rutine may nw rewrite the recrd. f the Write still prduces an errr, the rutine erases the recrd backward and then erases it frward, using the same cunt and bypassing the sectin f tape where the difficulty ccurred. The rutine may nw rewrite the recrd n a new sectin f tape. The erase prcedure is used t prduce the required 3.75 inches f blank tape between the lad pint and the first recrd. A rutine des this by erasing 300 wrds at 200 bpi density, 834 wrds at 556 bpi density, r 1200 wrds at 800 bpi density. EOM instructins t the tape units specify start-withut-eader since the tape un it generates gap at the end f a" recrds fr leader. A leader instructin shuld never be included in a magnetic tape prgram because an attempt t generate leader may cause an errneus peratin. Prgramming The SES and EOM instructins fr nrmal tape peratins are isted belw. The EOM instructins use tw characters per wrd frmat. TRT n TAPE READY TEST 1051n TRT test tape unit number n fr Nt Ready. f the tape is Nt Ready, the cmputer sets the Flag Bit. f the tape is Ready, the cmputer resets the Flag Bit. A tape is Nt Ready: if there is n physical unit set t the lgical unit number be i ng tested, if the selected unit is nt in the Autmatic mde, r if the tape is in mtin fr any peratin. FPT n FLE PROTECT TEST 1411n FPT tests tape unit number n fr file prtect ring. f the file ring is inserted, the cmputer sets the Flag Bit. f nt inserted, the cmputer resets the Flag Bit. The reset will ccur if lgical unit n is absent frm the channel line. 3-22

BTT n BEGNNNG OF TAPE TEST 1211n BTT tests tape unit number n fr the beginning f the tape. f it is nt psitined n the lad-pint marker, the cmputer sets the Flag Bit. f psitined at the lad-pint marker, the cmputer resets the Flag Bit. The reset will ccur if lgical unit n is absent frm the channel line. ETT n END OF TAPE TEST 11lln ETT tests whether tape unit number n is nt psitined at the end f the tape. f the tape unit has nt sensed the End-f Reel marker, the cmputer sets the Flag Bit. f the End-f Reel marker has been sensed, the cmputer resets the Flag Bit. The End-f-Reel cnditin is reset when the tape is mved backward ver the End-f-Reel marker. The reset will ccur if lgical unit n is absent frm the channel line. DT2 n DENSTY TEST, 200 BP 1631n DT2 tests tape unit number n fr being set at 200 bpi density. f nt, the cmputer sets the Flag Bit. f s, the cmputer resets the Flag Bit. DT5 n DENSTY TEST, 556 BP 1671n DT5 tests tape unit number n fr being set at 556 bpi density. f nt, the cmputer sets the Flag Bit. f s, the cmputer resets the Flag Bit. DT8 n DENSTY TEST, 800 BP 1731n DT8 tests tape unit number n fr being set at 800 bpi density. f nt, the cmputer sets the Flag Bit. f s, the cmputer resets the Flag Bit. TFT TAPE END-OF-FLE TEST 13710 TFT test the tape cntrl unit fr a tape under its cntrl encuntering an End-f-Fi e during the last Read r Scan peratin. f the End-f-File indicatr is reset, the cmputer sets the Flag Bit. f the End-f-File indicatr is set, the cmputer resets the Flag Bit. The End-f-File indicatr remains set until anther tape peratin is requested. WTB n,2 WRTE TAPE N BNARY 0335n WTB starts tape unit n in a Binary Write mde. WTD n,2 WRTE TAPE N DECMAL (BCD) 0235n WTD starts tape unit Wn in a BCD Write mde. EFT n,2 ERASE FORWARD TAPE 0337n EFT starts tape unit n in an Erase mde. ERT n,2 ERASE REVERSE TAPE 0737n ERT starts tape unit n in reverse in an Erase mde. RTB n,2 READ TAPE N BNARY 0331n RTB starts tape unit n in a Binary Read mde. RTD n,2 READ TAPE N DECMAL (BCD) 0231n RTD starts tape unit n in a BCD Read mde. SFB n,2 SCAN FORWARD N BNARY 0333n SFB starts tape unifn frward in a Binary Scan mde. SFD n,2 SCAN FORWARD N DECMAL (BCD) 0233n SFD starts tape unit n frward in a BCD Scan mde. SRB n,2 SCAN REVERSE N BNARY 0733n SRB starts tape unit n in reverse in a Binary Scan mde. SRD n,2 SCAN REVERSE N DECMAL (BCD) 0633n SRD starts tape unit n in reverse in a BCD Scan mde. REW n REWND 1411n REW starts tape unit n in a Rewind. RTS a CO NVERT READ TO SCAN 14100 RTS cnverts an in-prcess Read peratin t a Scan. f the interrupts are disabled when the gap is encuntered and the prgram is hanging n a WN (executed after RTS, but befre the gap), the WN brings int memry the last tw characters frm the channel buffer. f the interrupts are enabled, an End-f Wrd (11) interrupt ccurs when the gap is encuntered by the tape unit; the last character is avai lable via a WN. f anther Read r Scan EOM is executed within 1 millisecnd f the gap ccurrence, the tape des nt stp and n End-f-Recrd (2) interrupt ccurs; if nt, an 12 interrupt ccurs when the tape is actively stpping (1 millisecnd). Nte: All scans must be in the 2 characters/wrd mde. This necessarily implies that the read peratin preceding an "RTS" must have been in the 2 characters/wrd mde. MAGNETC TAPE EXAMPLE PROGRAMS The fllwing examples shw samples f cmplete input/utput prgrams fr magnetic tape. 3-23

EXAMPLE: Magnetic Tape Read This prgram reads ne recrd frm Magnetic Tape N. 1 n the /O Channel. The prgram is a clsed subrutine. The tape is nt at the beginning r the end f the tape. Lcatin nstructin Cmments FRST RES 2 This instructin reserves lcatins fr the subrutine entry. TEST TRT This instructin tests Ready Magnetic Tape N. 1. the cmmand is 10511. The ctal cnfiguratin fr BFT TEST This instructin branches back t TRT if the F lag is set. An exit t a rutine that determines reasn fr the nn-ready cnditin can be placed here. RTD 1,2 This instructin activates the channel, cnnects it t Magnetic Tape N.1, and starts tape mtin. The tw characters per wrd and BCD mdes are specified. LDA =99 This cunt is fr the RN instructin t read 100 wrds. RN 03000 Read 100 wrds starting at lcatin 03000. TP Terminate input. BRU *FRST This instructin branches back t the main prgram via FRST. EXAMPLE: Write Magnetic Tape This prgram writes ne recrd n magnetic tape. The prgram is a clsed subrutine; it uses Magnetic Tape N. 1. FRST RES 2 This instructin reserves lcatins fr the subrutine entry. TEST TRT This instructin tests whether Magnetic Tape N. 1 is ready. BFT TEST Thi s tests the Flag True. Thi s instructin branches back t the Ready test if the Flag is set. FPT This instructin tests whether the fi e prtect ring is present n the tape reel. f s, the cmputer sets the Flag B it. The cta cnfiguratin f the address is 14111. BFF BRML f the Flag is reset, branch t BRML. WTD 1,2 This instructin cnnects the channel t Magnetic Tape N.1, specifies BCD transfer mde, and starts the tape mving. Tw characters per wrd mde is specified. The ctal cnfiguratin f the instructin is 02351. LDA =99 The 100 is the blck length. ROT 02000 Starting at lcatin 02000, ROT writes 100 wrds. TOP This terminates utput. CTEST CAT Wait fr channel t discnnect. BFF CTEST BRU *FRST This instructin branches back t the main prgram via FRST. BRML BRM OPER This instructin branches and marks t an assumed rutine t call the peratr and instructs him t insert file-prtect ring n Magnetic Tape N. 1. 3-24

LNE PRNTER SDS buffered line printers are capable f printing up t 1000 lines per minute at 132 characters per line, with a standard set f 56 characters. Printing is accmpl ished by means f a rtating character drum and a bank f 132 print hammers. The drum passes 56 different characters, in ines f 132 each, past the hammer bank. Upn cmmand frm the cmputer, the selected print hammers drive the paper against the ribbn and nt the apprpriate character typeface as it passes the print psitin. The characters are transmitted sequentially fr strage in the printer buffer befre printing. A prgrammable frmat tape lp prvides fixed (r preselected) space cntrl. Upspac ing f 1 t 7 ines, as well as page cntrl, may be accmplished by prgram instructins. An ptinal, ff- ine faci ity allws the prgram r the peratr t initiate card-t-printer r magnetic tape-t-printer peratins simu taneus with cmputatin (see Off-Line Printing). Printer Cntrls The printer cntrls, Figure 3-6, fr SDS ine printers cnsist f eight switches and indicatrs. ( P~%ER ) ( READY) fl--...:~..:...;~:..:..~e=-d---1) ( FAUL T ) Figure 3-6. Printer Cntrl ndicatr Lights and Switches The POWER ON switch is an alternate actin switch. The cmputer must be turned n fr this switch t be activated. Pressing POWER ON lights the tp half f the indicatr, turns n the mtrs and hammer driver pwer supply, and starts a timer that allws the mtrs t reach prper speed. After 20 secnds the bttm half lights, indicating that the printer is perable. When the printer is initially turned n, the READY indicatr is ff. When pressed, it is turned n if: 1. paper is laded in the line pri nter, 2. the lwer half f the POWER ON switch is lighted, and 3. the hammer pwer supply is n. This indicatr autmatically ges ff when the abve cnditins are nt real ized. The printer is ready fr either n- ine rff- ine peratin when READY is turned n. Ready is reset t preclude cmputer interventin while changing paper r ribbn, r perating the TOP OF FORM r SNGLE SPACE switches. Pressing TOP OF FORM causes the printer t psitin paper accrding t frmat tape channell. This indicatr is lighted nly when the frmat tape is psitined at channell, that is, tp-f-frm n a standard tape lp. Th is switch is perative when there is paper in the printer and the READY indicatr isff. Pressing SNGLE SPACE causes the printer t upspace paper ne single space, independently f the vertical frmat tape. Th is switch is perative when there is paper in the machine and READY is ff. The FAULT indicatr lights when the printer detects a parity errr as infrmatin transfers frm the buffer t the print hammers, r when it detects a parity errr in incming data frm magnetic tape r cards during an ff- ine peratin. t remains lighted unti the next EOM addresses the printer. The cnditin f the ight crrespnds t the status f a prgramtestable fau t ind icatr in the printer. MANUAL OFF LNEt is a cmbinatin switch and indicatr fr ff- ine peratin. The cmputer r the peratr may initiate ff- ine peratin, which is indicated by the illuminatin fthe bttm half f this switch. f the peratr presses this switch t initiate ff-line peratin, the tp half is als lighted. This indicatr is nrmally reset when the end-f-file is detected frm the input unit. Pressing READY when it is lighted als resets it, that is, by switching the printer frm the "ready" t the "nt ready" state. The FORMAT/SPACE t switch is used in ff- ine peratin. The peratr may use either mde, spacing a single space after each ine f print, r using the first character stred n tape r cards as a vertical frmat character. The TAPE/CARD t switch selects the desired input device. Paper Tape Frmat Lp A paper tape frmat lp, placed in the printer, allws upspacing t prceed t prespecified vertical psitins n the print page. The frmat lp is an eight.:.channel paper tape. Putting a punch in the specified channel at the desired vertical spacing selects the channel upspace. Channel 1 is the tp-f-frm channel, channel 7 is the bttm-f-frm channel, and channel 0 is the single-upspace channel. n the ff- ine mde with SPACE cntrl, channel 0 cntrls single spacing. When printing with n frmat lp inserted in the printer, single upspacing ccurs regardless f the channel specified. Terminating Line Printer Output When the sing e-wrd mde f transmissin is used fr printing n the line printer, each character transmissin fr a line must be fllwed by a TERMNATE OUTPUT (TOP) instructin. TOP is autmatically generated with interlaced utputs. Errr Cnditins 1. Print fault - parity errr during transfer f character infrmatin frm print buffer t print hammers. 2. Buffer errr - parity r character rate errr during transfer f infrmatin thrugh buffer. t f an ff- ine cupler is nt attached t the printer, the MANUAL OFF LNE, FORMAT SPACE, and TAPE CARD indicatrs neither light nr affect printer peratin. 3-25

3. nput fau t - parity errr in incming data frm cards r magnetic tape (during ff- ine peratin nly). Off-Line Printing The ptinal, ff- ine facil ity allws the ine printer t prduce printed recrds frm card r magnetic tape surces withut cmputer attentin. The character transm issin prceeds directly frm the surce t the cmputerfr ther input/ utput peratins (e.g., card reading n card reader 2, card punch, paper tape read/punch, disk read/write, etc.). Once initiated, the printing peratin is cntrlled by the surce and prceeds until the surce generates an end-f-file signal (see card input and magnetic tape input fr apprpriate endf-file cnditins). The FAU LT indicatr ights when a parity errr is detected during the reading f a tape recrd; the ff- ine printer rereads the recrd in an attempt t read gd data. f th is reread recrd cntains an errr, FAULT lights, the ff-line peratin terminates, and the printer ges back n- ine if physically cnnected t the cmputer and the MANUAL indicatr is ff. When a val idity check ccurs during a card read, FAU LT ights, the peratin terminates, and the printer ges back n-line if the MANUAL indicatr is ff. The next EOM addressing the printer resets FAULT if the printer is n-line. f the MANUAL indicatr is n, the errr cnditin may be cleared by pressing READY ff and then n again. f a fault ccurs in an ff-line peratin initiated by the cmputer, the usual methd fr clearing the errr is: 1. Press MANUAL n. 2. Press READY ff. 3. Press READY n. 4. Press MANUAL ff. n a manually-initiated ff-line peratin, steps 1 and 4 are nt required. Off-line printing can be frmatted as desired thrugh the use f a single upspace r the frmat cntrl mde (see Table 3-3). Off-line printing terminates by an end-f-file indicatr frm either device. Upn terminatin f an ff-line peratin, a physically cnnected ff-line printer system returns n-line, prvided the MANUAL indicatr is ff. Table 3-3. Frmat Cntrl Characters Cde Character Functin 00 0 Skip t frmat channel 0 01 1 Skip t frmat channell 02 2 Skip t frmat channel 2 03 3 Skip t frmat channel 3 04 4 Skip t frmat channel 4 05 5 Skip t frmat channel 5 06 6 Sk ip t frmat channel 6 07 7 Skip t frmat channel 7 40 - (hyphen) D nt space 41 J Upspace 1 line 42 K Upspace 2 lines 43 L Upspace 3 lines 44 M Upspace 4 lines 45 N Upspace 5 lines 46 0 Upspace 6 lines 47 P Upspace 7 lines Printing Off-Line Under Operatr Cntrl The prcedure fr peratr cntrl f ff- ine printing is: 1. Switch n the desired input device. (Magnetic tape is selected by dial ing it t lgical tape number 7.) 2. Place paper at tp f frm, as desired, by means f the TOP OF FORM switch. 3. Select desired input device by means f the TAPE/CARD switch. 4. Select either the FORMAT r SPACE mde as required. 5. Press MANUAL OFF LNE switch. 6. Press READY switch n, which initiates actual data transfer. Printing Off-Line Under Cmputer Cntrl The prcedure fr cmputer cntrl f ff- ine printing is: 1. Turn the equipment n. 2. Prepare the desired input device fr peratin. 3. Select desired input device by means f the TAPE/CARD switch. 4. Select either the FORMAT r SPACE mde as required. 5. Press the READY switch n. 6. Under prgram cntrl, test the tape r card unit and the ine printer fr ready" cnd itin. 7. Then, t start transfer f data, give the POL instructin t print ff-line. Prgramming SES and EOM instructins that have spec ial use with the printer fllw. Fr cnvenience, assume that the instructins address the channel and cnnect, test, r use Line Printer Number 1 n the channel. PRT 1 PRNTER READY TEST 12160 This instructin tests the printer fr a Ready cnditin. f the printer can accept a ine t be printed, r accept a skip r space instructin, it is Ready. f the printer is Ready, the cmputer sets the Flag Bit. f the printer is Nt Ready, the cmputer resets the Flag Bit. When the printer is upspac ing paper, PRT tests fr Ready befre the dpw -.-.- ic; ----- '1------ rnmnlp.tp.. Thp.rp.fnrp....-------,. PRT ---' is ineffective _.. - - fr - searatina - tw successive upspace peratins. The secnd upspace specified may verride the first ne un less suffic ient de lay is inserted (see PSP). EPT 1 END OF PAGE TEST 14160 This instructin tests the printer fr having paper psitined at the End-f-Page, which is marked by a punch in channel 7. f nt at End-f-Page, the cmputer sets the Flag Bit. f at Endf-Page, the cmputer resets the Flag Bit. PFT 1 PRNTER FAU LT TEST 11160 This instructin tests whether the PRNT FAULT indicatr isset. f nt set, the cmputer sets the Flag Bit. f set, the cmputer resets the Flag Bit. 3-26

POL 1 PRNTER OFF-LNE 10360 Apprximate cmpletin times fr PSP (frm initiatin f instructin t paper stp) are: This instructin places the printer ff-line t begin an ff-line Upspace 1 line: 25 millisecnds print peratin. The card reader and/r magnetic tape attached Upspace mre than 1 line: Add 10 millisecnds fr each t the channel als ges ff-line (see Off-line Printing). additinal line. PSC 1, n PRNTER SKP TO FORMAT CHANNEL n 1n560 Off-line Print Terminatin The printer sk ips t frmat cntr channe n, where n dentes a channel number frm 0 t 7. The frmat cntrl is an eightchannel paper tape lp that is as lng as the paper being used. (See PSP fr timing.) Off-line printing terminates when an end-f-file indicatr frm the magnetic tape unit r card reader ccurs. When printing frm magnetic tape, the print peratin terminates when the first character read frm a recrd is the end-f-fi e cde, ctal 17. PSP 1, n PRNTER UPSPACE n LNES 1n760 The printer upspaces frm 0 t 7 ines as specified by n. Cnsecutive upspace instructins must be separated by a sufficient time delay. Otherwise, the tw PSP instructins may be merged by the printer. When printing frm cards, the print peratin terminates when the end-f-file signal cmes frm the reader. This ccurs when the card hpper becmes empty and the EOF ON switch n the reader is n (END OF FLE indicatr lights). f the hpper becmes empty when EOF ON is nt ighted, the printer waits fr mre cards t be placed in the hpper and the reader t becme ready. When the reader isagain ready, printing resumes. EXAMPLE: Print Tw Lines This prgram prints tw ines at the tp f a page with a single upspace between. Assume that the printer is Ready r is becming Ready after a print peratin. The prgram is a clsed subrutine fr printer number 1. Lcatin nstruct in Address Cmments FRST RES LDA 2 = 65 Saves lcatins fr subrutine entry. Lad A with 65 fr the length f a line image. TSTl PRT This instructin tests fr printer Ready. f nt Ready, the cmputer resets the Flag Bit. f Ready, the cmputer sets the Flag. BFF TSTl Nt Ready, retu rn t the test. PSC 1, This instructs the printer t mve paper t the tp f the page. The ctal cnfiguratin is 11560. PLP 1, 2 Cnnect line printer t the channel, specify 2 character/wrd mde. ROT LNE1 Output 66 wrds frm line 1 image area. TOP Terminate utput. TST2 CAT Wait fr channe t discnnect BFF TST2 LDA = 65 Relad A with 65. TST3 PRT Wait fr printer t becme ready after printing first line. BFF TST3 PSP 1, Upspace printer 1 line. The ctal cnfiguratin is 11760. PLP 1, 2 Address printer. ROT LNE2 Output image fr line 2. TOP Terminate. BRU *FRST Exit the subrutine via the BRU. 3-27

SDS CHARACTER CODES Characters Typewriter Printer SDS nternal Cde Card Cde Magnetic Tape Characters BCD Cde n Tape Typewriter Printer SDS nternal Cde Card Cde Magnetic Tape BCD Cde n Tape 2 3 4 5 6 7 8 9 Space # r = @r 2 3 4 5 6 7 8 9 Blank 00 01 02 03 04 05 06 07 10 11 12 13 14 2 3 4 5 6 7 8 9 8-2 8-3 8-4 12 01 02 03 04 05 06 07 10 K L M N P Q K L M N P Q 11 R R 120 Car. Ret.!0!0 13 $ 14 40 41 42 43 44 45 46 47 50 51 52 53 54 11 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-00 11-8-3 11-8-4 40 41 42 43 44 45 46 47 50 51 52 53 54 >.J >.J 15 16 17 8-5 8-6 8-7 15 16 17 55 56 57 11-8-5 11-8-6 11-8-7 55 56 57 & r + A B C D +.A. B C D E' 20 21 22 23 24 25 F 26 G H G H 27 30 31 Backspace?0 1 32 33 l r) 34 35 < 36 Stp 370 12 12-:1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-00 12-8-3 12-8-4 12-8-5 12-8-6 12-8-7 60 61 62 63 64 65 66 67 70 71 72 73 74 75 76 77 t) / s T U V W X Y Z Blank / S T U V W X Y z 60 61 62 63 64 65 66 67 70 71 Tab *0 * 72 73 % r ( 74 75 \ 76 <' Delete 77@ Blank 0-1 0-2 0-3 0-4 0-5 0-6 0-7 0-8 0-9 Cl-8-2 0-8-3 0-8-4 0-8-5 0-8-6 0-8-7 20 21 22 23 24 25 26 27 30 31 32 33 34 35 36 37 NOTES: @ CD 8) The characters?! and * are fr input nly. The functins Backspace, Carriage Return, r Tab always ccur n utput. On the ff-line paper tape preparatin unit, 37 serves as a stp cde and 77 as a cde delete. The internal cde 12 is written n tape as a 12 in BCD. When read, this cde is always cnverted t 00. The cdes 12-0 and 11-0 are generated by the card punch; hwever, the card reader wi als accept 12-8-2 fr 32 and 11-8-2 fr 52 t maintain cmpatibility with earlier s.ystems. Fr the 64-character printers nly. A-l

TABLE OF POWERS OF TWO 21\ 2 4 8 16 32 64 128 256 512 1 024 2 048 4 096 8 192 16 384 32 768 65 536 131 072 262 144 524 288 1 048 576 2 097 152 4194304 8 388 608 16 777 216 33 554 432 67 108 864 134 217 728 268 435 456 536 870 912 1 073 741 824 2 147 483 648 4 294 967 296 8 589 934 592 17 1 79 869 184 34 359 738 368 68 719 476 736 137438953472 274 877 906 944 549 755 ~13 888 1 099 511 627 776 2 199 023 255 552 4 398 046 511 104 8 796 093 022 208 1 7 592 186 044 416 35 184 372 088 832 70 368 744 177 664 140 737488 355 328 281 474 976 710 656 n 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 1.0 0.5. 25 0.125. 062 5 0.031 25 0.015625 0.007 812 5. 003 906 25 0.001 953 125 0.000 976 562 5. 000 488 281 25 0.000 244 140 625 O. 000 122 070 312 5 O. 000 061 035 156 25 O. 000 030 517 578 125. 000 015 258 789 062 5 0.000 007 629 394 531 25 O. a a a 003 81 4 697 26 5 6 25 O. 000 001 907 348 632 812 5 0.000 000 953 674 316 406 25 0.000 000 476 837 158 203 125 0.000 000 238 418 579 101 562 5 0.000 000 119 209 289 550 781 25 0.000 000 059 604 644 775 390 625 0.000 000 029 802 322387 695 312 5 0.000 000 014 90116119384765625 0.000 000 007 450 580 596 923 828 125 0.000 000 003 725 290 298 461 914 062 5 O. 000 0 a a 001 862 645 1 49 23 a 957 031 25 O. 000 000 000 931 322 574 615 478 515 625 O. 000 000 000 465 661 287 307 739 257 812 5 O. 000 000 000 232 830 643 653 869 628 906 25 O. 000 000 000 116 415 321 826 934 814 453 125 O. 000 000 000 058 207 660 913 467 407 226 5625 0.000 000 000 029 103 830 456 733 703 613 281 25 O. 000 000 000 014 551 915 228 366 851 806 640 625 0.000 000 000 007 275 957614 183 425 903 320 312 5 O. 000 000 000 003 637 978 807 091 712 951 660 156 25 O. 000 000 000 001 818 989 403 545 856 475 830 078 125 O. 000 000 000 000 909 494 701 772 928 237 915 039 062 5 O. 000 ado 000 000 454 747 350 886 464 118 957 519 531 25. 000 000 000 000 227 373 675 443 232 059 478 759 765 625 0.000 000 000 000 113 686 837 721 616 029 739 379 882 812 5 O. 000 000 000 000 056 843 418 860 808 014 869 689 941 406 25 O. 000 000 000 000 028 421 709 430 404 007 434 844 970 703 125 0.000 000 000 000 014210 854 715202 003 7174224853515625 O. a a a a a a a a a a a a a a 7 1 a 5 427 3 57 6 a 1 a 01 8 58 711 242 675 781 25 O. 000 000 000 000 003 552713 678 800 500 929355621 337890 625 A-2

OCTAL - DECMAL NTEGER CONVERSON TABLE 0000 t 0777 Octal) 0000 t 0511 (Decima/) Octal Decimal 10000-4096 20000-8192 30000-12288 40000-16384 50000-20480 60000-24576 70000-28672 0 0000 0000 0010 0008 0020 0016 0030 0024 0040 0032 0050 0040 0060 10048 0070 0056 0100 0064 0110 0072 0120 0080 0130 0088 0140 0096 0150 0104 0160 0112 0170 0120 0200 0128 0210 0136 0220 0144 0230 0152 0240 0160 0250 0168 0260 0176 0270 0184 0300 0192 0310 0200 0320 0208 0330 0216 0340 0224 0350 0232 0360 0240 0370 0248 1 2 3 4 5 6 7 0 1 0001 0002 000,;3 0004 0005 0006 0007 0400 0256 0257 0009 0010 0011 0012 0013 0014 0015 0410 0264 0265 0017 0018 0019 0020 0021 0022 0023 0420 0272 0273 0025 0026 0027 0028 0029 0030 0031 0430 0280 0281 0033 0034 0035 0036 0037 0038 0039 0440 0288 0289 0041 0042 0043 0044 0045 0046 0047 0450 0296 0297 0049 0050 0051 0052 0053 0054 0055 0460 0304 0305 0057 0058 0059 0060 0061 0062 0063 0470 0312 0313 0065 0066 0067 0068 0069 0070 0071 0500 0320 0321 0073 0074 0075 0076 0077 0078 0079 0510 0328 0329 0081 0082 0083 0084 0085 0086 0087 0520 0336 0337 0089 0090 0091 0092 0093 0094 0095 0530 0344 0345 0097 0098 0099 0100 0101 0102 010~ 0540 0352 0353 0105 0106 0107 0108 0109 0110 0111 0550 0360 0361 0113 0114 0115 0116 0117 0118 0119 0560 0368 0369 0121 0122 0123 0124 0125 0126 0127 0570 0376 0377 0129 0130 0131 0132 0133 0134 0135 0600 0384 0385 0137 0138 0139 0140 0141 0142 0143 0610 0392 0393 0145 0146 0147 0148 0149 0150 0151 0620 0400 0401 0153 0154 0155 0156 0157 0158 01~9 0630 0408 0409 0161 0162 0163 0164 0165 0166 0167 0640 0416 0417 0169 0170 0171 0172 0173 0174 0175 0650 0424 0425 0177 0178 0179 0180 0181 0182 0183 0660 0432 0433 0185 0186 0187 0188 0189 0190 0191 0670 0440 0441 0193 0194 0195 0196 019-7 0198 0199 0700 0448 0449 0201 0202 0203 0204 0205 0206 0207 0710 0456 0457 0209 0210 0211 0212 0213 0214 0215 0720 0464 0465 0217 0218 0219 0220 0221 0222 0223 0730 0472 0473 0225 0226 0227 0228 0229 0230 0231 0740 0480 0481 0233 0234 0235 0236 0237 0238 0239 0750 0488 0489 0241 0242 0243 0244 0245 0246 0247 0249 0250 0251 0252 0253 0254 0255 0760 0496 0497 0770 0504 0505 2 3 4 5 6 7 0258 0259 0260 0261 0262 Ol63 0266 0267 0268 0269 0270 0271 0274 0275 0276 0277 0278 0279 0282 0283 0284 0285 0286 0287 0290 0291 0292 0293 0294 0295 0298 0299 0300 0301 0302 0303 0306 0307 0308 0309 0310 0311 0314 0315 0316 0317 0318 0319 0322 0323 0324 0325 0326 0327 0330 0331 0332 0333 0334 0335 0338 0339 0340 0341 0342 0343 0346 0347 0348 0349 0350 0351 0354 0355 0356 0357 0358 0359 0362 0363 0364 0365 0366 0367 0370 0371 0372 0373 0374 0375 0378 0379 0380 0381 0382 0383 0386 0387 0388 0389 0390 0391 0394 0395 0396 0397 0398 0399 0402 0403 0404 0405 0406 0407 0410 0411 0412 0413 0414 0415 0418 0419 0420 0421 0422 0423 0426 0427 0428 0429 0430 0431 0434 0435 0436 0437 0438 0439 0442 0443 0444 0445 0446 0447 0450 0451 0452 0453 0454 0455 0458 0459 0460 0461 0462 0463 0466 0467 0468 0469 0470 0471 0474 0475 0476 0477 0478 0479 0482 0483 0484 0485 0486 0487 0490 0491 0492 0493 0494 0495 0498 0499 0500 0501 0502 0503 0506 0507 0508 0509 0510 0511 lc)oo 0512 t t 1777 1023 (Octal) toeciml) 0 1000 0512 1010 0520 1020 0528 1030 0536 1040 0544 1050 0552 1060 0560 1070 0568 1100 0576 1110 0584 1120 0592 1130 0600 1140 0608 1150 0616 1160 0624 1170 0632 1200 0640 1210 0648 1220 0656 1230 0664 1240 0672 1250 0680 1260 0688 1270 0696 1300 0704 1310 0712 1320 0720 1330 0728 1340 0736 1350 0744 1360 0752 1370 0760 1 2 3 4 5 6 7 0 1 0513 0514 0515 0516 0517 0518 0519 1400 0768 J769 0521 0522 0523 0524 0525 0526 0527 1410 0776 0777 0529 0530 0531 0532 0533 0534 0535 1420 0784 0785 0537 0538 0539 0540 0541 0542 0543 1430 0792 0793 0545 0546 0547 0548 0549 0550 0551 1440 0800 0801 0553 0554 0555 0556 0557 0558 0559 1450 0808 080~ 0561 0562 0563 0564 0565 0566 0567 1460 0816 0817 0569 0570 0571 0572 0573 0574 0575 1470 0824 0825 0577 0578 0579 0580 0581 0582 0583 1500 0832 0833 0585 0586 0587 0588 OS89 0590 0591 1510 0840 0841 0593 0594 0595 0596 0597 0598 0599 1520 0848 0849 0601 0602 0603 0604 0605 0606 0607 1530 0856 0857 0609 0610 0611 0612 0613 0614 0615 1540 0864 0865 0617 0618 0619 0620 0621 0622 0623 1550 0872 0873 0625 0626 0627 0628 0629 0630 0631 1560 0880 0881 0633 0634 0635 0636 0637 0638 0639 1570 0888 0889 0641 0642 0643 0644 0645 0646 0647 1600 0896 0897 0649 0650 0651 0652 0653 0654 0655 1610 0904 0905 0657 0658 0659 0660 0661 0662 0663 1620 0912 0913 0665 0666 0667 0668 0669 0670 0671 1630 0920 0921 0673 0674 0675 0676 0677 0678 0679 1640 0928 0929 0681 0682 0683 0684 0685 0686 0687 1650 0936 0937 0689 0690 0691 0692 0693 0694 0695 1660 0944 0945 0697 0698 0699 0700 0701 0702 0703 1670 0952 0953 0705 0706 0707 0708 0709 0710 0711 1700 0960 0961 0713 0714 0715 0716 0717 0718 0719 1710 0968 0969 0721 0722 0723 0724 0725 0726 0727 1720 0976 0977 0729 0730 0731 0732 0733 0734 0735 1730 0984 0985 0737 0738 0739 0740 0741 0742 0743 1740 0992 0993 0745 0746 0747 0748 0749 0750 0751 1750 1000 1001 0753 0754 0755 0756 0757 0758 0759 1760 1008 1009 0761 0762 0763 0764 0765 0766 0767 1770 1016 1017 2 3 4 5 6 7 077Q 0771 0772 0773 0774 0775 0778 0779 0780 0781 0782 0783 0786 0787 0788 0789 0790 0791 0794 0795 0796 0797 0798 0799 0802 0803 0804 0805 0806 0807 0810 0811 0812 0813 0814 0815 0818 0819 0820 0821 0822 0823 0826 0827 0828 0829 0830 0831 0834 0835 0836 0837 0838 0839 0842 0843 0844 0845 0846 0847 0850 0851 0852 0853 0854 0855 0858 0859 0860 0861 0862 0863 0866 0867 0868 0869 0870 0871 0874 0875 0876 0877 0878 0879 0882 0883 0884 0885 0886 0887 0890 0891 0892 0893 089~ 0895 0898 0899 0900 0901 OS02 0903 0906 0907 0908 0909 0910 0911 0914 0915 0916 091 7 0918 0919 0922 0923 0924 0925 0926 0927 0930 0931 0932 0933 0934 0935 0938 0939 0940 0941 0942 0943 0946 0947 0948 0949 0950 0951 0954 0955 0956 0957 0958 0959 0962 0963 0964 0965 0966 0967 0970 0971 0972 0973 0974 0975 0978 0979 0980 0981 0982 0983 0986 0987 0988 0989 0990 0991 0994 0995 0996 0997 0998 0999 1002 1003 1004 1005 1006 1007 1010 1011 1012 1013 1014 1015 1018 1019 1020 1021 1022 1023 A-3

Octal-Decimal nteger Cnversin Table 0 1 2 3 4 5 6 7 0 1 2000 1024 1025 1026 1027 1028 1029 1030 1031 2400 1280 1281 2010 1032 1033 1034 1035 1036 1037 1038 1039 2410 1288 1289 2020 1040 1041 1042 1043 1044 1045 1046 1047 2420 1296 1297 2030 1048 1049 1050 1051 1052 1053 1054 1055 2430 1304 1305 2040 1056 1057 1058 1059 1060 1061 1062 1063 2440 1312 1313 2050 1064 1065 1066 1067 1068 1069 1070 1071 2450 1320 1321 2060 1072 1073 1074 1075 1076 1077 1078 1079 2460 1328 1329 2070 1080 1081 1082 1083 1084 1085 1086 1087 2470 1336 1337 2100 1088 1089 1090 1091 1092 1093 1094 1095 2500 1344 1345 2110 1096 1097 1098 1099 1100 1101 1102 1103 2510 1352 1353 2120 1104 1105 1106 1107 1108 1109 1110 1111 2520 1360 1361 2130 1112 1113 1114 1115 1116 1117 1118 1119 2530 1368 1369 2140 1120 1121 1122 1123 1124 1125 1126 1127 2540 1376 1377 2150 1128 1129 1130 1131 1132 1133 1134 1135 2550 1384 1385 2160 1136 1137 1138 1139 1140 1141 1142 1143 2560 1392 1393 2170 1144 1145 1146 1147 1148 1149 1150 1151 2570 1400 1401 2 3 4 1282 1283 1284 i290 1291 1292 1298 1299 1300 1306 1307 1308 1314 1315 1316 1322 1323 1324 1330 1331 1332 1338 1339 1340 1346 1347 1348 1354 1355 1356 1362 1363 1364 1370 1371 1372 1378 1379 1380 1386 1387 1288 1394 1395 1396 1402 1403 1404 5 6 1285, 1286 1293, 1294 1301 1302 1309 1310 1317 1318 1325 1326 1323 1334 1341 1342 1349 1350 1357 1358 1365 1366 1373 1374 1381 1382 1389 1390 1397 1398 1405 1406 7 1287 1295 1303 1311 1319 1327 1335 1343 1351 1359 1367 1375 1383 1391 1399 1407 2000 t 2777 (Octal) 1024 t 1535 (Decimal) Octal Decimal 10000 4096 20000 8192 30000 12288 40000-16384 50000 20480 60000 24576 70000 28672 2200 1152 1153 1154 1155 1156 1157 1158 1159 2600 1408 1409 2210 1160 1161 1162 1163 1164 1165 1166 1167 2610 1416 1417 2220 1168 1169 1170 1171 1172 1173 1174 1175 2620 1424 1425 2230 1176 1177 1178 1179 1180 1181 1182 1183 2630 1432 1433 2240 1184 1185 1186 1187 1188 1189 1190 1191 2640 1440 1441 2250 1192 1193 1194 1195 1196 1197 1198 1199 2650 1448 1449 2260 1200 1201 1202 1203 1204 1205 1206 1207 2660 1456 1457 2270 1208 1209 1210 1211 1212 1213 1214 1215 2670 1464 1465 2300 1216 1217 1218 1219 1220 1221 1222 1223 2700 1472 1473 2310 1224 1225 1226 1227 1228 1229 1230 1231 2710 1480 1481 2320 1232 1233 1234 1235 1236 1237 1238 1239 2720 1488 1489 2330 1240 1241 1242 1243 1244 1245 1246 1247 2730 1496 1497 2340 1248 1249 1250 1251 1252 1253 1254 1255 2740 1504 1505 2350 1256 1257 1258 1259 1260 1261 1262 1263 2750 1512 1513 2360 1264 1265 1266 1267 1268 1269 1270 1271 2760 1520 1521 2370 1272 1273 1274 1275 1276 1277 1278 1279 2770 1528 1529 1410 1411 1412 1418 1419 1420 1426 1427 1428 1434 1435 1436 1442 1443 1444 1450 1451 1452 1458 1459 1460 1466 1467 1468 1474 1475 1476 1482 1483 1484 1490 1491 1492 1498 1499 1500 1506 1507 1508 1514 1515 1516 1522 1523 1524 1530 1531 1532 1413 1414 1421 1422 1429 1430 1437 1438 1445 1446 1453 1454 1461 1462 1469 1470 1477 1478 1485 1486 1493 1494 1501 1502 1509 1510 1517 1518 1525 1526 1533 1534 1415 1423 1431 1439 1447 1455 1463 1471 1479 1487 1495 1503 1511 1519 1527 1535 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 3000 1536 1537 1538 1539 1540 1541 1542 1543 3400 1792 1793 3010 1544 1545 1546 1547 1548 1549 1550 1551 3410 1800 1801 3020 1552 1553 1554 1555 1556 1557 1558 1559 3420 1808 1809 3030 1560 1561 1562 1563 1564 1565 1566 1567 3430 1816 1817 3040 1568 1569 1570 1571 1572 1573 1574 1575 3440 1824 1825 3050 1576 1577 1578 1579 1580 1581 1582 1583 3450 1832 1833 3060 1584 1585 1586 1587 1588 1589 1590 1591 3460 1840 1841 3070 1592 1593 1594 1595 1596 1597 1598 1599 3470 1848 1849 3100 1600 1601 1602 1603 1604 1605 1606 1607 3500 1856 1857 3110 1608 1609 1610 1611 1612 1613 1614 1615 3510 1864 1865 3120 1616 1617 1618 1619 1620 1621 1622 1623 3520 1872 1873 3130 1624 1625. 1626 1627 1628 1629 1630 1631 3530 1880 1881 3140 1632 1633 1634 1635 1636 1637 1638 1639 3150 1640 1641 1642 1643 1644 1645 1646 1647 3540 1888 1889 3550 1896 1897 3160 1648 1649 1650 1651 1652 1653 16'>4 1655 3560 1904 1905 3170 1656 1657 1658 1659 1660 1661 1662 1663 3570 1912 1913 3200 1664 1665 1666 1667 1668 1669 1670 1671 3600 1920 1921 3210 1672 1673 1674 1675 1676 1677 1678 1679 3610 1928 1929 3220 1680 1681 1682 1683 1684 1685 1686 1687 3620 1936 1937 3230 1688 1689 1690 1691 1692 1693 1694 1695 3630 1944 1945 3240 1696 1697 1698 1699 1700 1701 1702 1703 3640 1952 1953 3250 1704 1705 1706 1707 1708 1709 1710 1711 3650 1960 1961 3~60 1712 1713 1714 1715 1716 1717 1718 1719 3660 1968 1969 3270 1720 1721 1722 1723 1724 1725 1726 1727 3670 1976 1977 3300 1728 1729 1730 1731 1732 1733 1734 1735 3700 1984 1985 3310 1736 1737 1738 1739 1740 1741 1742 1743 3710 1992 1993 3320 1744 1745 1746 1747 1748 1749 1750 1751 3720 2000 2001 3330 1752 1753 1754 1755 1756 1757 1758 1759 3730 2008 2009 3340 1760 1761 1762 1763 1764 1765 1766 1767 3740 2016 2017 3350 1768 1769 1770 1771 1772 1773 1774 1775 3750 2024 2025 3360 1776 1777 1778 1779 1780 1781 1782 1783 3760 2032 2033 3370 1784 1785 1786 1787 1788 1789 1790 1791 3770 2040 2041 1794 1795 1796 1802 1803 1804 1810 1811 1812 1818 1819 1820 1826 1827 1828 1834 1835 1836 1842 1843 1844 1850 1851 1852 1858 1859 1860 1866 1867 1868 1874 1875 1876 1882 1883 1884 1890 1891 1892 1898 1899 1900 1906 1907 1908 1914 1915 1916 1922 1923 1924 1930 1931 1932 1938 1939 1940 1946 1947 1948 1954 1955 1956 1962 1963 1964 1970 1971 1972 1978 1979 1980 1986 1987 1988 1994 1995 1996 2002 2003 2004 2010 2011 2012 2018 2019 2020 2026 2027 2028 2034 2035 2036 2042 2043 2044 1797 1798 1805 1806 1813 1814 1821 1822 1829 1830 1837 1838 1845 1846 1853 1854 1861 1862 1869 1870 1877 1878 1885 1886 1893 1894 1901 1902 1909 1910 1917 1918 1925 1926 1933 1934 1941 1942 1949 1950 1957 1958 1965 1966 1973 1974 1981 1982 1989 1990 1997 1998 2005 2006 2013 2014 2021 2022 2029 2030 2037 2038 2045 2046 1799 1807 1815 1823 1831 1839 1847 1855 18'53 1871 1879 1887 1895 1903 1911 1919 1927 1935 1943 1951 1959 1967 1975 1983 1991 1999 2007 2 015 2023 2031 2039 2047 3000 t 3777 (Octal) 1536 t 2047 (Decimal) A-4

Octal-Decimal nteger Cnversin Table 4000 2048 t 10 4777 2559 (Ocll) tdecimal! Octal Decimal 10000 4096 20000 8192 30000 12288 40000 16384 50000 20480 60000 24576 70000 28672 5000 2560 t t 5777 3071 (Ocll) (Deciml) 0 4000 2048 4010 2056 4020. 2064 4030 2072 4040 2080 4050 2088 4060 2Q96 4070 2104 4100 2112 4110 2120 4120 2128 4130 2136 4140 2144 4150 2152 4160 2160 4170 2168 4200 2176 4210 2184 4220 2192 4230 2200 4240 2208 4250 2216 4260 2224 4270 2232 4300 2240 4310 2248 4320 2256 4330 2264 4340 2272 4350 2280 4360 2288 4370 2296 0 5000 2560 5010 2568 5020 2576 5030 2584 5040 2592 5050 2600 5060 2608 5070 2616 5100 2624 5110 2632 5120 2640 5130 2648 5140 2656 5150 2664 5160 2672 5170 2680 5200 2688 5210 2696 522012704 5230\2712 5240,2720 5250! 2728 5260 2736 5270 2744 5300 2752 5310 2760 5320 2768 5330 2776 5340 2784 5350 2792 5360 2800 5370 2808 1 2 3 2049 2050 2051 2057 2058 2059 2065 2066 2067 2073 2074 2075 2081 2082 2083 2089 2090 2091 2097 2098 2099 2105 2106 2107 2113 2114 2115 2121 2122 2123 2129 2130 2131 2137 2138 2139 2145 2146 2147 2153 2154 2155 2161 2162 2163 2169 2170 2171 2177 2178 2179 2185 2186 2187 2193 2194 2195 2201 2202 2203 2209 2210 2211 2217 2218 2219 2225 2226 2227 2233 2234 2235 2241 2242 2243 2249 2250 2251 2257 2258 2259 2265 2266 2267 2273 2274 2275 2281 2282 2283 2289 2290 2291 2297 2298 2299 2 3 2561 2562 2563 2569 2570 2571 2577 2578 '2579 2585 2586 2587 2593 2594 2595 2601 2602 2603 2609 2610 2611 2617 2618 2619 2625 2626 2627 2633 2634 2635 2641 2642 2643 2649 2650 2651 2657 2658 2659 2665 2666 2667 2673 2674 2675 2681 2682 2683 2689 2690 2691 2697 2698 2699 2705 2706 2707 2713 2714 2715 2721 2722 2723 2729 2730 2731 2737 2738 2739 2745 2746 2747 2753 2754 2755 2761 2762 2763 2769 2770 2771 2777 2778 2779 2785 2786 2787 2793 2794 2795 2801 2802 2803 2809 2810 2811 4 5 6 7 2052 2053 2054 2055 2060 2061 2002 2063 2068 2069 2070 2071 2076 2077 2078 2079 2084 2085 2086 2087 2092 2093 2094 2095 2100 2101 2102 2103 2108 2109 2110 2111 2116 2117 2118 2119 2124 2125 2126 2127 2132 2133 2134 2135 2140 2141 2142 2143 2148 2149 2150 2151 2156 2157 2158 2159 2164 2165 2166 2167 2172 2173 2174 2175 2180 2181 2182 2183 2188 2189 2190 2191 2196 219';' 2198 2199 2204 2205 2206 2207 2212 2213 2214 2215 2220 2221 2222 2223 2228 2229 2230 2231 2236 2237 2238 2239 2244 2245 2246 2247 2252 2253 2254 2255 2260 2261 2262 2263 2268 2269 2270 2271 2276 2277 2278 2279 2284 2285. 2286 2287 2292 2293 2294 2295 2300 2301 2302 2303j - ---'1 4 5 6 7 2564 2565 2566 25671 2572 2573 2574 2575 2580 2581 25~2 2583 2588 258~ 2590 2591 2596 2597 2598 2599 2604 2605 2606 2607 1 2612 2613 2614 2615 2620 ~21 2622 2623 2628 2629 2630 2631 2636 2637 2638 2639 2644 2645 2646 2647 2652 2653 2654 2655 2660 2661 2662 2663 2668 2669 2670 2671 2676 2677 2678 2679 2684 2685 2686 2687 2692 2693 2694 2695 2700 2701 2702 2703 2708 2709 2710 2711 2716 2717 2718 2719 2724 2725 2726 2727 2732 2733 2734 2735 2740 2741 2742 2743 2748 2749 2750 2751 2756 2757 2758 2759 2764 2765 2766 2767 2772 2773 2774 2775 2780 2781 2782 2783 2788 2789 2790 2791 2796 2797 2798 2799 2804 2805 2806 2807 2812 2813 2814 2815 0 1 2 3 4 5 6 7 4400 2304 2305 2306 2307 2308 2309 2310 2311 4410 2312 2313 2314 2315 2316 2317 2318 2319 4420 2320 2321 2322 2323 2324 2325 2326 2327 4430 2328 2329 2330 2331 2332 2333 2334 2335 4440 2336 2337 2338 2339 2340 2341 2342 23<43 445012344 2345 2346 2347 2348 2349 2350 2351 4460 2352 2353 2354 2355 2356 2357 2358 2359 4470 2360 2361 2362 2363 2364 2365 2366 2367 4500 2368 2369 2370 2371 2372 2373 2374 2375 4510 2376 2377 2378 2379 2380 2381 2382 2383 4520 2384 2385 2386 2387 2388 2389 2390 2391 4~30 2392 2393 2394 2395 2396 2397 2398 2399 4540 2400 2401 2402 2403 2404 2405 2406 2407 4550 2408 2409 2410 2411 2412 2413 2414 2415 4560 2416 2417 2418 2419 2420 2421 2422 2423 4570 2424 2425 2426 2427 2428 2429 2430 2431 4600 2432 2433 2434 2435 2436 2437 2438 2439 4610 2440 2441 2442 2443 2444 2445 2446 2447 4620 2448 2449 2450 2451 2452 2453 2454 2455 4630 2456 2457 2458 2459 2460 2461 2462 24~3 4640 2464 2465 2466 24,67 2468 2469 2470 2471 4650 2472 2473 2474 2475 2476 2477 2478 2479 4660 2480 2481 2482 2483 2184 2485 2486 2487 4670 2488 2489 2490 2491 2492 2493 2494 2495 4700 2.496 2497 2498 2499 2500 2501 2502 2503 4710 2504 2505 2506 2507 2508 2509 2510 2511 4720 2512 2513 2514 2515 2516 2517 2518 2519 4730 2520 2521 2522 2523 2524 2525 2526 2527 474012528 2529 2530 2531 2532 2533 2534 2535 4750 2536 2537 2538 2539 2540 2541 2542 2543 4760,2544 2545 2546 2547 2548 2549 2550 2551 14770! 2552 2553 2554 2555 2556 2557 2558 2559 0 1 2 3 4 5 6 7 540012816 2817 2818 2819 2820 2821 2822 2823 54101282' 2825 2826 2827 2828 2829 2830 2831 5420 2832 2'333 2834 2835 2836 2837 2838 2839 5430 2840 2841 2842 2843 2844 2845 2846 2847 5440 2848 2849 2850 2851 2852 2853 2854 2855 5450 2856 2857 2858 2859 2860 2861 2862 2863 5460 2864 2865 2866 2867 2868 2869 2870 2871 5470 2872 2873 2874 2875 2876 2877 2878 287U 5500 2880 2881 2882 2883 2884 2885 2886 288"/ 5510 2888 2889 2890 2891 2892 2893 2894 2895 5520 2896 2897 2898 2899 2900 2901 2902 2903 5530 2904 2905 2906 2907 2908 2909 2910 2911 5540 2912 2913 2914 2915 2916 2917 2918 2919 5550 2920 2921 2922 2923 2924 2925 2926 2927 5560 2928 2929 2930 2931 2932 2933 2934 2935 5570 2936 2937 2938 2939 2940 2941 2942 2943 5600 2944 2945 2945 2947 2948 2949 2950 2951-5610 12952 2953 2954 2955 2956 2957 2958 2959 562012960 2961 2962 2963 2964 2965 2966 2967 5630 2968 2969 2970 2971 2972 2973 2974 2975 564012976 2977 2978 2979 2980 2981 2982 2983 5650 2984 2985 2986 2987 2988 2989 2990 2991 5660 2992 2993 2994 2995 2996 2997 2998 2999 5670 3000 3001 3002 3003 3004 3005 3006 3007 ~700 3008 3009 3010 3011 3012 3013 3014 3015 5710 3016 3017 3018 3019 3020 3021 3022 3023 5720 3024 3025 3026 3027 3028 3029 3030 3031 5730 3032 3033 3034 3035 3036 3037 3038 3039 5740 3040 3041 3042 3043 3044 3045 3046 3047 5750 3048 3049 3050 3051 3052 3053 3054 3055 5760 3056 3057 3058 3059 3060 3061 3062 3063 5770 3064 3065 3066 3067 3068 3069 3070 3071 A-5

Octal-Decimal nteger Cnversin Table 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 6000 3072 3073 3074 3075 3076 3077 3078 3079 6010 3080 3081 3082 3083 3084 3085 3086 3087 6020 3088 3089 3090 3091 3092 3093 3094 3095 6030 3096 3097 3098 3099 3100 3101 3102 3103 6040 3104 3105 3106 3107 3108 3109 3110 3111 6050 3112 3113 3114 3115 3116 3117 3118 3119 6060 3120 3121 3122 3123 3124 3125 3126 3127 6070 3128 3129 3130 3131 3132 3133 3134 3135 6100 3136 3137 3138 3139 3140 3141 3142 3143 6110 i 3144 3145 3146 3147 3148 3149 3150 3151 612013152 3153 3154 3155 3156 3157 315B 3159 6130,3160 3161 3162 3163 3164 3165 3166 3167 6140 3168 3169 3170 3171 3172 3173 3174 3175 6150 3176 3177 3178 3179 3180 3181 3182 3183 6160 3184 3185 3186 3187 3188 3189 3190 3191 6170 3192 3193 3194 3195 3196 3197 3198 3199 16200 3200 3201 3202 3203 3204 3205 3206 3207 06210 3208 3209 3210 3211 3212 3213 3214 3215 6220 3216 3217 3218 3219 3220 3221 3222 3223 6230 3224 3225 3226 3227 3228 3229 3230 3231 6240 3232 3233 3234 3235 3236 3237 3238 3239 6250 3240 3241 3242 3243 3244 3245 3246 3247 6260 3248 3249 3250 3251 3252 3253 3254 3255 6270 3256 3257 3258 3259 3260 3261 3262 3263 6300 3264 3265 3266 3267 0 3268 3269 3270 3271 6310 3272 3273 3274 3275 3276 3277 3278 3279 6320 3280 3281 3282 3283 3284 3285 3286 3287 6330 3288 3289 3290 3291 3292 3293 3294 3295 6340 3296 3297 3298 3299 3300 3301 3302 3303 6350 3304 3305 3306 3307 3308 3309 3310 3311 636013312 3313 3314 3315 3316 3317 3318 33191 6370 3320 3321 3322 3323 3324 3325 3326 3~ 6400 3328 3329 6410 3336 3337 6420 3344 3345 6430 3352 3353 6440 3360 3361 6450 3368 3369 6460 3376 3377 6470 3384 3385 6500 3392 3393 6510 3400 3401 652013408 3409 6530 3416 3417 6540 3424 3425 6550 3432 3433 6560 3440 3441 6570 3448 3449 6600 3456 3457 6610 3464 3465 6620 3472 3473 6630 3480 3481 6640 3488 3489 6650 3496 3497 6660 3504 3505 6.670 3512 3513 6700 3520 3521 6710 3528 3529 6720 3536 3537 6730 3544 3545 6740 3552 3553 6750 3560 3561 6760 3568 3569 6770 3576 3577 3330 3331 3332 3338 3339 3340 3346 3347 3348 3354 3355 3356 3362 3363 3364 3370 3371 3372 3378 3379 3380 3386 3387 3388 3394 3395 3396 3402 3403 3404 3410 3411 3412 3418 3419 3420 3426 3427 3428 3434 3435 3436 3442 3443 3444 3450 3451 3452 3458 3459 3460 3466 3467 3468 3474 3475 3476 3482 3483 3484 3490 3491 3492 3498 3499 3500 3506 3507 3508 3514 3515 3516 3522 3523 3524 3530 3531 3532 3538 3539 3540 3546 3547 3548 3554 3555 3556 3562 3563 3564 3570 3571 3572 3578 3579 3580 3333 3334 3341 3342 3349 3350 3357 3358 3365 3366 3373 3374 3381 3382 3389 3390 3397 3398 3405 3406 3413 3414 3421 3422 3429 3430 3437 3438 3445 3446 3453 3454 3461 3462 3469 3470 3477 3478 3485 3486 3493 3494 3501 3502 3509 3510 3517 3518 3525 3526 3533 3534 3541 3542 3549 3550 3557 3558 3565 3566 3573 3574 3581 3582 3335 3343 3351 3359 3367 3375 3383 3391 3399 3407 3415 3423 3431 3439 3447 3455 3463 3471 3479 3487 3495 3503 3511 3519 3527 3535 3543 3551 3559 3567 3575 3583 6000 3072 t t 6777 3583 (Octal) (Decimal) Octal Decimal 10000-4096 20000-8192 30000-12288 40000-16384 50000-20480 60000-24576 70000-28672 a 1 2 3 4 5 6 7 7000 3584 3585 3586 3587 3588 3589 3590 3591 7010 3592 3593 3594 3595 3596 3597 3598 3599 7020 3600 3601 3602 3603 3604 3605 3606 3607 7030 3608 3609 3610 3611 3612 3613 3614 3615 7040 3616 3617 3618 3619 3620 3621 3622 3623 7050 3624 3625 3626 3627 3628 3629 3630 3631 7060 3632 3633 3634 3635 3636 3637 3638 3639 7070 3640 3641 3642 3643 3644 3645 3646 3647 7100 3648 3649 3650 3651 3652 3653 3654 3655 7110 3656 3657 3658 3659 3660 3661 3662 3663 7120 3664 3665 3666 3667 3668 3669 3670 3671 7130 3672 3673 3674 3675 3676 3677 3678 3679 7140 3680 3681 3682 3683 3684 3685 3686 3687 7150 3688 3689 3690 3691 3692 3693 3694 3695 7160 3696 3697 3698 3699 3700 3701 3702 3703 7170 3704 3705 3706 3707 3708 3709 3710 3711 7200 3712 3713 3714 3715 3716 3717 3718 3719 7210 3720 3721 3722 3723 3724 3725 3726 3727 7220 3728 3q29 3730 3731 3732 3733 3734 3735 7230 3736 3737 3738 3739 3740 3741 3'742 3743 7240 37044 3745 3746 374'1 3748 3149 3750 3751 7250 3752 3753 3754 3755 3756 3757 3758 3759 7260 :1750 3761 3762 3763 3764 3765 3766 3767 7270 3168 3769 3770 3771 3772 3773 3774 3775 7300 3776 3777 3778 3779 3780 3781 3782 3783 7310 3784 3785 3786 3787 3788 3789 3790 3791 7320 3792 3793 3794 3795 3796 3797 3798 3799 7330 3800 3801 3802 3803 3804 3805 3806 3807 ~340 3808 3809 3810 3811 3812 3813 3814 3815 73)0 3816 3817 3818 3819 3820 3821 3822 3823 7360 3824 3825 3826 3827 3828 3829 3830 3831 7370 3832 3833 3834 3835 3836 3837 3838 3839 0 1 7400 3840 3841 7410 3848 3.849 7420 3856 3857 7430 3864 3865 7440 3872 3873 7450 3880 3881 7460 3888 3889 7470 3896 3897 7500 3904 3905 7510 3912 3913 7520 3920 3921 7530 3928 3929 7540 3936 3937 7550 3944 3945 7560 3952 3953 7570 3960 3961 7600 3968 3969 7610 3976 3977 7620 3984 3985 7630 3992 3993 7640 4000 4001 7650 4008 4009 7660 4016 4017 7670 4024 4025 7700 4032 4033 7710 4040 4041 7720 4048 4049 7730 4056 4057 7740 4064 4065 7750 4072 4073 7760 4080 4081 7770 4088 4089 2 3 4 3842 3843 3844 3850 3851 3852 3858 3859 3860 3866 3867 3868 3874 3875 3876 3882 3883 3884 3890 3891 3892 3898 38il9 3900 3906 3907 3908 3914 3915 3916 3922 3923 3924 3930 3931 3932 3938 3939 3940 3946 3947 3948 3954 3955 3956 3962 3963 3964 3970 3971 3972 3978 3979 3980 3986 3987 3988 3994 3995 3996 4002 4003 4004 4010 4011 4012 4018 4019 4020 4026 4027 4028 4034 4035 4036 4042 4043 4044 4050 4051 4052 4058 4059 4060 4066 4067 4068 4074 4075 4076 4082 4083 4084 4090 4091 4092 5 6 3845 3846 3853 3854 3861 3862 3869 3S70 3877 3878 3885 3886 3893 3894 3901 3902 3909 3910 3917 3918 3925 3926 3933 3934 3941 3942 3949 3950 3957 3958 3965 3966 3973 3974 3981 3982 3989 3990 3997 3998 4005 4006 4013 4014 4021 \022 4029 4030 4037 4038 4045 4046 4053 4054 4061 4062 4069 4070 4077 4078 4085 4086 4093 4094 7 3847 3855 3863 3871 3879 3887 3895 3903 3911 3919 3927 3935 3943 3951 3959 3967 3975 3983 3991 3999 4007 4015 4023 4031 4039 4047 4055 4063 4071 4079 4087 4095 7000 3584 t 10 7777 4095 (Octal) (Decimal) A-6

OCTAL DECMAL FRACTON CONVERSON TABLE 'OCTAL DEC. OCTAL Dl::C. OCTAL DEC. OCTAL m:c..000.000000.100.125000.200.250000.300.375000.001.001953.101.126953.201.251953.301 37G953.002.1t03906.102.128906.202.253906.302.378906.003.005859.103.130859.203.255859.303.380859.004.007812.104.132812.204.257812.304.382812.005.009765.105.134765.205.259765.305.384765.006.011718.106.136718.206.261718.306.386718.007.013671.107.138671.207.263671.307.388671.010.015625.110.140625.210.265625.310.390625.011.017578.111.142578.2ll.267578.311.392578.012.019531.112.144531.212.269531.312.394531.013.021484.113.146484.213.271484.313.396484.014.023437.114.148437.214.273437.314.398437.015.025390.115.150390.215.275390.315.400390.016.027343.116.152343.216.277343.316.402343.017.029296.117.154296.217.279296.317.404296.020.031250.120.156250.220.281250.320.406250.021.033203.121.158203.221.283203.321.408203.022.035156.122.160156.222.285156.322.410156.023.037109.123.162109.223.287109.323.412109.024.039062.124.164062.224.289062.324.414062.025.041015.125.166015.225.291015.~25.416015.026.042968.126.167968.226.29296'8.326.417968.027.044921.127.169921.227.294921.327.419921.030.046875.130.171875.230.296875.330.421875.031.048828.131.173828.231.298828.331.423828.032.050781.132.175781.232.300781.332.425781.033.052734.133.177734.233.302734.333.427734.034.054687.134.179687.234.304687.334.. 429687.035.056640.135.181640.235.306640.335.431640.036.058593.136.183593.236.308593.336.433593.037.060546.137.185546.237.310546.337.435546.040.062500.140.187500.240.312500.340.437500.041.064453.141.189453.241.314453.341.439453.042.066406.142.191406.242.316406.342.441406.043.068359.143.193359.243.318359.343.443359.044.070312.144.195312.244.320312.344.445312.045.072265.145.197265.245.322265.345.447265.046.074218.146.199218.246.324218.346.449218.047.076171.147.201171.247.326171.347.451171.050.078125.150.203125.250.328125.350.453125.051.080018.151.205078.251.330078.351.455078.052.082031.152.207031.252.332031.352.457031.053.083984.153.208984.253.333984.353.458984.054.085937.154.210937.254.335937.354.460937.055.087890.155.212890.255.337890.355.462890.056.089843.156.214843.256.339843.356.464843.057.091796.157.216796.257.341796.357.466"196.060.093750.160.218750.260.343750.360.468750.061.095703.161.220703.261.345703.361.470703.062.097656.162.222656.262.347656.362.472656.063.099609.163.224609.263.349609.363.474609.064.101562.164.226562.264.351562.364.416562.065.103515.165.228515.265.353515.365.478515.066.105468.166.230468.266.355468.366.460468.067.107421.167.232421.267.357421.367.482421.070.109375.170.234375.270.359375.370.484375.071.111328.171.236328.271.361328.371.486328.072.113281.172.238281.272.363281.372.48821\1.073.115234.173.240234.273.365234.373.490234.074.117187.174.242187.274.367187.374.492187.075.119140.175.244140.275.369140.375.494140.076.121093.176.246093.276.371093.376.496093.077.123046.177 ~ 248046.277.373046.377.498046.. ' A-7

Octal-Decimal Fractin Cnversin Table OCTAL DEC. OCTAL DEC. OCTAL DEC. OCTAL DEC 000000.000000.000100.000244.000200.000488.000300.000732.000001.000003.000101.000247.000201.000492.000301.000736.000002,000007.000102.000251.000202.000495.000302.000740.000003.000011.000103.000255.000203.000499.000303.000743,000004.000015.000104.000259.000204.000503.000304.000747.000005.000019.000105.000263.000205.000507.000305.000751.000006.000022.000106.000267.000206.000511.000306.000755.000007.000026.000107.000270.000207.000514.000307.000759.000010.000030,000110.000274.000210.000518.000310.000762.000011.000034.000111.000278.000211.000522.000311.000766.000012.000038.000112.000282.000212.000526.000312.000770.000013.000041.000113.000286.000213.000530.000313.000774.000014.000045.000114.000289.000214.000534.000314.000778.000015.000049.000115.000293.000215.000537.000315.000782.000016.000053.000116.000297.000216.000541.000316.000785.000017 QOO057.000117.000301.000217.000545.000317.000789.000020.000061,000120.000305.000220.000549.000320.000793.000021.000064.000121.000308.000221.000553.000321.000797.000022.000068.000122.000312,000222.000556.000322.000801,000023.000072,000123,000316,000223.000560.000323.000805.000024.000076.000124.000320.000224.000564.000324.000808.000025.000080.000125.000324.000225.000568.000325.000812.000026.000083.000126,000328.000226.000572.000326.000816.000027.000087.000127.000331,000227.000576.000327.000.820.000030.000091.000130.000335.000230.000579.000330.000823.000031.000095,000131.000339.000231.000583.000331.000827.000032.000099.000132.000343.000232.000587.000332.000831.000033.000102.000133.000347.000233.000591.000333.000835.000034.000106.000134.000350.000234.000595.000334.000839.000035.000110.000135.000354.000235.000598.000335.000843.000036.000114.000136.000358.000236.000602.000336.000846.000037.000118.000137.000362.000237.000606.000337.000850.000040.000122.000140.000366.000240.000610.000340.000854.000041.000125.000141.000370.000241.000614.000341.000858.000042.000129.000142.000373.000242.000617.000342.000862.000043.000133.000143.000371.000243.000621.000343.000865.000044.000131.000144.000381.000244.000625.000344.000869.000045.000141.000145.000385,000245.000629.000345.000873.000046.000144.000146,000389,000246.000633.000346.000877.000047.000148.000147.000392.000247.000637.000347.000881.000050.000152.000150,000396.000250.000640.000350.000885.000051.000156.000151.000400.000251.000644.000351.000888.000052.000160.000152.000404.000252.000648.000352.OG0892.000053.000164.000153,000408.000253.000652.000353.000896.000054.000167.000154.000411.000254.000656.000354.000900.000055.000171.000155.000415.000255.000659.000355.000904.000056.000175.000156.000419.000256.000663.000356.000907.000057.000179.000157.000423.000257.000667.000357.000911.000060.000183.000160.000427.000260,000671.000360.000915.000061.000186.000161.000431.000261.000675.000361.000919.000062.000190.000162.000434.000262.000679.000362.000923.000063.000194.000163.000438.000263.000682.000363.000926.000064.000198.000164.000442.000264.000686.000364.000930.000065.000202.000165.000446.000265.000690.000365.000934.000066.000205.000166.000450.000266.000694.000366.000938.000067.000209.000167.000453.000267.000698.000367.000942.000070.000213.000170.000457.000270.000701.000370.000946.000071.000217.000171.000461.000271.000705.000371.000949.000072.000221.000172.000465.000272.000709.000372.000953.000073.000225.000173.000469.000273.000713.000373.000957.000074.000228.000174.000473.000274.000717.000374.000961.000075.000232.000175.000476.000275.000720.000375.000965.000076.000236.000176.000480.000276.000724.000376.000968.000077.000240.000177.000484.000277.000728.000377.000972 A-a

Octal-Decimal Fradin Cnversin Table OCTAL DEC. OCTAL DEC. OCTAL DEC. OCTAL DEC..000400.000976.000500.001220.000600.001464.000700.001708.000401.000980.000501.001224.000601.001468.000701.001712.000402.000984.000502.00122-8.00060'2.001472.000702.001716.000403.000988.000503.001232.000603.001476.000703.001720.000404.000991.000504.001235.000604.001480.000704.001724.000405.000995.000505.001239.000605.001483.000705.001728.000406.000999.000506.001243.000606.001487.000706.001731.000407.001003.000507.001247.000607.001491.000707.001735.000410.001007.000510.001251.000610.001495.000710.001739.000411.001010.000511.001255.000611.001499.000711.001743.000412.001014.000512.001258.000612.001502.000712.001747.000413.001018.000513.001262.000613.001506.000713.001750.000414.001022.000514.001266.000614.001510.000714.001754.000415.001026.000515.001270.000615.001514.000715.001758.000416.001029.000516.001274.000616. 001518.000716.001762.000417.001033.000517.001277.000617.001522.000717.001766.000420.001037.000520.001281.000620.001525.000720.001770.000421.001041.000521.001285.000621.001529.000721.001773.000422.001045.000522.001289.000622.001533.000722.001777.000423.001049.000523.001293.000623.001537.000723.001781.000424.001052.000524.001296.000624.001541.000724.001785.000425.001056.000525.001300.000625.001544.000725.0017t19.000426.001060.000526.001304.000626.001548.000726.001792.000427.001064.000527.001308.000627.001552.000727.001796.000430.001068.000530.001312.000630.001556.000730.001800.000431.001071.000531.001316.000631.001560.000731.001804.000432.001075.000532.001319.000632.001564.000732.001808.000433.001079.000533.001323.000633.001567.000733.0018ll.000434.001083.000534.001327.000634.001571.000734.001815.000435.001087.000535.001331.000635.001575.000735.001819.000436.001091.000536.001335.000636.001579.000736.001823.000437.001094.000537.001338.000637.001583.000737.001827.000440.001098.000540.001342.000640.001586.000740.001831.000441.001102.000541.001346.000641.001590.000741.001834.000442.001106.000542.001350.000642.001594.000742.001838.000443.001110.000543.0'01354.000643.001598.000743.001842.000444.001113.000544.001358.000644.001602.000744.001846.000446.001117.000545.001361.000645.001605.000745.001850.000446.001121 000546.001365.000646.001609.000746.001853.000447.001125.000547.001369.000647.001613.000747.001857.000450.001129.000550.001373.000650.001617.000750.001861.000451.001132.000551.001377.000651.001621.000751.001865.000452.001136.000552.001380.000652.001625.000752.001869.000453.001140.000553.001384 QO{)653.001628.000753.001873.000454.001144.000554.001388.000654.001632.000754.001876.000455.001148.000555.001392.000655.001636.000755.001880.000456.001152.000556.001396.00'0656.001640.000756.001884.000457.001155.000557.001399.000657.001644.000757.001888.000460.001159.000560.001403.000660.001647.000760.001892.000461.001163.000561.001407.000661.001651.000761.001895.000462.001167.000562.001411.000662.001655.000762.001899.000463.001171.000563.001415.000663.001659.000763.001903.000464.001174.000564.001419.000664.001663.000764.001907.000465.001178.000565.001422.000665.001667.000765.001911.000466.001182.000566.001426.000666.001670.000766.001914.000467.001186.000567.001430.000667.001674.000767.001918.000470.001190.000570.001434.000670.001678.000770.001922.000471.001194.000571.001438.000671.001682.00.0771.001926.000472.001197.000572.001441.000672.001686.000772.001930.000473.001201.000573.001445.000673.001689.000773.001934.000474.001205.000574.001449.000674.001693.000774.001937.000475.001209.000575.001453.000675.001697.000775.001941.000476.001213.000576.001457.000676.0017.Dl.000776.001945.000477.001216.000577.001461.000677.001705.000777.001949 A-9

TWO'S COMPLEMENT ARTHMETC SDS cmputer systems hld numbers in memry in tw's cmplement frm. Single-precisin numbers have 23 magnitude bits and a sign bit. The sign bit is in the first bit psitin t the left f the mst significant f the magnitude bits. Thus, the sign bit actually is a part f the number in all arithmetic peratins. A "0" bit dentes a psitive sign and a 11111 bit dentes a negative sign. n this system, the negative f a number is its tw's cmplement. An algrithm fr finding the tw's cmplement f a binary number with attached sign bit is: T find the tw's cmplement f the binary number B that has.!l significant bits including the sign bit, subtract it frm the number 2 n expressed in binary frm. This latter number is a "1 11 fllwed by nzers. EXAMPLES: The fllwing example indicates the tw's cmplement f binary numbers held in five bits plus a sign bit. Their decimal equivalents are n the left. Decimal Binary Negative f Tw's Cmplement Number Equivalent Decimal Number f Binary Equivalent,+ 2 +14 000010 001110-2 -14 111110 110010 n the additin example belw, decimal ntatin is n the left and binary ntatin n the right. +20-03 +17 010100.lll!Ql 010001 n the cmputer, 24-bit numbers are written as eight ctal digits fr cnvenience. The fllwing example shws three frms f the same additin -- decimal, binary, and ctal, respectivel y. The binary number is assumed t be an integer. Decimal Binary Octal As the examples indicate, the sign bit is an integral part f the number t which it is attached and its value, plus r minus, is autmatically taken care f during the use f tw's cmplement arithmetic. This prperty is used when numbers f different length are added. Fr example, assume that these tw signed, tw's cmplemented, negative numbers f 6-bit at.1d 3-bit length are added: Decimal -21-03 -24 101011 101 11 0000 = - 16 10 Ntice that the third least significant bit f the first number is added t the sign bit f the secnd number causing an errneus result. This errr is crrected by filling in the empty, mst significant bit psitins with the value f the sign bit f the shrter number: Decimal -21-03 -24 Th is prperty suggests: Binary 101011 111101 101000 = -24 10 1) Fill ing the empty bit psitins with the sign value f a psitive number, that is, zers, has n changing effect n the result,and 2) f the tw's cmplement is taken by the methd suggested, where n is the larger number's length, the sign value is ~tmatically appended t the smaller number. Fr instance, in the abve example, if the cmplement f 03 is taken using n = 6, 1000000 011 111101 +21 000000000000000000010101-03 111111111111111111111101 +18 000000000000000000010010 00000025 77777775 00000022 the sign is prperly appended t the number. This prcedure is called lextending li the sign f a number. A-lO

OPTONAL EQUPMENT REAL-TME CLOCK The Real-Time Clck (RTC) prvides a highly flexible timerientatin system fr the SDS 92 Cmputer. t derives time pulses frm the 60-cycle cmputer pwer supply. These pulses are then used t prduce a timing mark every 16.67 mi isecnds r ptinally every 8.33 millisecnds. The Real-Time Clck can als accept timing marks frm a custmer-supplied input, thereby allwing time measurement t any required reslutin fr special applicatins. These timing marks are supplied at standard SDS lgic levels t the cmputer's RTC circuitry. The timing marks are then used by the cmputer and its interrupt system t prvide either an elapsed-time cunter r a cntinuusly incrementing time cunter depending n the needs f the custmer. The RTC wi perate in either mde depending nly n the cmputer's stred prgram. Tw pairs f lcatins f pririty interrupts are prvided with the RTC. These are as fllws: Lcatin 164 166 Nrmal Single nstructin Cmputer 92 92 Descriptin CLOCK SYNC CLOCK PULSE The Clck Pulse and Clck Sync interrupts functin tgether t prvide elapsed-time, event-cunter r time-f-day clcks. The Clck Pulse interrupt is a single-instructin interrupt. (Nte: See Single nstructin nterrupts in Sectin.) An MPO instructin is usually placed in the Clck Pulse interrupt lcatin. When MPO is used as a single-instructin interrupt subrutine, it causes the cntents f the effective address t be incremented by ne but it des nt alter the current cntent f the flag. Furthermre, if the new (incremented) cntents f the effective address is 0000, a Clck Sync interrupt is generated. The Clck Sync interrupt can be generated in n ther way. ELAPSED-TME CLOCK The elapsed-time c lck times the length f a prgram r subrutine, r initiates r discntinues prcessing at prgramdetermined time intervals. An arbitrary memry lcatin is reserved as a cunter. When initialized, this cell cntains the 2's cmplement f the number f time intervals t be cunted. The Clck Pulse interrupt lcatin cntains an MPO instructin. Each Clck Pulse interrupt results in incrementing the clck cunt by ne. When the cunt is finished, an interrupt t the Clck Sync lcatin ccurs. A supervisry r ther apprpriate cntrl prgram can then be entered t perfrm the custmerdesired peratin. CONTNUOUS LY NCREMENTNG CLOCK The cntinuusly incrementing clck maintains "time-f-day" fr the cmputer. Tw memry lcatins serve t cunt the timing marks. n this case, the Clck Pulse is used t increment the least significant twelve bits f the cunt. (The Clck Pulse interrupt lcatin cntains an MPO instructin.) The Clck Sync is used t increment the mst significant twelve bits f the cunt. (The Clck Sync interrupt subrutine includes an MPO instructin.) A simple, straightfrward subrutine can be entered t recnstruct the exact time-f-day frm this twenty-fur bit cunt. ARM/DSARM The Clck Pulse interrupt can be armed and disarmed with these instructins: EOM Effective Address Actin 20200 20100 The Clck Sync interrupt is always armed. AUTOMATC POWER FAL-SAFE SYSTEM Disarm Clck Pulse nterrupt Arm Clck Pu se nterrupt The cmputer cre memry hlds its infrmatin with all pwer remved, but infrmatin in the cmputer registers is destryed by lss f pwer. Upn fai lure f main pwer t the cmputer, this system prvides that the cntents f all registers and ther vlati e infrmatin are autmatically stred in cre memry; als, further writing int cre strage is inhibited durrng the decay perid f the cmputerdc pwer supplyutputs. Errneus memry cntrl is prevented during pwer-ff and pwer-n peratins. Pwer-ff/-n interrupt rutines permit prper resumptin f a prgram, autmatically, after pwer is restred. The system cnsists f relay-cntrlled, ac pwer-sensing and memry-sequencing circuitry, tw high-pririty interrupt channels, and a "shut-dwn/start-up" prgramming sequence. The Sense External Signal (SES) instructin is an aid in prgramming this ptin. ts effective address is 24000. f the OFF interrupt (152) has just ccurred, this SES sets the Flag. DATA MULTPLEXNG SYSTEM NTRODUCTON The standard /O systems prvided with the SDS 92 Cmputer prvide fr peratin with all standard SDS peripheral equipments and fr high-perfrmance special devices. The Data Multiplexing System prvides an alternate /O system that is f particular use in dealing with multiple surces f data and fr systems which may have data rates frm lw t very high. The SDS 92 Cmputer has essentially tw majr paths alng wh ich /O data can flw t and frm memry. The fi rst path is the same that is used by the main frame itself. The B-1

PN BP POT BPO Pririty nterrupts Central Prcessr Basic /O Channel First Path Memry..-- Fixed Lcatin nterlace Cntr 1--"-'-- Wrds fr the Attached DSCs 1-----... -... Memry Parity. Checking Optin ---- -- -- -- -- -- -~e::; P:;- -------- ---- Data Multiplexing System 1 L ElN Pririty nterrupt Data Multiplex Channel Address Register nput 1. Data 2. Addresses 3. 4-Bit Functin Cdes DSC- Data Register Data Register 6-Bit Characters (lr 2 per 12-Bit Wrd) 12-Bit Characters Output 1. Data 2. Cntrl 12- r 24-Bit Characters DSC Pririty DSC 11* -P-ri-~i-tY-~t-e-rr-u~~ - - ~ ~--.-----~------... -------- Char. Register UnitAddress ""'--"-"~ ElN 1 t /O DEVCE Data/cntm~ - * N strage reg i sters. ---,' ~~S ~ Pririty nterrupt ------.1 SDS 92 Cmputer Cnfiguratin B-2

PN/POT peratins use the first path. The basic /O channel als uses this path. n additin t this path, which is primari y under the cntrl f the main frame, there is an ptinal secnd path that is cmpletely under the cntrl f the units attached t it. The secnd path has pririty ver the first fr access t memry. This path is made available with the installatin f a Data Multiplexing System. The Data Multiplexing System (DMS) cnsists f a Data Multiplex Channel (DMC) and ne r mre Data Subchannels (DSC). A maximum f 64 subchannels are allwed. Transmissin between a DSC and cmputer memry is cntrlled by tw interlace cntrl wrd-pairs unique t the DSC and wired int fixed, adjacent lcatins in memry. During a transmissin, the cntrlling DMC uses these tw wrd-pairs fr cntrl f address and recrd length. Fur DSCs (ne DSC- and three DSC-s) culd be placed in a system as fllws. The DSCs are numbered frm 100, 104,... t 1148' Cntrl wrd quads assc i ated wi th the DSCs are numbered accrd i ng y: 100-103 fr DSC-100, etc. DATA MULTPLEX CHANNEL (DMC) The Data Multiplex Channel is a basic unit fr the Data Multipexing System. t cnnects t the SDS 92 Cmputer via the secnd path t memry. The DMC cntains a 13-bit Data Register, 15-bit Address Register, and cntrl lgic t enable the DMS t perfrm a variety f functins. The data and address are cnnected t memry when a transfer f infrmatin is imminent. Prgram cntrl required fr input/utput perates directly n the individual Data Subchannel (DSC), nt n the DMC. When external data addresses are prvided t the DMC, the DMC transmissins require ne cycle fr each 12-bit wrd transmitted and tw cycles fr each 24-bit duble wrd transmitted. The DMC has an internal interlace feature. This feature allws subchannels t specify the addresses f wrd pairs in memry where the data address and cunt are lcated. When perating with internal interlace, the subchannel supplies the address f its assciated interlace cntrl wrds instead f the actual data address. The DMC accesses the interlace wrd pair, increments the address prtin, decrements the wrd cunt, restres mdified wrds, and then accepts data frm, r transmits data t, the requesting subchannel. The DMC als supplies a signal t the subchannel, if the decremented wrd cunt is zer. The frmat f the'internal interlace wrd pair is: --Wrd N+1--1 'Wrd Cunt 8 9-11 1 0 Wrd N---- Data Address The 9-bit wrd cunt permits blck lengths t 512 wrds. Transmissins using internal interlace require five cycles, if the required transmissin is fr a 12-bit wrd, and six cyc les, if the required transmissin is fr a 24-bit duble wrd. The DMC prvides fr autmatic memry incrementing. The cunting capability f the DMC Data Register permits an externally specified memry wrd t be incremented. When such 11 a memry increment peratin is t be perfrmed, the subchannel signals the DMC with a special increment line and supplies the address. Fr memry increments, the DMC accesses memry, increments it, and then restres the wrd. f a memry increment peratin results in an all-zer wrd (r duble wrd), the DMC signals the subchannel. The zer signal may then be used t interrupt the prgram. Memry increments require tw cycles. Cntrl f the varius DMC functins is achieved by fur Functin Cde ines frm the subchannels. The DMC, in cnjunctin with the main frame Memry Parity Checking Optin, insure the integrity f data transmissins. Wrds read frm memry are checked fr parity; parity is generated fr wrds stred in memry; wrds received by the DMC are checked fr prper parity; a parity errr signal is generated by the DMC and sent t the subchannel when an input parity discrepancy is detected. DATA SUBCHANNELS (DSC-N) A number f subchannels can be attached t the DMC. The tw described belw are standard subchannels. Subchannels can cntrl and generate prgram interrupts, but d nt include the interrupt levels themselves. The signl,s must be ruted t ptinal interrupt levels. The subchannels use a pririty scheme t determine which may transmit t the DMC at any given time. Up t 64 DSCs may be cnnected t a DMC. A DSC may use the internal interlace feature f the DMC t cntrl its transmissin, r it may be equipped with an External nterlace (EN). A DSC using internal interlace has tw wrd pairs assigned t it. These tw wrd pairs are lcated in cntiguus memry lcatins and are fixed fr a given subchannel. The prgram may select either the even wrd pair r dd wrd pair lcatin. f the even wrd pair lcatin is selected, the subchannel wi autmatically switch t the dd wrd pair lcatin when the cunt field f the even wrd pair wrd is zer. The prgram can als select whether the subchannel switches back t the even wrd pair when the cunt field f the dd wrd pair is zer. The subchannel generates an interrupt signal when the cunt field f either wrd pair reaches zer. Transmissin terminatin ccurs when the dd wrd pair's cunt equals zer, if the subchannel des nt switch back t the even wrd pair. The tw wrd pai~ internal interlace allws a subchannel t hand e cntinuus data by alternately wrking frm ne memry area r anther. By allwing the subchannel t switch autmatically frm ne interlace wrd pair t the ther, the prgram is relieved f the necessity fr making real-time respnses t the zer cunt cnditin. Using first the even pair then the dd pair interlace wrds allws a maximum transmissin f 1024 wrds r duble wrds. CHARACTER SUBCHANNEL (DSC-) The DSC- cntains a 12-bit data register that can assemble and disassemble tw 6-bit characters, and transmit ne r tw06-bit characters r ne 12-bit character. (DSC- has a unit address B-3

register.) t checks and generates the parity f characters t enable it t cuple with standard SDS peripheral equipment. The subchannel may perate with either internal r external interlace. t has ne mde f utput and tw mdes f input. During utput, it transmitsuntil the dd internal interlace wrd 'pair cunt is zer and then terminates, if interlace cycl ing is nt requested. The utput may als be terminated ifthedevice sends an END signal t the channel. This END signal may cause the DSC- t generate an interrupt t the prgram. nput, like utput, may always be terminated due t an external END signal. TheprgramcanalsspecifythattheDSC terminates and discnnects n zer cunt, r discnnects nly n the END signal. n either case, hwever, all transmissin t memry is terminated after the dd interlace cunt reaches zer, if interlace cycling is nt requested. FULL WORD SUBCHANNEL (DSC-) The DSC- is a general-purpse subchannel, designed t allw any device t be cnnected t it. t cntains n strage fr data. Depending n the Functin Cde prvided t the DMC, the DSC- will permit 12- r 24-bit (plus parity) transmissin between the DMC and external devices cnnected t the DSC-. The external device must be capable f hlding the data during the transm issin t/frm the DMC. (An A-t-D cnverterwu d have such capability.) Like the DSC-, the DSC- can perate with either internal r external interlace. ts peratin in this respect is identical t the DSC-. The DSC- als cntains cntrl lgic t facilitate memry increment peratins in cnjunctin with the DMC. EXTERNAL NTERLACE (EN) The External nterlace can be attached t the DSC t cntrl the transmissin f its data t/frm memry. The EN cnsists f a 15-bit address register and a 9-bit cunt register. These registers are laded autmatically when the subchannel is activated, the infrmatin cming frm the internal interlace memry lcatins. Once the EN is set up, it will cntrl the transm issin f the DSC at a maximum rate f ne wrd per memry cycle. After each wrd is transmitted, the EN increments its address register and decrements its cunt. When the cunt equals zer, the EN signals the DSC, which can then generate a prgram interrupt and/r ntify the external device. Transrn:ssin nrmally terminates n zer cunt. Sequencing f interlace wrds is identical t the sequence f peratins perfrmed fr internal interlace, except that nly fur memry cyc! es are used fr interl ace wrd prcessi ng. The first istaccess the interlace wrd pair initiallyi the secnd is t restre the interlace wrd pair when the cunt reaches zer. MEMORY PARTY NTERRUPTS SDS cmputers incrprate an extensive memry parity checking system. The inclusin f parity generatin and checking circu itry assures the integrity f all data and instructins transferred amng the memry, the central prcessing unit, and input/utput channels. n nrmal peratin a switch n the cmputer cnsle specifies the actin t be perfrmed by the cmputer when a memry parity errr is detected. Tw actins are avai lable: the cmputer halts with the parity indicatr lightedi r the cmputer ignres the parity errr and prceeds with the prgram. n many real-time appl icatins it is desirable t keep the cmputer running when a parity errr isdetected. Als, the prgram must be ntified f the errr withut stpping cmputat in. An ptinal feature prvides this capability by means f tw levels f armed interrupts. One interrupt level is assciated with the central prcessr and the Time-Multiplexed Cmmunicatin Channelsi the ther interrupt level with the Direct Access Cmmunicatin Channels and the Data Multiplexing System. Memry parity errrs detected frm these tw surces prduce a pririty interrupt assciated with the cause. The prcessing rutine assciated with the interrupt can then take apprpriate actin, such as re-initiate the failed peratin, ntify the peratr, renter a diagnstic rutine. Such actin allws memry parity errrs t be recgnized and handled prperly withut hindering the cmputer's perfrmance f realtime r n- ine calculatins. B-4

TRAPPNG RETURN SUBROUTNE EXAMPLE The fllwing cde determines hw many cells (ne r tw) the trapped instructin used: it then increments the subrutine entry accrdingly t prvide the prper return address. has the frm: MUASM F 'CT Unpredictable 3 bits Assume (1) the trap instructin is a multiply simulatr at lcatin 124, and (2) the branch in lcatin 124 is BRM MUASM. Assume als that MUA hardware is nt present in the machine. Executing an instructin cntaining the MUA peratin cde causes the BRM MUASM t be executed. The marked place 12 bits 2 3 4 5 6.7 8 9 10 11 which marks the Flag and PCT bits in 0, 1, zers in bits 6 thrugh 8, and the trap instructin address in bits 9, 10, 11 t MUASM and in bits 0 thrugh 11 in MUASM + 1. The subrutine return rutine fllws: MUASM PLUSONE DATA DATA LOB *MUASM Lad trapped instructin. LOA =1 Lad an incrementer. COB =040 BFT TRUE Branch if bit 6 is reset. COB =037 BRU ACK F = 1 if address was an immediate address (tw wrds); F = 0 if it was direct single precisin. TRUE COB =010 BFT ACK Branch if bit 8 is reset (i.e., if F is set t 1 which implies tw wrd-full address with n index). COB =020 F = 0 if indirect address, single precisin; F = 1 if tw wrd indexed ACK ACA =0 Add 1 t A if tw wrd (add 0 if ne wrd). MPA MUASM+1 Add 1 r 2 t the subrutine entry. MPF MUASM This is fr address verflw crrectin. B-5

SOS 92 MEMORY ALLOCATON 0000 0001-0037 0040-0077 0100-0117 0120 0122 0124 0126 0130 0132 0134 0136 0140 0142 0144 01'46 0150 0152 0154 0156 0160 s 0162 0164 0166 0170 0172 0174 0176 r\ 0200-1177 Unassigned Scratch Pad Unassigned DSC nterlace Cntrl Wrd Pairs Trap 12 Trap 52 Trap 13 Trap 53 Trap 10 Trap 50 Trap 11 Trap 51 Trap 14 Trap 54 Trap 15 Trap 55 \ nterrupt, POWER ON (always arm"'ed) nterrupt, POWER OFF (always armed) nterrupt, MAN FRAME PARTY (armed via cnsle switch) nterrupt, OAT A MU LTPLEXNG SYSTEM PARTY (armed via cnsle switch) Unassigned Unassigned nterrupt, CLOCK SYNC (always armed) nterrupt, CLOCK PULSE (arm furnished,. type) nterrupt, l (arm furnished) nterrupt, 12 (arm furnished) Unassigned Unassigned System nterrupts (up t 256 levels; any may be f. type if desired). --- Single nstructin nterrupt r --- nterrupt system must be enabled befre interrupt ges active. s - nterrupt always prceeds frm Waiting t Active B-6

SDS 92 NSTRUCTON LST - FUNCTONAL CATEGORES nstructin Mnemnic Cde Name Functin Timing* LOAD!...STORE LDA 64 LOAD A (M) --A 2 LDB 24 LOAD B (M) --B 2 STA 44 STORE A (A) --M 2 STB 04 STORE B (B) --M. 2 XMA 74 EXCHANGE M AND A (A)---(M) 3 XMB 34 EXCHANGE M AND B (B)---(M) 3 FLAG XMF 17 EXCHANGE M AND F (M)O---F 3 LDF 57 LOAD F (M)O --F 3 SFT 0044 SET FLAG TRUE 1--F 3,4 SFF 0042 SET FLAG FALSE --F 3,4 NF 0046 NVERT FLAG f (F)=l, 0 --F; if (F)=O, 1--F 3,4 ARTHMETC ADA 62 ADD TO A (A)+ (M) -- A; Carry - F 2 ADB 22 ADD TO B (B)+ (M) ---- B; Carry --- F 2 ACA 63 ADD WTH CARRY TO A (A)+ (M)+ F -- A; Carry -- F 2 ACB 23 ADD WTH CARRY TO B (B)+ (M)+ F - B; Carry --- F 2 SUA 60 SUBTRACT TO A (A) - (M) ---A; Carry --- F 2 SUB 20 SUBTRACT TO B (B) - (M) - B; Carry --F 2 SCA 61 SUBTRACT WTH CARRY TO A (A) - (M) - F ---A; Carry --- F 2 SCB 21 SUBTRACT WTH CARRY TO B (B) - (M) - F --- B; Carry ---F 2 MPA 76 MEMORY PLUS A TO MEMORY (M)+ (A) ---M; Carry --F 3 MPB 36 MEMORY PLUS B TO MEMORY (M)+ (B) --M; Carry -- F 3 MPO 16 MEMORY PLUS ONE TO MEMORY (M)+l ---M; Carry~F 3 MPF 56 MEMORY PLUS FLAG TO MEMORY (M)+ (F) --- M; Carry --- F 3 MUA 13 MU LTPL Y A (Optinal) (A)x (M) --AB 5 MUB 53 MULTPLY B (Optinal) (B)x(M) ---AB 5 DVA 52 DVDE AB (Optinal) (AB)+(M) -B; R--A 13 DVB 12 DVDE BA (Optinal) (BA)+(M) --- B; R --A 13 LOGCAL ANA 65 AND TO A (A) and (M) --A 2 ANB 25 AND TO B (B) and (M) --B 2 ORA 67 OR TOA (A) r (M) --A 2 ORB 27 OR TO B (B) r (M) --B 2 EOA 66 EXCLUSVE OR TO A (M)(A) r (M)(A) ---A 2 *See page 2-1 fr interpretatin and use f the Timing clumn. B-7

SDS 92 NSTRUCTON LST - FUNCTONAL CATEGOR,ES (cntinued) nstructin Mnemnic Cde Name Functin Timing LOGCAL (cntinued) EOB 26 EXCLUSVE OR TO B (M)(B) r (M)(B) --B 2 MAA 75 MEMORY AND A TO MEMORY (M) and (A) --M 3 MAB 35 MEMORY AND B TO MEMORY (M) and (B) --M 3 COMPARSON COA 45 COMPARE ONES WTH A f (A)(M) = 0, set Fi if (A)(M) 10, reset F 2 COB, 05 COMPARE ONES WTH B f (B)(M)=O, set Fi if (B)(M)O, reset F 2 CMA 47 COMPARE MAGNTUDE OF M WTH A f.(a) ~(M), set Fi if (A) < (M), reset F 2 CMB 07 COMPARE MAGNTUDE OF M WTH B f (B) ~(M), set Fi if (B) «M), reset F 2 CEA 46 COMPARE M EQUAL TO A f (M) (A), set F; if (M) =(A), reset F 2 CEB 06 COMPARE M EQUAL TO B f (M)(B), set Fi if (M)=(B), reset F 2 BRANCH SHFT BRU 73 BRANCH UNCONDTONALLY M ---P BRC 32 BRANCH, CLEAR NTERRUPT, AND LOAD FLAG M --- Pi c lear nterrupt (see page 2-4) 3 BRL 33 BRANCH AND LOAD FLAG M --- i (see page 2-4) BFF 31 BRANCH ON F LAG FALSE f F = 0, M ---- Pi 1 if F = 1, take next instructin 2 BFT 71 BRANCH ON F LAG TRUE f F = 1, M ---- Pi 1 if F = 0, take next instructin 2 BDA 70 BRANCH ON DECREMENTNG A (A) - 1---A f (A) 177778, M --- Pi 1 f (A) = 7777, take next instructin 8 2 BAX 30 BRANCH AND EXCHANGE A AND B (A)~ (B)i (M) --- P BRM 77 BRANCH AND MARK PLACE (P) ---M, M+1i M+2---Pi (F) -MO; (PCT)--- M1 3 BMC 37 BRANCH, MARK PLACE, AND CLEAR FLAG (See page 2-5) 3 CYA 42* CYCLE A A cycled left N places 3-7 CYB 02* CYCLE B B cycled left N places 3-7 CFA 43* CYCLE FLAG AND A F,A cycled left N places 3-7 CFB 03* CYCLE FLAG AND B F, B cycled left N places 3-7 CYD 02/42* ** CYCLE DOUBLE A, B cycled left N places 3-7 CFD 43* CYCLE FLAG AND DOUBLE A, B, F cycled left N places 3-7 CF 03* CYCLE FLAG AND DOUBLE NVERSE B, A, F cycled left N places 3-7 CONTROL EXU 72 EXECUTE nstructin M is perfrmed, P unchanged HLT 0041/00000000** HALT Ha ts cmputatin 3,4 *See page 2-5 fr indicatin f the instructin structure and cde redundancy. ** A slash (/) indicates that either instructin cde can be used t perfrm the same peratin. B-8

SDS 92 NSTRUCTON LST - FUNCTONAL CATEGORES (cntinued) nstructin Mnemnic Cde Name Timing TRAPPNG SCT 0061 SET PROGRAM-CONTROLLED TRAP 1-PCT 3,4 RCT 0060 RESET PROGRAM-CONTROLLED TRAP O-PCT 3,4 TCT 0160 TEST PROGRAM-CONTROLLED TRAP f PCT = 0, O-F; if PCT = 1, 3,4 l~f BREAKPONT TESTS BPT 1 0144 BREAKPONT NO.1 TEST Test Breakpint Switch 3,4 BPT 2 0145 BREAKPONT NO.2 TEST Test Breakpint Switch 3,4 BPT 3 0146 BREAKPONT NO.3 TEST Test Breakpint Switch 3,4 BPT 4 0147 BREAKPONT NO.4 TEST Test Breakpint Switch 3,4 NTERRUPTS ER 0051 ENABLE NTERRUPT 3,4 DR 0050 DSABLE NTERRUPT 3,4 let 0150 NTERRUPT ENABLED TEST; SET FLAG F NTERRUPT SYSTEM ENABLED 3,4 AR 00020001 ARM NTERRUPTS 3,4 CHANNEL CONTROL AND TESTS DSC 00000100 DSCONNECT CHANNEL 3,4 TOP 00012100 TERMNATE OUTPUT ON CHANNEL 3,4 TP 00012100 TERMNATE NPUT ON CHANNEL 3,4 ALC 00050100 ALERT CHANNEL NTERLACE 3,4 ASC 00010500 ALERT TO STORE NTERLACE COU NT 3,4 CAT 01004100 CHANNEL ACTVE TEST; SET FLAG F NOT ACTVE 3,4 CET 01001100 CHANNEL ERROR TEST; SET FLAG F ERROR 3,4 NPUTLOUTPUT WN 15 WORD N (Channel)- M 5 + wait RN 55 RECORD N (Channel d )_M N wr s 3 + 2N + wait WOT 11 WORD OUT (M)- Channel 4 + wait ROT 51 RECORD OUT (M d )-Channel N wr s 2 + 2N + wait PN 14 PARALLEL NPUT (Unit M)_ M in parallel 5 + wait, and 5,6 + wait POT 10 PARALLEL OUTPUT (M)_Unit M in parallel 4 + wait, and 4,5 + wait BP 54 BLOCK PARALLEL NPUT (Unit M)_ M in parallel, 4 + N + wait, and N sequential lcatins. 3,4+2N+wait BPO 50 BLOCK PARALLEL OUTPUT (M)_ Unit M in parallel, 3 + N + wait, and N sequential lcatins 2,3 + 2N + wait EOM 00(40)* ENERGZE OUTPUT M 3.5 fjsec pulse t pints addressed 3,4 SES 01(41)* SENSE EXTERNAL SGNAL f Signal = 1, set Flag Bit; if Signal = 0, reset Flag Bit 3,4 *Cdes EOM 40 and SES 41 are reserved fr use in special system applicatins. B-9

SDS 92 NSTRUCTON LST - NUMERCAL ORDER nstructin Cde Mnemnic Name 00(40)* EOM ENERGZE OUTPUT M 00000000/0041** HLT HALT 00000100 DSC DSCONNECT CHANNEL 00010500 ASC ALERT TO STORE NTERLACE COUNT 00012100 TP TERMNATE NPUT ON CHANNEL 00012100 TOP TERMNATE OUTPUT ON CHANNEL 00020001 AR ARM NTERRUPTS 00050100 ALC ALERT CHANNEL NTERLACE 0042 SFF SET FLAG FALSE 0044 SFT SET FLAG TRUE 0046 NF NVERT FLAG 0050 DR DSABLE NTERRUPT 0051 ER ENABLE NTERRUPT 0060 RCT RESET PROGRAM-CONTROLLED TRAP 0061 SCT SET PROGRAM-CONTROLLED TRAP 01(41)* SES SENSE EXTERNAL SGNAL 01001100 CET CHANNEL ERROR TEST; SET FLAG F ERROR 01004100 CAT CHANNEL ACTVE TEST; SET FLAG F NOT ACTVE 0144 BPT 1 BREAKPONT NO. 1 TEST 0145 BPT 2 BREAKPONT NO. 2 TEST 0146 BPT 3 BREAKPONT NO.3 TEST 0147 BPT 4 BREAKPONT NO.4 TEST 0150 let NTERRUPT ENABLED TEST; SET FLAG F NTERRUPT SYSTEM ENABLED 0160 TCT TEST PROGRAM-CONTROLLED TRAP 02*** CYB CYCLE B 02/42** *** CYD CYCLE DOUBLE 03*** CFB CYCLE FLAG AND B 03*** CF CYCLE FLAG AND DOUBLE NVERSE 04 STB STORE B 05 COB COMPARE ONES WTH B 06 CEB COMPARE M EQUAL TO B 07 CMB COMPARE MAGNTUDE OF M WTH B 10 POT PARALLEL OUTPUT 11 WOT WORD OUT 12 DVB DVDE BA (Optinal) 13 MUA MULTPLY A (Optinal) Paae Reference 3-5,3-6,3-9 2-6 3-6 3-6 3-6 3-6 3-12 3-7 2-2 2-1 2-2 3-11 3-11 2-7 2-7 3-6,3-7,3-9 3-7 3-7 2-7 2-7 2-7 2-7 3-11 2-7 2-6 2-6 2-6 2-6 2-1 2-4 2-4 2-4 3-7,3-8,3-9,3-12 3-2 2-3 2-3 *Cdes EOM 40 and SES 41 are reserved fr use in spec ial system appl icatins. ** A slash (/) indicates that either instructin cde can be used t perfrm the same peratin. ***See page 2-5 fr indicatin f the instructin structure and cde redundancy. B-ll

SDS 92 NSTRUCTON LST - NUMERCAL ORDER (cntinued) nstructin Cde Mnemnic Name Pa~e Reference 14 PN PARALLE L NPUT 3-8,3-9 15 WN WORD N 3-2 16 MPO MEMORY PLUS ONE TO MEMORY 2-2 17 XMF EXCHANGE M ANDF 2-1 20 SUB SUBTRACT TO B 2-2 21 SCB SUBTRACT WTH CARRY TO B 2-2 22 ADB ADD TO B 2-2 23 ACB ADD WTH CARRY TO B 2-2 24 LDB LOAD B 2-1 25 ANB AND TO B 2-3 26 EOB EXCLUSVE OR TO B 2-3 27 ORB OR TO B 2-3 30 BAX BRANCH AND EXCHANGE A AND B 2-5 31 BFF BRANCH ON FLAG FALSE 2-4 32 BRC BRANCH, CLEAR NTERRUPT, AND LOAD FLAG 2-4 33 BRL BRANCH AND LOAD FLAG 2-4 34 XMB EXCHANGE M AND B 2-1 35 MAB MEMORY AND B TO MEMORY 2-4 36 MPB MEMORY PLUS B TO MEMORY 2-2 37 BMC BRANCH, MARK PLACE, AND CLEAR FLAG 2-5 42* CYA CYCLE A 2-6 43* CFA CYCLE FLAG AND A 2-6 43* CFD CYCLE FLAG AND DOUBLE 2-6 44 STA STORE A 2-1 45 COA COMPARE ONES WTH A 2-4 46 CEA COMPARE M EQUAL TO A 2-4 47 CMA COMPARE MAGNTUDE OF M WTH B 2-4 50 BPO BLOCK PARALLEL OUTPUT 3-8,3-9 51 ROT RECORD OUT 3-2 52 DVA DVDE AB (Optina ) 2-3 53 MUB MULTPLY B (Optinal) 2-3 54 BP BLOCK PARALLEL NPUT 3-8,3-9 55 RN RECORD N 3-3 56 MPF MEMORY PLUS FLAG TO MEMORY 2-3 57 LDF LOAD F 2-1 60 SUA SUBTRACT TO A 2-2 61 SCA SUBTRACT WTH CARRY TO A 2-2 62 ADA ADD TO A 2-2 *See page 2-5 fr indicatin f the instructin structure and cde redundancy. B-12

SDS 92 NSTRUCTON LST - NUMERCAL ORDER (cntinued) nstructin Cde Mnemnic Name Page Reference 63 ACA ADD WTH CARRY TO A 2-2 64 LDA LOAD A 2-1 65 ANA AND TO A 2-3 66 EOA EXCLUSVE OR TO A 2-3 67 ORA OR TO A 2-3 70 BDA BRANCH ON DECREMENTNG A 2-5 71 BFT BRANCH ON FLAG TRUE 2-5 72 EXU EXECUTE 2-6 73 BRU BRANCH UNCONDTONALLY 2-4 74 XMA EXCHANGE M AND A 2-1 " 75 MAA MEMORY AND A TO MEMORY 2-4 76 MPA MEMORY PLUS A TO MEMORY 2-2 77 BRM BRANCH AND MARK PLACE 2-5 B-13

SDS 92 NSTRUCTON LST - ALPHABETCAL ORDER Mnemnic nstructin Cde Name Paae Reference ACA 63 ADD WTH CARRY TO A 2-2 ACB 23 ADD WTH CARRY TO B 2-2 ADA 62 ADD TO A 2-2 ADB 22 ADD TO B 2-2 AR 00020001 ARM NTERRUPTS 3-12 ALC 00050100 ALERT CHANNEL NTERLACE 3-7 ANA 65 AND TO A 2-3 ANB 25 AND TO B 2-3 ASC 00010500 ALERT TO STORE NTERLACE COUNT 3-6 BAX 30 BRANCH ON DECREMENTNG A 2-5 BDA 70 BRANCH AND DECREMENTNG A 2-5 BFF 31 BRANCH ON FLAG FALSE 2-4 BFT 71 BRANCH ON FLAG TRUE 2-5 BMC 37 BRANCH, MARK PLACE, AND CLEAR FLAG 2-5 BP 54 BLOCK PARALLEL NPUT 3-8,3-9 BPO 50 BLOCK PARALLEL OUTPUT 3-8,3-9 BPT 1 0144 BREAKPONT NO. 1 TEST 2-7 BPT 2 0145 BREAKPONT NO.2 TEST 2-7 BPT 3 0146 BREAKPONT NO.3 TEST 2-7 BPT 4 0147 BREAKPONT NO.4 TEST 2-7 BRC 32 BRANCH, CLEAR NTERRUPT, AND LOAD FLAG 2-4 BRL 33 BRANCH AND LOAD FLAG 2-4 BRM 77 BRANCH AND MARK PLACE 2-5 BRU 73 BRANCH UNCONDTONALLY 2-4 CAT 01004100 CHANNEL ACTVE TEST; SET FLAG F NOT ACTVE 3-7 CEA 46 COMPARE M EQUAL TO A 2-4 CEB 06 COMPARE M EQUAL TO B 2-4 CET 01001100 CHANNEL ERROR TEST; SET FLAG F ERROR 3-7 CFA 43* CYCLE FLAG AND A 2-6 CFB 03* CYC LE FLAG AND B 2-6 CFD 43* CYCLE FLAG AND DOUBLE 2-6 CF 03* CYCLE FLAG AND DOUBLE NVERSE 2-6 CMA 47 COMPARE MAGNTUDE OF M WTH A 2-4 CMB 07 COMPARE MAGNTUDE OF M WTH B 2-4 COA 45 COMPARE ONES WTH A 2-4 COB 05 COMPARE ONES WTH B 2-4 CYA 42* CYCLE A 2-6 CYB 02* CYCLE B 2-6 *See page 2-5 fr indicatin f the instructin structure and cde redundancy. B-15

SDS 92 NSTRUCTON LST - ALPHABETCAL ORDER (cntinued) Mnemnic nstructin Cde Name CYD 02/42* ** CYCLE DOUBLE DR 0050 DSABLE NTERRUPT DSC 00000100 DSCONNECT CHANNEL DVA 52 DVDE AB (Optinal) DVB 12 DVDE BA (Optinal) ER 0051 ENABLE NTERRUPT EOA 66 EXCLUSVE OR TO A EOB 26 EXCLUSVE OR TO B EOM 00(40)*** ENERGZE OUTPUT M EXU 72 EXECUTE HLT 00000000/0041** HALT let 0150 NTERRUPT ENABLED TEST; SET FLAG F NTERRUPT SYSTEM ENABLED NF 0046 NVERT FLAG LDA 64 LOAD A LDB 24 LOAD B LDF 57 LOAD F MAA 75 MEMORY AND A TO MEMORY MAB 35 MEMORY AND B TO MEMORY MPA 76 MEMORY PLUS A TO MEMORY MPB 36 MEMORY PLUS B TO MEMORY MPF 56 MEMORY PLUS FLAG TO MEMORY MPO 16 MEMORY PLUS ONE TO MEMORY MUA 13 MULTPLY A (Optinal) MUB 53 MULTPLY B (Optinal) ORA 67 OR TOA ORB 27 OR TO B PN 14 PARALLEL NPUT POT 10 PARALLEL OUTPUT RCT 0060 RESET PROGRAM-CONTROLLED TRAP RN 55 RECORD N ROT 51 RECORD OUT SCA 61 SUBTRACT WTH CARRY TO A SCB 21 SUBTRACT WTH CARRY TO B SCT 0061 SET PROGRAM-CONTROLLED TRAP SES 01 (41)*** SENSE EXTERNAL SGNAL SFF 0042 SET FLAG FALSE SFT 0044 SET FLAG TRUE Paae Reference 2-6 3-11 3-6 2-3 2-3 3-11 2-3 2-3 3-5,3-6,3-9 2-6 2-6 3-11 2-2 2-1 2-1 2-1 2-4 2-4 2-2 2-2 2-3 2-2 2-3 2-3 2-3 2-3 3-8,3-9 3-7,3-8,3-9,3-12 2-7 3-3 3-2 2-2 2-2 2-7 3-6,3-7,3-9 2-2 2-1 *See page 2-5 fr indicatin f the instructin structure and cde redundancy. **A slash V) indicates that either instructin cde can be used t perfrm the same peratin. ***Cdes EOM 40 and SES 41 are reserved fr use in special system appl icatins. B-16

SDS 92 NSTRUCTON LST - ALPHABETCAL ORDER (cntinued) \ Mnemnic nstructin Cde Name Pase Reference STA 44 STB 04 SUA 60 SUB 20 TCT 0160 TP 00012100 TOP 00012100 WN 15 WOT 11 XMA 74 XMB 34 XMF 17 STORE A STORE B SUBTRACT TO A SUBTRACT TO B TEST PROGRAM-CONTROLLED TRAP TERMNATE NPUT ON CHANNEL TERMNATE OUTPUT ON CHANNEL WORD N WORD OUT EXCHANGE M AND A EXCHANGE M AND B EXCHANGE M AND F 2-1 2-1 2-2 2-2 2-7 3-6 3-6 3-2 3-2 2-1 2-1 2-1 B-17

SOS 92 NPUT/OUTPUT NSTRUCTONS Mnemnic Octal Cde Name Mnemnic Octal Cde Name Buffer nstructins and Tests BUFFER CONTROL BUFFER TESTS EOM A, T 00 r 40 Energize Output M DSC 00000100 Discnnect Channel SES A, T 01 r 41 Sense External Signal TOP 00012100 Terminate Output n Channel CAT 01004100 Channel Active Test TP 00012100 Terminate nput n Channel CET 01001100 Channel Errr Test ASC 00010500 Alert t Stre nterlace Cunt ALC 00050100 Alert Channel nterlace DAT A TRANSFER PARALLEL NPUT/OUTPUT WOT A, T 11 Wrd Out POT A, T 10 Parallel Output ROT A, T 51 Recrd Out BPO A, T 50 Blck Parallel Output WN A,T 15 Wrd n PN A, T 14 Parallel nput RN A, T 55 Recrd n BP A, T 54 Blck Parallel nput Peripheral Device nstructins and Tests TYPEWRTER LNE PRNTER (cnt. ) RKB 1,2 00002301 Read Keybard PSC 1, n 0001n560 Printer Skip t Frmat Channel n TYP 1,2 00002341 Write Typewri ter PSP 1, n 0001 n760 Pri nter Space n Li nes PLP 1,2 00002360 Print Line Printer PAPER TAPE MAGNETC TAPE RPT 1,2 00002304 Read Paper Tape PTL 1,2 00000344 Punch Paper Tape with Leader TRT n 0101051n T ape Ready Test PPT 1,2 00002344 Punch Paper Tape, N Leader FPT n 0101411n File Prtect Test BTT n 0101211 n Beginning f Tape Test CARD ETT n 0101111n End f Tape Test DT2 n 0101631n Density Test, 200 BP CRT 01012106 Card Reader Ready Test DT5 n 0101671n Density Test, 556 BP CFT 01011106 Card Reader EOF Test DT8 n 0101731n Density Test, 800 BP RCD 1,2 00002306 Read Card Dec imal (Hllerith) TFT 01013710 Tape End-f-File Test RCB 1,2 00003306 Read Card Binary WTB n,2 0000335n Write Tape in Binary CPT 1 01014146 Card Punch Ready Test WTD n,2 0000235n Write Tape in Decimal (BCD) PCD 1,2 00002346 Punch Card Decimal (Hllerith) EFT n,2 0000337n E rase Frward Tape PCB 1,2 00003346 Punch Card Binary ERT n,2 0000737n Erase Reverse Tape RTB n,2 0000331n Read Tape in Binary RTD n,2 0000231n Read Tape in Decimal (BCD) LNE PRNTER SFB n,2 0000333n Scan Frward in Binary SFD n,2 0000233n Scan Frward in Decimal (BCD) PRT 01012160 Pri nter Read y T es t SRB n,2 0000733n Scan Reverse in Binary EPT 01014160 End f Page Test SRD n,2 0000633n Scan Reverse in Decimal (BCD) PFT 01011160 Printer Fault Test REW n 0001411 n Rewind POL 00010360 Printer Off-line RTS 0 00014100 Cnvert Read t Scan Legend A = address; *A = indirect address; =A = immediate address; T = index tag; n = number (0-7) Mnemnics and Octal Cdes are given fr device number 1 in a tw-character/wrd mde.

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