SRAM Based Random Number Generator For Non-Repeating Pattern Generation

Applied Mechanics and Materials Online: 2014-06-18 ISSN: 1662-7482, Vol. 573, pp 181-186 doi:10.4028/www.scientific.net/amm.573.181 2014 Trans Tech Publications, Switzerland SRAM Based Random Number Generator For Non-Repeating Pattern Generation G.P.Ramesh 1,a*, A.Rajan 2,b 1 Professor, St. Peter s University, Chennai, India 2 Research Scholar, St. Peter s University, Chennai, India a rameshgp@gmail.com, b arurajan@yahoo.com Keywords: RNG, LFSR, SRAM Abstract Field-programmable gate array (FPGA) optimized random number generators (RNGs) are more resource-efficient than software-optimized RNGs because they can take advantage of bitwise operations and FPGA-specific features. A random number generator (RNG) is a computational or physical device designed to generate a sequence of numbers or symbols that lack any pattern, i.e. appear random. The many applications of randomness have led to the development of several different methods for generating random data. Several computational methods for random number generation exist, but often fall short of the goal of true randomness though they may meet, with varying success, some of the statistical tests for randomness intended to measure how unpredictable their results are (that is, to what degree their patterns are discernible).lut-sr Family of Uniform Random Number Generators are able to handle randomness only based on seeds that is loaded in the look up table. To make random generation efficient, we propose new approach based on SRAM storage device. I. INTRODUCTION Since the beginning of the computer age, high-quality random numbers have played an important and expanding role in areas such as Monte Carlo simulations, computer-based gaming, VLSI chip testing, and probabilistic computing methods like simulated annealing, genetic algorithms, and neural networks. As computers have become more powerful and simulations more ambitious, the demand on random number generators (RNGs) have likewise increased. An essential property of RNG is that it produces a satisfactorily random sequence of numbers. In particular, uniform random bits are extremely cheap to generate in an FPGA, as large numbers of bits can be generated per cycle at high clock rates. FPGA-optimized generators provide a simple method for engineers to instantiate an RNG that meets the specific needs of their application [3]. With the advent of VLSI design, it became advantageous to incorporate a part of the chip testing system on the chip itself. Initially, linear feedback shift registers were used to implement the random pattern generator portion of the built-in self-test. The paper deals with the making of non-repeating random number patterns from a generator using input seeds stored in SRAM. Static random-access memory (SRAM) is a type of semiconductor memory that uses bistable latching circuitry to store each bit. Whenever patterns are repeated the memory can rewrite new seeds into it, by this we can avoid the repetition. Verilog implementation of SRAM based random number generator has been proposed in this thesis. In this paper non-repeating patterns is generated by using LFSR were its input is from SRAM and a controller. The patterns are combined with data signals, compressed and then transmitted. Since the codes are not repeating it avoids interference in the transmission channel. In the recent years the RNGs on FPGA platform is a common technique used by various applications. The Spartan TM-3E family of Field-Programmable Gate Arrays (FPGAs) is specifically broadband designed to meet the needs of high volume, cost-sensitive consumer electronic applications II. OVERVIEW A. RANDOM NUMBER GENERATOR A random number sequence is a sequence that is unpredictable. One way to determine the unpredictability of a number sequence is to look for characteristics of a perfectly random sequence of numbers. A good sequence of random numbers should not have any correlation between successive All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications, www.ttp.net. (ID: 130.203.136.75, Pennsylvania State University, University Park, USA-06/03/16,21:32:00)

182 Advancements in Automation and Control Technologies numbers. This means that one should not be able to predict the next number in the sequence by looking at previous numbers. The most fundamental characteristic of a sequence of numbers is its distribution. That is whether generators produce uniformly distributed number sequences or other distributions such as normal, Poisson, geometric, binomial [2]. The range of a sequence is also important. There will be a smallest and largest number boundary for the random sequence. The sequence type is another characteristic. That is the random number produced may be integer or floating point. Most computer programming languages include functions or library routines that purport to be random number generators. They are often designed to provide a random byte or word, or a floating point number uniformly distributed between 0 and 1. B. LINEAR FEEDBACK SHIFT REGISTER In computing, a linear feedback shift register (LFSR) is a shift register whose input bit is a linear function of its previous state. For a general reference on the subject of LFSRs and related sequence generators. The most commonly used linear function of single bits is XOR. Thus, an LFSR is most often a shift register whose input bit is driven by the exclusive-or (XOR) of some bits of the overall shift register value. The initial value of the LFSR is called the seed, and because the operation of the register is deterministic, the stream of values produced by the register is completely determined by its current (or previous) state. Likewise, because the register has a finite number of possible states, it must eventually enter a repeating cycle. However, an LFSR with a well-chosen feedback function can produce a sequence of bits which appears random and which has content very long cycle [8, 11]. C. STATIC RANDOM-ACCESS MEMORY (SRAM) An SRAM cell has three different states. It can be in: standby (the circuit is idle), reading (the data has been requested) and writing (updating the contents). [5] The SRAM to operate in read mode and write mode should have "readability" and "write stability" respectively. Characteristics: SRAM is more expensive, but faster and significantly less power hungry (especially idle) than DRAM. It is therefore used where either bandwidth or low power, or both, are principal considerations. SRAM is also easier to control (interface to) and generally more truly random access than modern types of DRAM. Due to a more complex internal structure, SRAM is less dense than DRAM and is therefore not used for high-capacity, low-cost applications such as the main memory in personal computers. D. CODE DIVISION MULTIPLE ACCESS (CDMA) It is a channel access method used by various radio communication technologies. One of the concepts in data communication is the idea of allowing several transmitters to send information simultaneously over a single communication channel. This allows several users to share a band of frequencies (see bandwidth). This concept is called multiple accesses. CDMA employs spreadspectrum technology and a special coding scheme (where each transmitter is assigned a code) to allow multiple users to be multiplexed over the same physical channel. By contrast, time division multiple access (TDMA) divides access by time, while frequency-division multiple access (FDMA) divides it by frequency. CDMA is a form of spread-spectrum signaling, since the modulated coded signal has a much higher data bandwidth than the data being communicated. Steps in CDMA Modulation: CDMA is a spread spectrum multiple access technique. A spread spectrum technique spreads the bandwidth of the data uniformly for the same transmitted power. A spreading code is a pseudorandom code that has a narrow ambiguity function, unlike other narrow pulse codes. In CDMA a locally generated code runs at a much higher rate than the data to be transmitted [6]. Data for transmission is combined via bitwise XOR (exclusive OR) with the faster code. The figure shows how a spread spectrum signal is generated. The data signal with pulse duration of T b (symbol period) is XOR ed with the code signal with pulse duration of T c (chip period). (Note: bandwidth is proportional to 1/T where T= bit time) Therefore, the bandwidth of the data signal is 1/T b and the bandwidth of the spread spectrum signal is 1/T c. Since T c is much smaller than T b, the bandwidth of the spread spectrum signal is much larger than the bandwidth of the original signal. The ratio Tb/T c

Applied Mechanics and Materials Vol. 573 183 is called the spreading factor or processing gain and determines to a certain extent the upper limit of the total number of users supported simultaneously by a base station. Fig 1.1 Graph Each user in a CDMA system uses a different code to modulate their signal. Choosing the codes used to modulate the signal is very important in the performance of CDMA systems. The best performance will occur when there is good separation between the signal of a desired user and the signals of other users. The separation of the signals is made by correlating the received signal with the locally generated code of the desired user. If the signal matches the desired user's code then the correlation function will be high and the system can extract that signal. If the desired user's code has nothing in common with the signal the correlation should be as close to zero as possible (thus eliminating the signal); this is referred to as cross correlation. If the code is correlated with the signal at any time offset other than zero, the correlation should be as close to zero as possible. This is referred to as auto-correlation and is used to reject multi-path interference. III. SRAM BASED RNG We know that existing LUT-SR based random number generator fails to handle the user defined data due to look up table where we load data predefined [1]. Shift registers produces random numbers based on the seeds loaded into look up tables. This kind of architecture should not be used in mobile communication. So we enhance this architecture using static random access memory instead of Look up tables. By using SRAM we can make random number generator to process user defined data. The significant aim of VLSI design is to reduce power for every logic that is directly proportion to area. In digital communication, channel encoding is significant to make data transmission easier. It s not possible to compress data s without any uniform method. For this intention, we design a compressor that should compress information with ½ ratios. The paper had been designed in the domain of VLSI to generate non-repeating sequence of patterns. The main purpose of this paper is to produce random numbers that are non-repeating in nature. Random numbers are generated using linear feedback shift registers (LFSR). One way to determine the unpredictability of a number sequence is to look for characteristics of a perfectly random sequence of numbers. The paper is implemented in a real time application of CDMA communication. Field Programmable Gate Arrays (FPGAs) are emerging as an attractive platform for random number generator implementations. FPGA consists of many number of configurable logic blocks and thus we can easily implement our paper in this. Advantages: It can feed user defined data at run time. Power consumption is less as compared to LUT-SR. Non-repeating patterns are obtained. It avoids interference in communication channel. It can be useful in real time applications.

184 Advancements in Automation and Control Technologies A. TRANSMITTER SECTION Fig 1.2 Block diagram of Transmitter The SRAM seeds are loaded into shift registers. The linear feedback shift register produces the random patterns. The controller is a circuit in Fig 1.2 consists of a register and a comparator. Comparator checks whether the sequence exceeds the limit and the controller checks whether the sequence repeats or not. If the sequence is not repeated then it combines with the data signal by XORing the data signal with the random sequence. The spreaded signal is compressed and then transmitted. B. RECEIVER SECTION Received Signal Fig 1.3 Decompressed Signal The received signal is decompressed as shown in Fig 1.3. The decompressed signal is then XOR ed with the sequence from controller and thus the data signal is separated out from the random pattern by the de spreader. (a) SRAM Static random-access memory (SRAM) is a type of semiconductor memory that uses bistable latching circuitry to store each bit. We can reload the SRAM after a particular period or after getting a control signal from controller. The power consumption of SRAM varies widely depending on how frequently it is accessed. SRAM is integrated on FPGA. Fig 1.4 Shows how to read and write SRAM SRAM has control logic whether to read or write data from or to the corresponding address. The data out from SRAM is the seeds for shift register. The row and column decoder of the address latch determines the address to which data is writing or the address from which data is read. (b) LFSR In computing, a linear feedback shift register (LFSR) is a shift register whose input bit is a linear function of its previous state. The most commonly used linear function of single bits is XOR. (c) Controller The controller is the significant part in this paper. The controller consists of a comparator and a register. The controller uses a comparator is used to check whether the patterns from linear feedback shift registers exceed the predetermined limit. If it exceeds then it discards the pattern else give this to the register in the controller. The controller checks whether the data is repeating or not by matching it with the patterns preloaded in the register file. If the patterns are repeating then the controller discards the pattern and sends a control signal to the SRAM to feed next seed to the LFSR.

Applied Mechanics and Materials Vol. 573 185 (d) Spreader The spreader gets its name from its role in the paper. The spreaders have two inputs, one from the controller and the other from the data generator. Spreader combines these two inputs with XOR function and then given it to the compressor block. (e) Despreader The de-spreader function is just opposite of that the spreader. It de combines received data. The function de combining means the received data is XORed with the random number sequence generated by the linear feedback shift register. It eliminates the random pattern in the received data and finally we get the original data transmitted. IV. FLOWDIAGRAM Fig 1.5 Flow of the Paper In the Fig 1.5 the SRAM is providing 16 bit seeds to linear feedback shift register. The LFSR makes random sequences of 16 bits from this seeds. The controller block checks whether the random patterns are repeating or it exceeds the maximum limit. If they are not repeating and not exceeds the limit then the corresponding random sequence is combined with data signal. The spreaded signal is compressed and then transmitted. At the receiver side it decompresses and de combines to get the original data transmitted. V. RESULT & SIMULATION Fig 1.6 Simulation Result In the Fig 1.6 avoidance of repeating patterns are shown. FPGA IMPLEMENTATION Fig 1.7 Implementation

186 Advancements in Automation and Control Technologies The non-repeating patterns generated are shown above in the display of FPGA kit. Here Altera DE II kit is used for the implementation. VI. CONCLUSION AND FUTURE WORK Random numbers are required in a wide variety of applications. We have examined several design techniques for hardware random number generators and their feasibility for FPGA devices [3]. FPGA-optimized generators are not widely used in practice, as the process of constructing a generator for a given parameterization is time-consuming, in terms of both developer man-hours and CPU-time. SRAM based implementation helps in making patterns of user defined data. So this random number generator can be used in real time applications such as CDMA, simulating test benches etc. Since the patterns are non-repeating it also avoids interference in communication channel. Cryptographic purpose also needs non-repeating patterns to provide enough security to the documents. For random number generator, LFSR is the most effective method. When multiple bits are required, our LFSR can be extended by utilizing extra time (as in counter method) or extra circuitry (as in parallel LSFR method and leap-forward LSFR method). For a small number of bits, leap-forward LFSR method is ideal since it balances the combinational circuitry and register and thus fully utilizes the FPGA's resource [4]. Our design shows high randomness between patterns and avoids repeated patterns. As digital systems become faster and denser, it is feasible, and frequently necessary, to implement random number generators directly in hardware. In future, we will describe techniques suitable for hardware implementation, including multiple-bit true random number generator, one-bit LFSR (Linear Feedback Shift Register) generator, and multiple bit LFSR generators. We will also implement our design using Clock gating technique to reduce static and dynamic power consumption. Clock gating will be applied to the SRAM to make it to on only for the time the seeds are taken to the LFSR, remaining time it will kept off. REFERENCES [1] The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures David B. Thomas, Member, IEEE, and Wayne Luk, Fellow, IEEE, IEEE Transactions 2012 [2] D. B. Thomas and W. Luk, High quality uniform random number generation using LUT optimised state-transition matrices, J. VLSI Signal Process, vol. 47, no. 1, pp. 77 92, 2012. [3] D. B. Thomas and W. Luk, FPGA-optimised high-quality uniform random number generators, in Proc. Field Program. Logic Appl. Int. Conf., 2011, pp. 235 244 [4] Uniform Random Number Generator using Leap-Ahead LFSR Architecture, GU Xiao-chen, ZHANG Min-xuan School of Computer National University of Defense Technology Changsha, China specialsjtu@163.com, 2010 International Conference on Computer and Communications Security [5] Zahid Ullah1, Manish Kumar Jaiswal2, Y.C. Chan3, and Ray C.C. Cheung4; FPGA Implementation of SRAM-based Ternary Content Addressable Memory; IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012 [6] V. Sriram and D. Kearney, A high throughput area time efficient pseudo uniform random number generator based on the TT800 algorithm, in Proc. Int. Conf. Field Program. Logic Appl., 2009, pp. 529 532. [7] M. Saito and M. Matsumoto, SIMD-oriented fast mersenne twister: A 128-bit pseudorandom number generator, in Monte-Carlo and Quasi- Monte Carlo Methods. New York: Springer- Verlag, 2006, pp. 607 622. [8] F. Panneton, P. L Ecuyer, and M. Matsumoto, Improved long-period generators based on linear recurrences modulo 2, ACM Trans. Math. Software, vol. 32, no. 1, pp. 1 16, 2006. [9] M. Matsumoto and Y. Kurita, Twisted GFSR generators II, ACM Trans. Modeling Comput. Simulat., vol. 4, no. 3, pp. 254 266, 1994. [10] P. L Ecuyer and R. Simard. (2007). TestU01 Random Number Test Suite [Online]. Available: http://www.iro.umontreal.ca/ imardr/indexe.html [11] Y. Li, P. C. J. Jiang, and M. Zhang, Software/hardware framework for generating parallel long-period random numbers using the well method, in Proc. Int. Conf. Field Program. Logic Appl., Sep. 2011, pp. 110 115.

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