FEATURES N-SYSTEM PROGRAMMABLE (5-V ONLY) 4-Wire Serial Programming nterface Minimum,000 Program/Erase Cycles Built-in Pull-own on S Pin Eliminates iscrete Resistor on Board (ispgal22vc Only) HGH PERFORMANCE E 2 CMOS TECHNOLOGY 5 ns Maximum Propagation elay Fmax 11 MHz 5 ns Maximum from Clock nput to ata Output UltraMOS Advanced CMOS Technology ACTVE PULL-UPS ON ALL LOGC NPUT AN /O PNS COMPATBLE WTH STAN 22V EVCES Fully Function/Fuse-Map/Parametric Compatible with Bipolar and CMOS 22V evices E 2 CELL TECHNOLOGY n-system Programmable Logic 0% Tested/Guaranteed 0% Yields High Speed Electrical Erasure (<0ms) 20 Year ata Retention TEN OUTPUT LOGC MACROCELLS Maximum Flexibility for Complex Logic esigns APPLCATONS NCLUE: MA Control State Machine Control High Speed Graphics Processing Software-riven Hardware Configuration ELECTRONC SGNATURE FOR ENTFCATON ESCRPTON The ispgal22v, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E 2 ) floating gate technology to provide the industry's first in-system programmable 22V device E 2 technology offers high speed (<0ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell () to be configured by the user The ispgal22v is fully function/fuse map/parametric compatible with standard bipolar and CMOS 22V devices The standard PLCC package provides the same functional pinout as the standard 22V PLCC package with No-Connect pins being used for the interface signals Unique test circuitry and reprogrammable cells allow complete AC, C, and functional testing during manufacture As a result, Lattice Semiconductor guarantees 0% field programmability and functionality of all GAL products n addition,,000 erase/ write cycles and data retention in excess of 20 years are guaranteed Specifications ispgal22v FUNCTONAL BLOCK AGRAM SO S MOE S ispgal22v n-system Programmable E 2 CMOS PL Generic Array Logic / PN CONFGURATON PROGRAMMNG LOGC PROGRAMMABLE AN-RAY (132X44) Copyright 1996 Lattice Semiconductor Corp All brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice LATTCE SEMCONUCTOR CORP, 5555 Northeast Moore Ct, Hillsboro, Oregon 94, USA 1996 ata Book Tel (503) 61-011; 1---PLS; FAX (503) 61-303; http://wwwlatticesemicom MOE 5 9 4 / PLCC S Vcc 2 2 /O/ 11 1 19 GN ispgal22v Top View S /O/ /O/ 26 /O/ 25 23 21 /O/ /O/ /O/ SO /O/ /O/ /O/ RESET S / MOE GN PRESET 1 ispgal 22V Top View 2 22 /O/ /O/ /O/ /O/ /O/ /O/ /O/ /O/ /O/ /O/ Vcc /O/ /O/ /O/ /O/ /O/ SO /O/ /O/ /O/ /O/ /O/ S isp22v_01 1 1996 ata Book
Specifications ispgal22v ORERNG NFORMATON Commercial Grade Specifications T pd (ns) T su (ns) T co (ns) cc (ma) Ordering # 5 6 5 5 0 ispgal22vc-lj ispgal22vc-lk 2-Lead ispgal22vb-lj 0 ispgal22vc-lj 0 ispgal22vc-lj ndustrial Grade Specifications ispgal22vc-lk 2-Lead ispgal22vb-lj ispgal22vc-lk 2-Lead ispgal22vb-lj T pd (ns) T su (ns) T co (ns) cc (ma) Ordering # 5 ispgal22vc-lj ispgal22vc-lk 2-Lead PT NUMBER ESCRPTON XXXXXXXX _ XX X X X ispgal22vc ispgal22vb evice Name Speed (ns) Grade Blank = Commercial = ndustrial L = Low Power Power J = PLCC K = 2 1996 ata Book
Specifications ispgal22v OUTPUT LOGC MACROCELL () The ispgal22v has a variable number of product terms per Of the ten available s, two s have access to eight product terms (pins 1 and 2), two have ten product terms (pins 1 and 26), two have twelve product terms (pins 19 and 25), two have fourteen product terms (pins 20 and 24), and two s have sixteen product terms (pins 21 and 23) n addition to the product terms available for logic, each has an additional product-term dedicated to output enable control The output polarity of each can be individually programmed to be true or inverting, in either combinatorial or registered mode This allows each output to be individually configured as either active high or active low The ispgal22v has a product term for Asynchronous Reset () and a product term for Synchronous Preset () These two product terms are common to all registered s The Asynchronous Reset sets all registers to zero any time this dedicated product term is asserted The Synchronous Preset sets all registers to a logic one on the rising edge of the next clock pulse after this product term is asserted NOTE: The and product terms will force the output of the flip-flop into the same state regardless of the polarity of the output Therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen 4 TO 1 MUX 2 TO 1 MUX ispgal22v OUTPUT LOGC MACROCELL () OUTPUT LOGC MACROCELL CONFGURATONS Each of the Macrocells of the ispgal22v has two primary functional modes: registered, and combinatorial /O The modes and the output polarity are set by two bits (SO and ), which are normally controlled by the logic compiler Each of these two primary modes, and the bit settings required to enable them, are described below and on the following page REGSTERE n registered mode the output pin associated with an individual is driven by the output of that s -type flip-flop Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low) Output tri-state control is available as an individual product-term for each, and can therefore be defined by a logic equation The flip-flop s / output is fed back into the AN array, with both the true and complement of the feedback available as inputs to the AN array NOTE: n registered mode, the feedback is from the / output of the register, and not from the pin; therefore, a pin defined as registered is an output only, and cannot be used for dynamic /O, as can the combinatorial pins COMBNATORAL /O n combinatorial mode the pin associated with an individual is driven by the output of the sum term gate Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low) Output tri-state control is available as an individual product-term for each output, and may be individually set by the compiler as either on (dedicated output), off (dedicated input), or productterm driven (dynamic /O) Feedback into the AN array is from the pin side of the output enable buffer Both polarities (true and inverted) of the pin are fed back into the AN array 3 1996 ata Book
Specifications ispgal22v REGSTERE MOE ACTVE LOW ACTVE HGH COMBNATORAL MOE ACTVE LOW ACTVE HGH 4 1996 ata Book
Specifications ispgal22v ispgal22v LOGC AGRAM / JEEC FUSE MAP 2 0000 0044 0396 PLCC & Pinout 0 4 20 24 2 32 36 40 ASYNCHRONOUS RESET (TO ALL REGSTERS) 50 509 2 3 4 5 6 9 11 0440 00 0924 52 96 21 26 260 2904 360 3652 426 43 440 44 5324 536 520 564 5 511 5 513 5 5 5 51 51 519 520 521 522 523 524 525 526 52 SYNCHRONOUS PRESET (TO ALL REGSTERS) 13 26 25 24 23 21 20 19 1 1 52, 529 Electronic Signature 590, 591 Byte Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 M L SB S B 5 1996 ata Book