TTCrx, AN ASIC FOR TIMING, TRIGGER AND CONTROL DISTRIBUTION IN LHC EXPERIMENTS

TTCrx, AN ASIC FOR TIMING, TRIGGER AND CONTROL DISTRIBUTION IN LHC EXPERIMENTS J. Christiansen, A. Marchioro P. Moreira, CERN - ECP/MIC, Geneva, Switzerl ABSTRACT An ASIC receiver was developed for the LHC Timg, Trigger Control (TTC) distribution system. The ASIC implements an terface between the front end electronics the TTC system makg the TTC codg multiplexg schemes transparent to the users. The receiver delivers the LHC timg reference signal, the first level trigger decisions its associated bunch event numbers. It can be programmed to compensate for the propagation delays associated with the detectors their electronics. The IC supports the transmission of data of synchronised broadcast comms. The ASIC was implemented a stard 1 µm CMOS process usg a combation of full custom stard cell design techniques. The jitter measured on the recovered clock is less than 8 ps RMS for put optical powers down to -22 dbm. The time deskewg functions allows the comms the first level trigger accepignal to be phase shifted up to a maximum of sixteen clock cycles steps of.1 ns with an RMS error of 92 ps. 1. INTRODUCTION A passive optical fibre network has been proposed to distribute the LHC Timg, Trigger Control (TTC) formation to several thous front-end electronic destations usg a sgle laser source [1,2]. At the transmitter end, two communication channels are time division multiplexed coded the BiPhase Mark (BPM) format, before they are optically transmitted over the network. One of the multiplexed channels carries the firstlevel trigger-accepignal while the other is used to transmit general broadcast dividually addressed comms. A timg receiver is associated to each of the puts of the optical network. This receiver is composed of a commercial tegrated photodetector-preamplifier the special purpose IC (TTCrx) described this paper [3]. The TTCrx ASIC receives the formation broadcast over the TTC distribution network makes it available to electronics both side side the LHC detectors. 2. TTCrx ARCHITECTURE The ma functions of the timg receiver are to recover the 4.8 MHz LHC reference clock with mimum jitter, to distribute the first-level trigger-accept decisions broadcast comms to make them available to the detector electronics properly deskewed time. Additionally, the receiver recognises dividually addressed comms for purposes of ternal external control. Bunch crossg event identification numbers are also made available. Figure 1 shows the architecture chosen to implement this functionality. In this figure the broken le represents the boundary between the full custom the stard cell part of the design. The full custom part implements all the analogue timg critical functions of the receiver, while the stard cell design implements the digital control non-time critical functions. Input from PINFET Full Custom Stard Cells Local Address JTAG Lear Receiver Internal Registers Control Clock Extraction Data Decoder/ Demultiplexer A 4φ B A-B Channels Identification Error Monitorg Serial/Parallel Converter Programmable Fe Deskews Control & Data Interface Bunch/Event Counters Coarse Deskew Functions Figure 1 Timg receiver chip block diagram CLK φ1 CLKφ2 L1 Accept Bunch No/ Event No Bcast CMDS/ Sub-address As shown Figure 1, the ASIC receives the TTC data the form of an electrical signal from the optical preamplifier. Due to the optical power levels detected by the preamplifier, this signal needs to be amplified to CMOS levels before it can be used for clock recovery, data decodg demultiplexg. The unit marked as Lear Receiver Figure 1 implements that function. Signal level detection automatic ga control are also taken care of side this block. After the signal is restored to CMOS levels, it is fed to the Clock Extraction the Data Decoder/ Demultiplexer units where the LHC system clock is recovered with mimum jitter, the trigger (A) data (B) channels are separated. The recovered clock is then fed to the Programmable Fe Deskew unit where two different clock phases, synchronous with the LHC system clock, are generated. The phases of the two clocks can be controlled dependently via comms on the B channel. The Programmable Fe Deskew unit allows the two clock phases to be changed steps of 14 ps between 25 ns. The TTCrx control logic consists of three major blocks. The first block contas the ternal configuration status registers implements the logic necessary to read a 14 bit number from an external serial configuration PROM that supplies the TTCrx ASIC with its unique system address. The Data Error

logic this block also implements a functional subset of the JTAG/IEEE 1149.1 stard [4] providg the capability for the ASIC to be used board-level connectivity tests. The second block identifies the trigger data channels constantly monitors the data channel B for transmission errors. It deserializes the received data decides if these are addressed to the IC itself or to some external addressable or common space. Fally, the third functional block implements two dependently programmed coarse deskewg functions for the first-level trigger signal the broadcast comms. The related control registers can be programmed by dividually addressed data transmitted over the B channel. Both first-level trigger broadcast comms can be deskewed over a range of 16 bunchcrossg tervals. 2.1 The Lear Receiver The signal received by the optical receiver preamplifier is amplified converted to CMOS levels by the Lear Receiver unit whose block diagram is given Figure 2. Ga Controlled Amplifier Discrimator Sce the biphase mark codg scheme is characterised by constant phase versions, it is not possible to recover the clock directly from the data with some kd of preprocessg of the signal or a lockg acquisition aid mechanism. Typically, circuits designed to recover the clock from a BPM signal require an external quartz oscillator to serve as a timg reference the itial phase of the lock acquisition process. However, for the application question, it was undesirable to adopuch a solution. To solve the lock acquisition problem, a strategy was adopted where the signal of the discrimator is first fed to a sequential circuit that generates a reference clock signal from the BPM encoded data. This signal is then filtered by a narrow bwidth Phase Locked Loop (PLL) that generates the desired low jitter reference clock. A simplified diagram of the clock reference generator circuit is shown Figure 3. A) B- Delay Locked Loop t p DLL control voltage a R S t p ÈÀÀÉDT A Peak Detector a Ref. Figure 2 TTCrx Lear Receiver unit block diagram As shown the above diagram, the lear part of the TTCrx is composed of a Ga Controlled Amplifier (GCA), a peak detector, a loop amplifier, a loop filter (tegrator) a discrimator. The signal path this design is fully differential with the conversion to sgle ended takg place only the lastage of the discrimator. To achieve a ga bwidth product compatible with the system requirements, usg the relatively slow 1µm CMOS process, the ga controlled amplifier was designed as a cascade of six identical ga stages. The design is similar to that reported [5], but with the triode voltage controlled resistors replaced by learised floatg resistors [6]. The put of the ga controlled amplifier is converted to CMOS logic levels by the discrimator. A moderate amount of positive feedback is used this circuit to achieve fast operation while at the same time avoidg undesirable hysteresis effects [7]. Fally, sce the expected optical signal power variations are maly due to fibre darkeng under radiation to the laser transmitter ageg, the ga control loop was designed with a long time constant. 2.2 Clock Data Extraction R S Figure 3 A) Clock reference generator circuit B) Timg diagram In this circuit, at the put of the XOR gate (pot a Figure 3), rectangular pulses are generated at each transition of the puignal. The sequential circuit, composed of the AND gate, the RS flip-flop the time delays t p, suppresses the pulses generated by the half bit terval transitions of the BPM encoded data. In this way, at the put, a periodic signal of twice the LHC clock frequency is generated. After division by two, this signal is used as time reference by the narrow b PLL as illustrated Figure 4. Note that, after itialisation, the reference signal always aligns with the data bit boundaries once the first data zero is detected 1. The correct operation of this circuit depends strongly on the circuit s ability to correctly set the time delay. The precision required is superior to what can be expected from process parameters temperature variations. To overcome this problem, a Delay Locked Loop (DLL) is used 1 The itialisation circuit has been omitted from the figure for simplicity.

to regulate the delay. A special Phase Detector (PD) was designed which allows the DLL to lock directly on the BPM encoded data. When the delay is built controlled the same way as the delay cha the DLL, it is possible to obta a good precision. clock signal but this time t (N-1) = T/(N-1) seconds apart. By appropriate put tap selection each DLL the clock signal can be shifted with a time resolution that is given by: t = t (N-1) - t N N Phase Detector Clock Reference Generator D U/D R U V D Charge Pump (1) Charge Pump (2) P I VCO Φ4 Φ3 Φ2 Φ1 Φ MUX N-1 Loop Filter sel Phase Detector. Figure 4 Phase Frequency Locked Loop block diagram MUX Loop Filter sel The Phase Frequency Locked Loop (PFLL) represented Figure 4 uses separate frequency phase detectors the control loop. The loop is designed such a way that the frequency detector domates the PFLL behaviour when far away from lock. In this case, the PFLL has a frequency sensitive operation. When lock, the loop behaviour is dictated by the phase detector alone. Sce this last has a better phase resolution than the frequency detector, it is possible to obta a frequency sensitive PLL while, at the same time, matag good phase resolution. This mimises the jitter of the recovered clock while keepg the loop operation tolerant to process temperature variations with the need for external trimmg components. The PFLL uses a three state phase detector [8] for frequency acquisition a D flip-flop type PD [9,1] for phase acquisition trackg. Data decodg demultiplexg of the trigger data channels are made side the Data Decoder/Demultiplexer unit usg the four-phase clock signals generated the clock recovery circuit. 2.3 Fe Clock Deskewg Function The recovered clock is fed to the Programmable Fe Deskew unit. There, two dependently controlled clock signals are generated made externally available. The two clock signals are controlled usg data transmitted over the TTC distribution system. They can be programmed steps of 14 ps up to a maximum delay correspondg to a bunch crossg terval. The Programmable Fe Deskew unit contas two identical programmable delay generators to produce the two dependent clocks. In order to obta a sub-gate delay resolution a novel architecture based on two staggered delay locked loops was used. Its prciple of operation can be easily understood with reference to Figure 5. In this scheme, the first DLL generates N replicas of the recovered clock each one of them delayed by t N = T/N seconds from the previous one, where T is the recovered clock period. One of these signals is selected as the put to the followg delay locked loop. The second DLL generates N-1 copies of the. Figure 5 Programmable sub-gate resolution delay generator In the present case, N=16 was used, resultg a mimum combed time step of 14. ps The scheme presented here has the advantages of providg well defed time steps of beg self calibratg sce it uses the LHC recovered system clock as the timg reference. The circuit operation details of the DLL used to implement the programmable delay generators have been previously described [1]. 2.4. Digital Control Logic Functionality Each TTCrx IC is identified the distribution network by a unique 14-bit channel Identification (ID) number. This number is read from the serial PROM at power up or after a reload ID broadcast comm is received. The ASIC control logic identifies the A B channels, deserializes the data the B channel contuously monitors it to look for the presence of its ID channel number. Data channel B can be of two types [1,2]: Broadcast comms dividually addressed data/comms. Broadcast comms are used to distribute messages to all TTC receivers the system. When detected, these comms are executed by all the timg ASICs. These messages are also made available to the side electronics. The dividually addressed data/comms are implemented the TTC system to transmit user-defed data comms over the network. These comms have two distct modes of operation. In the first mode, they are aimed at the TTC receivers themselves their user-defed content is used to control the receiver s operation. In the second mode, the data are tended for the external electronics. In this case, both the data sub-address contents of the received comms are made externally available. Both the broadcast the dividually addressed comms are transmitted over the TTC network usg a frame format

that has been specified reference [3]. The frame structure contas several fields to control the transmission cludes a field which several redundant bits are serted for error detection correction. The codg scheme used is a stard Hammg code with the capability of double error detection sgle bit error correction. Error detection correction is implemented for both the broadcast the dividually addressed comms. The TTCrx contas several ternal registers used for control monitorg of its operation. These registers are: The Configuration register, Control register, Coarse Delay register, Fe Delay registers, Bunch Counter register, Event Counter register, Sgle Bit Error Counter Double Bit/Frame Error counter. The Configuration register contas the configuration bits read durg itialisation from the external serial PROM. It is used to store the 14-bit chip ID to set up some of the different ASIC operation test modes. The Control register is used to mimise the IC power consumption by allowg the disablg of some of the chip functionality applications that do not require it. For stance, the Event Bunch counters the Address Data buses can be disabled if not required by the external electronics. The Coarse Delay register holds the deskewg parameters for the First Level Trigger Accept (L1A) the Bunch Counter Reseignals. The contents of this register conjunction with that of the Fe Delay register affects the total amount of deskewg. Sce the same deskewg is applied to the L1A signal the broadcast comms, deskewg of the latter ones will also have to be performed at the source of the TTC system to compensate for the time necessary to transmit decode these comms. The Fe Delay registers hold the deskewg parameters that control the programmable delay generator discussed previously. When combed with the coarse deskewg functions, a compensation range of 16 bunch-crossg tervals is obtaed. This allows a substantial marg beyond the possible maximum variations due to differences timeof-flight optical fibre path lengths the detectors. The Bunch Counter the Event Counter registers are free runng counters that are cremented by the recovered clock the L1A signals, respectively. These counters can be reset by specially defed broadcast comms. The Bunch Counter register content, which is a 12-bit number, is normally available to the side logic. However, durg the two clock cycles followg a trigger accept, the 24-bit Event Number register content can optionally be made available to the side electronics on the same 12 put les. Fally, the Sgle Bit Error the Double Bit/Frame Error counters are used to keep track of the number of errors occurrg durg data reception. Sce the receiver Hammg decoder is capable of fully recoverg from sgle bit errors, the data are accepted after correction the Sgle Bit Error register cremented. When a double bit error is recognised by the receiver logic or a frame error is detected, the data are ignored the contents of the Double Bit/Frame Error register cremented. The contents of the ternal error counters are dumped on the external data bus when an error dump broadcast comm is issued by the central TTC system. 3. MEASUREMENTS In this section we present the measurement results for the clock recoverg fe deskewg functions. Measurement results concerng the analogue functions of the IC have already been reported a previous publication [12]. 3.1 Clock Recoverg Fe Deskew Function The IC was connected to a 11 KΩ photodetector-preamplifier the jitter of the recovered clock measured. The put optical signal was a biphase mark encoded PRBS provided by the TTC transmitter. Figure 6 shows the measurement results for the recovered clock jitter at the put of the reference generator circuit (doted le), at the put of the PLL (solid le) at the put of the programmable delay generator (dashed le). Measured rms jitter (ps) 35 3 25 2 15 1 5 TTCrx Jitter Ref. Gen. 22 2 18 16 14 12 1 Input optical power (dbm) PLL DLL Figure 6 Measured RMS jitter From this figure it can be seen that the jitter of the recovered clock is always less than 8 ps RMS over the whole operation range. This figure also shows that the programmable delay generator is not troducg any significant amount of jitter that the PFLL is effectively filterg the jitter of the signal generated by the reference generator circuit. The learity of the of the delay generator was also measured the results are shown Figure 7 Figure 8. The delay generator allows the clock phase to be shifted steps of.1 ns up to a maximum of 25 ns with an RMS error of 92 ps. It is, however, necessary to mention that the learity of the programmable delay generator is strongly fluenced by the

presence of parasitic package ductance. The results reported here were obtaed with the IC directly bonded to the PCB to mimise ductance. For a common package (PGA 1) the RMS error degrades to 2 ps. Different packagg solutions for the TTCrx are now beg studied order to mimise this effect. Measured delay (ns) 25 2 15 1 5 PCB bonded chip 5 1 15 2 25 Programmed delay (ns) Figure 7 Measured delay as function of the programmed delay 6 5 4 3 2 1 RMS =.915ns PP =.4885ns PCB bonded chip.6.4.2.2.4.6 Measured delay error (ns) Figure 8 Delay error histogram 4. CONCLUSION An ASIC receiver to be used with the LHC Timg, Trigger Control distribution system was designed, fabricated tested. The receiver is tended to recover the LHC reference clock to distribute it together with first level trigger decisions to the detector electronics properly deskewed time. Additionally, the receiver allows broadcast addressed comms to be transmitted over the network. The measurement results show that it is possible to recover the LHC clock from the TTC multiplexed encoded data with an RMS jitter better than 8 ps to control its phase steps of.1 ns with an RMS error smaller than 1 ps. 5. ACKNOWLEDGEMENTS The authors wish to acknowledge Bruce G. Taylor for valuable discussions on this work Ernst Murer for the preparation of the teset-up for helpg with the measurements. REFERENCES [1] B. G. Taylor, Timg, Trigger Control (TTC) Systems for LHC Detectors, CERN/ECP http://www.cern.ch/ttc/ tro.html. [2] B. G. Taylor, TTC Distribution, Proceedgs of the First Workshop on Electronics for LHC Experiments, Lisbon, 11-15 September 1995, (CERN/LHCC/95-56), pp. 18-184. [3] J. Christiansen, A. Marchioro P. Moreira, TTCrx Reference Manual A Timg, Trigger Control Distribution Receiver ASIC for LHC Detectors, CERN/RD12 workg document. [4] C. M. Maunder R. E. Tulloss, The Test Access Port Boundary-Scan Architecture, IEEE Computer Society Press, 199 [5] T. H. Hu P. R. Gray, A Monolithic 48 Mb/s Parallel AGC/Decision/Clock-Recovery Circuit 1.2- µm CMOS, J. Solid-State Circuits, vol. SC-28, pp. 1314-132, December 1993. [6] M. Banu Y. Tsividis, Floatg Voltage-Controlled Resistors CMOS Technology, Electronics Letters, vol. 18, pp. 678-679, July 1982. [7] D. J. Allstot, A Precision Variable-Supply CMOS Comparator, J. Solid-State Circuits, vol. SC-17, pp. 18-179, December 1982. [9] M. Soyuer R. Meyer, Frequency Limitations of a Conventional Phase-Frequency Detector, J. Solid-State Circuits, vol. SC-25, pp. 119-122, August 199. [1]M. Johnson E. Hudson, A Variable Delay Le for CPU Co-Processor Synchronization, J. Solid-State Circuits, vol. SC-23, pp. 1218-1223, October 1988. [11] J. Christiansen, An Integrated CMOS.15ns Digital Timg Generator for TDC s Clock Distribution Systems, IEEE Trans. Nuclear Science, vol. 42, pp. 753-757, August 1995. [12] J. Christiansen, A. Marchioro, P. Moreira, A. Sancho, Receiver ASIC for Timg, Trigger Control Distribution LHC Experiments, Trans. Nuclear Science, vol. 43, pp. 1773 1777, June 1996.